* [U-Boot] [v2 1/2] ata: fsl_sata: Add DM support for Freescale PowerPC SATA driver
@ 2019-10-23 10:56 Peng Ma
2019-10-23 10:56 ` [U-Boot] [v2 2/2] ata: sata_sil: Add DM support for Silicon sata driver Peng Ma
0 siblings, 1 reply; 3+ messages in thread
From: Peng Ma @ 2019-10-23 10:56 UTC (permalink / raw)
To: u-boot
Add DM support for Freescale PowerPC sata driver used for PowerPC T series SoCs,
CONFIG_BLK needs to be enabled on these platforms. It adds the SATA controller as
AHCI device, which is strictly speaking not correct, as the controller is not AHCI
compatible, But the U-Boot AHCI uclass interface enables the usage of this DM driver,
Also fix below warning while PowerPC T series boards compilation,
===================== WARNING ======================"
This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
enabled. Please update the storage controller driver to use"
CONFIG_AHCI before the v2019.07 release."
Failure to update by the deadline may result in board removal."
See doc/driver-model/MIGRATION.txt for more info."
===================================================="
Signed-off-by: Peng Ma <peng.ma@nxp.com>
---
Changed for v2:
- Rewrite the subject and description
- Copy lba48 for new block device
arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 --
drivers/ata/Kconfig | 1 +
drivers/ata/fsl_sata.c | 307 ++++++++++++++++++++++++++----------
drivers/ata/fsl_sata.h | 13 +-
4 files changed, 233 insertions(+), 98 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index cac9280..9c12c87 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -1023,16 +1023,6 @@ void arch_preboot_os(void)
mtmsr(msr);
}
-#if defined(CONFIG_SATA) && defined(CONFIG_FSL_SATA)
-int sata_initialize(void)
-{
- if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
- return __sata_initialize();
-
- return 1;
-}
-#endif
-
void cpu_secondary_init_r(void)
{
#ifdef CONFIG_U_QE
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 87636ae..57121f6 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -87,6 +87,7 @@ config DWC_AHSATA_AHCI
config FSL_SATA
bool "Enable Freescale SATA controller driver support"
select LIBATA
+ select AHCI if BLK
help
Enable this driver to support the SATA controller found in
some Freescale PowerPC SoCs.
diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c
index e70a515..3261c10 100644
--- a/drivers/ata/fsl_sata.c
+++ b/drivers/ata/fsl_sata.c
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
+ * Copyright 2019 NXP
+ * Author: Dave Liu <daveliu@freescale.com>
*/
#include <common.h>
@@ -16,6 +17,11 @@
#include <sata.h>
#include "fsl_sata.h"
+#if CONFIG_IS_ENABLED(BLK)
+#include <dm.h>
+#include <ahci.h>
+#include <blk.h>
+#else
#ifndef CONFIG_SYS_SATA1_FLAGS
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#endif
@@ -35,6 +41,7 @@ static struct fsl_sata_info fsl_sata_info[] = {
{0, 0},
#endif
};
+#endif
static inline void sdelay(unsigned long sec)
{
@@ -74,7 +81,11 @@ static int ata_wait_register(unsigned __iomem *addr, u32 mask,
return (i < timeout_msec) ? 0 : -1;
}
+#if !CONFIG_IS_ENABLED(BLK)
int init_sata(int dev)
+#else
+static int init_sata(struct fsl_ata_priv *priv, int dev)
+#endif
{
u32 length, align;
cmd_hdr_tbl_t *cmd_hdr;
@@ -110,13 +121,18 @@ int init_sata(int dev)
/* Zero all of the device driver struct */
memset((void *)sata, 0, sizeof(fsl_sata_t));
- /* Save the private struct to block device struct */
- sata_dev_desc[dev].priv = (void *)sata;
-
- snprintf(sata->name, 12, "SATA%d", dev);
+ snprintf(sata->name, 12, "SATA%d:\n", dev);
/* Set the controller register base address to device struct */
+#if !CONFIG_IS_ENABLED(BLK)
+ sata_dev_desc[dev].priv = (void *)sata;
reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
+ sata->dma_flag = fsl_sata_info[dev].flags;
+#else
+ reg = (fsl_sata_reg_t *)(priv->base + priv->offset * dev);
+ sata->dma_flag = priv->flag;
+ priv->fsl_sata = sata;
+#endif
sata->reg_base = reg;
/* Allocate the command header table, 4 bytes aligned */
@@ -479,34 +495,16 @@ static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
return -1;
}
-static void fsl_sata_identify(int dev, u16 *id)
-{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d, *cfis = &h2d;
-
- memset(cfis, 0, sizeof(struct sata_fis_h2d));
-
- cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
- cfis->pm_port_c = 0x80; /* is command */
- cfis->command = ATA_CMD_ID_ATA;
-
- fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
- ata_swap_buf_le16(id, ATA_ID_WORDS);
-}
-
-static void fsl_sata_xfer_mode(int dev, u16 *id)
+static void fsl_sata_xfer_mode(fsl_sata_t *sata, u16 *id)
{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
-
sata->pio = id[ATA_ID_PIO_MODES];
sata->mwdma = id[ATA_ID_MWDMA_MODES];
sata->udma = id[ATA_ID_UDMA_MODES];
debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
}
-static void fsl_sata_set_features(int dev)
+static void fsl_sata_set_features(fsl_sata_t *sata)
{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
u8 udma_cap;
@@ -533,9 +531,9 @@ static void fsl_sata_set_features(int dev)
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
}
-static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
+static u32 fsl_sata_rw_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt, u8 *buffer,
+ int is_write)
{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
u32 block;
@@ -558,9 +556,8 @@ static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_wr
return blkcnt;
}
-static void fsl_sata_flush_cache(int dev)
+static void fsl_sata_flush_cache(fsl_sata_t *sata)
{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
@@ -572,9 +569,9 @@ static void fsl_sata_flush_cache(int dev)
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
}
-static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
+static u32 fsl_sata_rw_cmd_ext(fsl_sata_t *sata, u32 start, u32 blkcnt,
+ u8 *buffer, int is_write)
{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
u64 block;
@@ -602,10 +599,9 @@ static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int i
return blkcnt;
}
-static u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer,
- int is_write)
+static u32 fsl_sata_rw_ncq_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
+ u8 *buffer, int is_write)
{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
int ncq_channel;
u64 block;
@@ -646,9 +642,8 @@ static u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer,
return blkcnt;
}
-static void fsl_sata_flush_cache_ext(int dev)
+static void fsl_sata_flush_cache_ext(fsl_sata_t *sata)
{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
@@ -660,10 +655,8 @@ static void fsl_sata_flush_cache_ext(int dev)
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
}
-static void fsl_sata_init_wcache(int dev, u16 *id)
+static void fsl_sata_init_wcache(fsl_sata_t *sata, u16 *id)
{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
-
if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
sata->wcache = 1;
if (ata_id_has_flush(id))
@@ -672,26 +665,8 @@ static void fsl_sata_init_wcache(int dev, u16 *id)
sata->flush_ext = 1;
}
-static int fsl_sata_get_wcache(int dev)
-{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
- return sata->wcache;
-}
-
-static int fsl_sata_get_flush(int dev)
-{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
- return sata->flush;
-}
-
-static int fsl_sata_get_flush_ext(int dev)
-{
- fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
- return sata->flush_ext;
-}
-
-static u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
- const void *buffer, int is_write)
+static u32 ata_low_level_rw_lba48(fsl_sata_t *sata, u32 blknr, lbaint_t blkcnt,
+ const void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
@@ -704,18 +679,22 @@ static u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
max_blks = ATA_MAX_SECTORS_LBA48;
do {
if (blks > max_blks) {
- if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
- fsl_sata_rw_cmd_ext(dev, start, max_blks, addr, is_write);
+ if (sata->dma_flag != FLAGS_FPDMA)
+ fsl_sata_rw_cmd_ext(sata, start, max_blks, addr,
+ is_write);
else
- fsl_sata_rw_ncq_cmd(dev, start, max_blks, addr, is_write);
+ fsl_sata_rw_ncq_cmd(sata, start, max_blks, addr,
+ is_write);
start += max_blks;
blks -= max_blks;
addr += ATA_SECT_SIZE * max_blks;
} else {
- if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
- fsl_sata_rw_cmd_ext(dev, start, blks, addr, is_write);
+ if (sata->dma_flag != FLAGS_FPDMA)
+ fsl_sata_rw_cmd_ext(sata, start, blks, addr,
+ is_write);
else
- fsl_sata_rw_ncq_cmd(dev, start, blks, addr, is_write);
+ fsl_sata_rw_ncq_cmd(sata, start, blks, addr,
+ is_write);
start += blks;
blks = 0;
addr += ATA_SECT_SIZE * blks;
@@ -725,7 +704,7 @@ static u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
return blkcnt;
}
-static u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt,
+static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt,
const void *buffer, int is_write)
{
u32 start, blks;
@@ -739,12 +718,12 @@ static u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt,
max_blks = ATA_MAX_SECTORS;
do {
if (blks > max_blks) {
- fsl_sata_rw_cmd(dev, start, max_blks, addr, is_write);
+ fsl_sata_rw_cmd(sata, start, max_blks, addr, is_write);
start += max_blks;
blks -= max_blks;
addr += ATA_SECT_SIZE * max_blks;
} else {
- fsl_sata_rw_cmd(dev, start, blks, addr, is_write);
+ fsl_sata_rw_cmd(sata, start, blks, addr, is_write);
start += blks;
blks = 0;
addr += ATA_SECT_SIZE * blks;
@@ -757,38 +736,81 @@ static u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt,
/*
* SATA interface between low level driver and command layer
*/
+#if !CONFIG_IS_ENABLED(BLK)
ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
- u32 rc;
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
+#else
+static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+{
+ struct fsl_ata_priv *priv = dev_get_platdata(dev);
+ fsl_sata_t *sata = priv->fsl_sata;
+#endif
+ u32 rc;
if (sata->lba48)
- rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
+ rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
+ READ_CMD);
else
- rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
+ rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
+ READ_CMD);
return rc;
}
+#if !CONFIG_IS_ENABLED(BLK)
ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
- u32 rc;
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
+#else
+static ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
+{
+ struct fsl_ata_priv *priv = dev_get_platdata(dev);
+ fsl_sata_t *sata = priv->fsl_sata;
+#endif
+ u32 rc;
if (sata->lba48) {
- rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
- if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev))
- fsl_sata_flush_cache_ext(dev);
+ rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
+ WRITE_CMD);
+ if (sata->wcache && sata->flush_ext)
+ fsl_sata_flush_cache_ext(sata);
} else {
- rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
- if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush(dev))
- fsl_sata_flush_cache(dev);
+ rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
+ WRITE_CMD);
+ if (sata->wcache && sata->flush)
+ fsl_sata_flush_cache(sata);
}
return rc;
}
+static void fsl_sata_identify(fsl_sata_t *sata, u16 *id)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+ cfis->command = ATA_CMD_ID_ATA;
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
+ ata_swap_buf_le16(id, ATA_ID_WORDS);
+}
+
+#if !CONFIG_IS_ENABLED(BLK)
int scan_sata(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
+#else
+static int scan_sata(struct udevice *dev)
+{
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct fsl_ata_priv *priv = dev_get_platdata(dev);
+ fsl_sata_t *sata = priv->fsl_sata;
+#endif
+
unsigned char serial[ATA_ID_SERNO_LEN + 1];
unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
unsigned char product[ATA_ID_PROD_LEN + 1];
@@ -806,23 +828,19 @@ int scan_sata(int dev)
}
/* Identify device to get information */
- fsl_sata_identify(dev, id);
+ fsl_sata_identify(sata, id);
/* Serial number */
ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
- memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
/* Firmware version */
ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
- memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
/* Product model */
ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
- memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
/* Totoal sectors */
n_sectors = ata_id_n_sectors(id);
- sata_dev_desc[dev].lba = (u32)n_sectors;
#ifdef CONFIG_LBA48
/* Check if support LBA48 */
@@ -833,21 +851,136 @@ int scan_sata(int dev)
debug("Device supports LBA28\n\r");
#endif
+#if !CONFIG_IS_ENABLED(BLK)
+ memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
+ memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
+ memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
+ sata_dev_desc[dev].lba = (u32)n_sectors;
+#ifdef CONFIG_LBA48
+ sata_dev_desc[dev].lba48 = sata->lba48;
+#endif
+#else
+ memcpy(desc->product, serial, sizeof(serial));
+ memcpy(desc->revision, firmware, sizeof(firmware));
+ memcpy(desc->vendor, product, sizeof(product));
+ desc->lba = n_sectors;
+#ifdef CONFIG_LBA48
+ desc->lba48 = sata->lba48;
+#endif
+#endif
+
/* Get the NCQ queue depth from device */
sata->queue_depth = ata_id_queue_depth(id);
/* Get the xfer mode from device */
- fsl_sata_xfer_mode(dev, id);
+ fsl_sata_xfer_mode(sata, id);
/* Get the write cache status from device */
- fsl_sata_init_wcache(dev, id);
+ fsl_sata_init_wcache(sata, id);
/* Set the xfer mode to highest speed */
- fsl_sata_set_features(dev);
+ fsl_sata_set_features(sata);
+
#ifdef DEBUG
- fsl_sata_identify(dev, id);
ata_dump_id(id);
#endif
free((void *)id);
return 0;
}
+
+#if CONFIG_IS_ENABLED(BLK)
+static const struct blk_ops sata_fsl_blk_ops = {
+ .read = sata_read,
+ .write = sata_write,
+};
+
+U_BOOT_DRIVER(sata_fsl_driver) = {
+ .name = "sata_fsl_blk",
+ .id = UCLASS_BLK,
+ .ops = &sata_fsl_blk_ops,
+ .platdata_auto_alloc_size = sizeof(struct fsl_ata_priv),
+};
+
+static int fsl_ata_ofdata_to_platdata(struct udevice *dev)
+{
+ struct fsl_ata_priv *priv = dev_get_priv(dev);
+
+ priv->number = dev_read_u32_default(dev, "sata-number", -1);
+ priv->flag = dev_read_u32_default(dev, "sata-fpdma", -1);
+ priv->offset = dev_read_u32_default(dev, "sata-offset", -1);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int fsl_ata_probe(struct udevice *dev)
+{
+ struct fsl_ata_priv *blk_priv, *priv;
+ struct udevice *blk;
+ char sata_name[10];
+ int nr_ports;
+ int ret;
+ int i;
+
+ priv = dev_get_priv(dev);
+ nr_ports = priv->number;
+ nr_ports = min(nr_ports, CONFIG_SYS_SATA_MAX_DEVICE);
+
+ for (i = 0; i < nr_ports; i++) {
+ snprintf(sata_name, sizeof(sata_name), "fsl_sata%d", i);
+ ret = blk_create_devicef(dev, "sata_fsl_blk", sata_name,
+ IF_TYPE_SATA, -1, 512, 0, &blk);
+ if (ret) {
+ debug("Can't create device\n");
+ return ret;
+ }
+
+ /* Init SATA port */
+ ret = init_sata(priv, i);
+ if (ret) {
+ debug("%s: Failed to init sata\n", __func__);
+ return ret;
+ }
+
+ blk_priv = dev_get_platdata(blk);
+ blk_priv->fsl_sata = priv->fsl_sata;
+ /* Scan SATA port */
+ ret = scan_sata(blk);
+ if (ret) {
+ debug("%s: Failed to scan bus\n", __func__);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int sata_fsl_scan(struct udevice *dev)
+{
+ /* Nothing to do here */
+
+ return 0;
+}
+
+struct ahci_ops sata_fsl_ahci_ops = {
+ .scan = sata_fsl_scan,
+};
+
+static const struct udevice_id fsl_ata_ids[] = {
+ { .compatible = "fsl,pq-sata-v2" },
+ { }
+};
+
+U_BOOT_DRIVER(fsl_ahci) = {
+ .name = "fsl_ahci",
+ .id = UCLASS_AHCI,
+ .of_match = fsl_ata_ids,
+ .ops = &sata_fsl_ahci_ops,
+ .ofdata_to_platdata = fsl_ata_ofdata_to_platdata,
+ .probe = fsl_ata_probe,
+ .priv_auto_alloc_size = sizeof(struct fsl_ata_priv),
+};
+#endif
diff --git a/drivers/ata/fsl_sata.h b/drivers/ata/fsl_sata.h
index a4ee83d..5b9daa7 100644
--- a/drivers/ata/fsl_sata.h
+++ b/drivers/ata/fsl_sata.h
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007-2008 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
+ * Copyright 2019 NXP
+ * Author: Dave Liu <daveliu@freescale.com>
*/
#ifndef __FSL_SATA_H__
@@ -318,4 +319,14 @@ typedef struct fsl_sata {
#define READ_CMD 0
#define WRITE_CMD 1
+#if CONFIG_IS_ENABLED(BLK)
+struct fsl_ata_priv {
+ u32 base;
+ u32 flag;
+ u32 number;
+ u32 offset;
+ fsl_sata_t *fsl_sata;
+};
+#endif
+
#endif /* __FSL_SATA_H__ */
--
2.9.5
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [v2 2/2] ata: sata_sil: Add DM support for Silicon sata driver
2019-10-23 10:56 [U-Boot] [v2 1/2] ata: fsl_sata: Add DM support for Freescale PowerPC SATA driver Peng Ma
@ 2019-10-23 10:56 ` Peng Ma
2019-11-18 9:02 ` Priyanka Jain
0 siblings, 1 reply; 3+ messages in thread
From: Peng Ma @ 2019-10-23 10:56 UTC (permalink / raw)
To: u-boot
Add DM support for Silicon(SIL3131 / SIL3132 / SIL3124) sata driver as
few of the PowerPC platforms such as P series based boards need to
use SATA_SIL with DM,
Also fix below warning while PowerPC P series boards compilation,
===================== WARNING ======================"
This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
enabled. Please update the storage controller driver to use"
CONFIG_AHCI before the v2019.07 release."
Failure to update by the deadline may result in board removal."
See doc/driver-model/MIGRATION.txt for more info."
===================================================="
Signed-off-by: Peng Ma <peng.ma@nxp.com>
---
Changed for v2:
- Rewrite the subject and description
drivers/ata/Kconfig | 1 +
drivers/ata/sata_sil.c | 539 +++++++++++++++++++++++++++++++------------------
drivers/ata/sata_sil.h | 14 +-
3 files changed, 357 insertions(+), 197 deletions(-)
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 57121f6..fe589d3 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -110,6 +110,7 @@ config SATA_MV
config SATA_SIL
bool "Enable Silicon Image SIL3131 / SIL3132 / SIL3124 SATA driver support"
select LIBATA
+ select AHCI if BLK
help
Enable this driver to support the SIL3131, SIL3132 and SIL3124
SATA controllers.
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index a8598d9..20502b3 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
* Author: Tang Yuantian <b29983@freescale.com>
*/
@@ -14,18 +15,29 @@
#include <sata.h>
#include <libata.h>
#include <sata.h>
+
+#if CONFIG_IS_ENABLED(BLK)
+#include <dm.h>
+#include <blk.h>
+#endif
+
#include "sata_sil.h"
-/* Convert sectorsize to wordsize */
-#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
+/* just compatible ahci_ops */
+struct sil_ops {
+ int *rev0;
+ int *rev1;
+ int (*scan)(struct udevice *dev);
+};
+
static struct sata_info sata_info;
static struct pci_device_id supported[] = {
- {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131},
- {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132},
- {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124},
+ { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131) },
+ { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132) },
+ { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124) },
{}
};
@@ -113,9 +125,9 @@ static int sil_init_port(void *port)
return 0;
}
-static void sil_read_fis(int dev, int tag, struct sata_fis_d2h *fis)
+static void sil_read_fis(struct sil_sata *sata, int tag,
+ struct sata_fis_d2h *fis)
{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
void *port = sata->port;
struct sil_prb *prb;
int i;
@@ -128,9 +140,9 @@ static void sil_read_fis(int dev, int tag, struct sata_fis_d2h *fis)
*dst++ = readl(src++);
}
-static int sil_exec_cmd(int dev, struct sil_cmd_block *pcmd, int tag)
+static int sil_exec_cmd(struct sil_sata *sata, struct sil_cmd_block *pcmd,
+ int tag)
{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
void *port = sata->port;
u64 paddr = virt_to_bus(sata->devno, pcmd);
u32 irq_mask, irq_stat;
@@ -164,9 +176,8 @@ static int sil_exec_cmd(int dev, struct sil_cmd_block *pcmd, int tag)
return rc;
}
-static int sil_cmd_set_feature(int dev)
+static int sil_cmd_set_feature(struct sil_sata *sata)
{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
struct sil_cmd_block cmdb, *pcmd = &cmdb;
struct sata_fis_d2h fis;
u8 udma_cap;
@@ -191,9 +202,9 @@ static int sil_cmd_set_feature(int dev)
if (udma_cap == ATA_UDMA3)
pcmd->prb.fis.sector_count = XFER_UDMA_3;
- ret = sil_exec_cmd(dev, pcmd, 0);
+ ret = sil_exec_cmd(sata, pcmd, 0);
if (ret) {
- sil_read_fis(dev, 0, &fis);
+ sil_read_fis(sata, 0, &fis);
printf("Err: exe cmd(0x%x).\n",
readl(sata->port + PORT_SERROR));
sil_sata_dump_fis(&fis);
@@ -203,9 +214,34 @@ static int sil_cmd_set_feature(int dev)
return 0;
}
-static int sil_cmd_identify_device(int dev, u16 *id)
+static void sil_sata_init_wcache(struct sil_sata *sata, u16 *id)
+{
+ if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
+ sata->wcache = 1;
+ if (ata_id_has_flush(id))
+ sata->flush = 1;
+ if (ata_id_has_flush_ext(id))
+ sata->flush_ext = 1;
+}
+
+static void sil_sata_set_feature_by_id(struct sil_sata *sata, u16 *id)
+{
+#ifdef CONFIG_LBA48
+ /* Check if support LBA48 */
+ if (ata_id_has_lba48(id)) {
+ sata->lba48 = 1;
+ debug("Device supports LBA48\n");
+ } else {
+ debug("Device supports LBA28\n");
+ }
+#endif
+
+ sil_sata_init_wcache(sata, id);
+ sil_cmd_set_feature(sata);
+}
+
+static int sil_cmd_identify_device(struct sil_sata *sata, u16 *id)
{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
struct sil_cmd_block cmdb, *pcmd = &cmdb;
struct sata_fis_d2h fis;
int ret;
@@ -220,9 +256,9 @@ static int sil_cmd_identify_device(int dev, u16 *id)
pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
pcmd->sge.flags = cpu_to_le32(SGE_TRM);
- ret = sil_exec_cmd(dev, pcmd, 0);
+ ret = sil_exec_cmd(sata, pcmd, 0);
if (ret) {
- sil_read_fis(dev, 0, &fis);
+ sil_read_fis(sata, 0, &fis);
printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
sil_sata_dump_fis(&fis);
return 1;
@@ -232,17 +268,16 @@ static int sil_cmd_identify_device(int dev, u16 *id)
return 0;
}
-static int sil_cmd_soft_reset(int dev)
+static int sil_cmd_soft_reset(struct sil_sata *sata)
{
struct sil_cmd_block cmdb, *pcmd = &cmdb;
- struct sil_sata *sata = sata_dev_desc[dev].priv;
struct sata_fis_d2h fis;
void *port = sata->port;
int ret;
/* put the port into known state */
if (sil_init_port(port)) {
- printf("SRST: port %d not ready\n", dev);
+ printf("SRST: port %d not ready\n", sata->id);
return 1;
}
@@ -252,9 +287,9 @@ static int sil_cmd_soft_reset(int dev)
pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
pcmd->prb.fis.pm_port_c = 0xf;
- ret = sil_exec_cmd(dev, &cmdb, 0);
+ ret = sil_exec_cmd(sata, &cmdb, 0);
if (ret) {
- sil_read_fis(dev, 0, &fis);
+ sil_read_fis(sata, 0, &fis);
printf("SRST cmd error.\n");
sil_sata_dump_fis(&fis);
return 1;
@@ -263,10 +298,9 @@ static int sil_cmd_soft_reset(int dev)
return 0;
}
-static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
- u8 *buffer, int is_write)
+static ulong sil_sata_rw_cmd(struct sil_sata *sata, ulong start, ulong blkcnt,
+ u8 *buffer, int is_write)
{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
struct sil_cmd_block cmdb, *pcmd = &cmdb;
struct sata_fis_d2h fis;
u64 block;
@@ -296,9 +330,9 @@ static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
pcmd->sge.flags = cpu_to_le32(SGE_TRM);
- ret = sil_exec_cmd(dev, pcmd, 0);
+ ret = sil_exec_cmd(sata, pcmd, 0);
if (ret) {
- sil_read_fis(dev, 0, &fis);
+ sil_read_fis(sata, 0, &fis);
printf("Err: rw cmd(0x%08x).\n",
readl(sata->port + PORT_SERROR));
sil_sata_dump_fis(&fis);
@@ -308,10 +342,9 @@ static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
return blkcnt;
}
-static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
- u8 *buffer, int is_write)
+static ulong sil_sata_rw_cmd_ext(struct sil_sata *sata, ulong start,
+ ulong blkcnt, u8 *buffer, int is_write)
{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
struct sil_cmd_block cmdb, *pcmd = &cmdb;
struct sata_fis_d2h fis;
u64 block;
@@ -344,9 +377,9 @@ static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
pcmd->sge.flags = cpu_to_le32(SGE_TRM);
- ret = sil_exec_cmd(dev, pcmd, 0);
+ ret = sil_exec_cmd(sata, pcmd, 0);
if (ret) {
- sil_read_fis(dev, 0, &fis);
+ sil_read_fis(sata, 0, &fis);
printf("Err: rw ext cmd(0x%08x).\n",
readl(sata->port + PORT_SERROR));
sil_sata_dump_fis(&fis);
@@ -356,8 +389,9 @@ static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
return blkcnt;
}
-static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
- const void *buffer, int is_write)
+static ulong sil_sata_rw_lba28(struct sil_sata *sata, ulong blknr,
+ lbaint_t blkcnt, const void *buffer,
+ int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
@@ -369,12 +403,12 @@ static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
max_blks = ATA_MAX_SECTORS;
do {
if (blks > max_blks) {
- sil_sata_rw_cmd(dev, start, max_blks, addr, is_write);
+ sil_sata_rw_cmd(sata, start, max_blks, addr, is_write);
start += max_blks;
blks -= max_blks;
addr += ATA_SECT_SIZE * max_blks;
} else {
- sil_sata_rw_cmd(dev, start, blks, addr, is_write);
+ sil_sata_rw_cmd(sata, start, blks, addr, is_write);
start += blks;
blks = 0;
addr += ATA_SECT_SIZE * blks;
@@ -384,8 +418,9 @@ static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
return blkcnt;
}
-static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
- const void *buffer, int is_write)
+static ulong sil_sata_rw_lba48(struct sil_sata *sata, ulong blknr,
+ lbaint_t blkcnt, const void *buffer,
+ int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
@@ -397,14 +432,14 @@ static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
max_blks = ATA_MAX_SECTORS_LBA48;
do {
if (blks > max_blks) {
- sil_sata_rw_cmd_ext(dev, start, max_blks,
- addr, is_write);
+ sil_sata_rw_cmd_ext(sata, start, max_blks,
+ addr, is_write);
start += max_blks;
blks -= max_blks;
addr += ATA_SECT_SIZE * max_blks;
} else {
- sil_sata_rw_cmd_ext(dev, start, blks,
- addr, is_write);
+ sil_sata_rw_cmd_ext(sata, start, blks,
+ addr, is_write);
start += blks;
blks = 0;
addr += ATA_SECT_SIZE * blks;
@@ -414,7 +449,7 @@ static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
return blkcnt;
}
-static void sil_sata_cmd_flush_cache(int dev)
+static void sil_sata_cmd_flush_cache(struct sil_sata *sata)
{
struct sil_cmd_block cmdb, *pcmd = &cmdb;
@@ -423,10 +458,10 @@ static void sil_sata_cmd_flush_cache(int dev)
pcmd->prb.fis.pm_port_c = (1 << 7);
pcmd->prb.fis.command = ATA_CMD_FLUSH;
- sil_exec_cmd(dev, pcmd, 0);
+ sil_exec_cmd(sata, pcmd, 0);
}
-static void sil_sata_cmd_flush_cache_ext(int dev)
+static void sil_sata_cmd_flush_cache_ext(struct sil_sata *sata)
{
struct sil_cmd_block cmdb, *pcmd = &cmdb;
@@ -435,54 +470,30 @@ static void sil_sata_cmd_flush_cache_ext(int dev)
pcmd->prb.fis.pm_port_c = (1 << 7);
pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
- sil_exec_cmd(dev, pcmd, 0);
-}
-
-static void sil_sata_init_wcache(int dev, u16 *id)
-{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
-
- if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
- sata->wcache = 1;
- if (ata_id_has_flush(id))
- sata->flush = 1;
- if (ata_id_has_flush_ext(id))
- sata->flush_ext = 1;
-}
-
-static int sil_sata_get_wcache(int dev)
-{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
-
- return sata->wcache;
-}
-
-static int sil_sata_get_flush(int dev)
-{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
-
- return sata->flush;
-}
-
-static int sil_sata_get_flush_ext(int dev)
-{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
-
- return sata->flush_ext;
+ sil_exec_cmd(sata, pcmd, 0);
}
/*
* SATA interface between low level driver and command layer
*/
+#if !CONFIG_IS_ENABLED(BLK)
ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
+ sil_sata_t *sata = (sil_sata_t *)sata_dev_desc[dev].priv;
+#else
+static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+{
+ struct sil_sata_priv *priv = dev_get_platdata(dev);
+ int port_number = priv->port_num;
+ sil_sata_t *sata = priv->sil_sata_desc[port_number];
+#endif
ulong rc;
if (sata->lba48)
- rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
+ rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, READ_CMD);
else
- rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
+ rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, READ_CMD);
return rc;
}
@@ -490,111 +501,48 @@ ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
/*
* SATA interface between low level driver and command layer
*/
+#if !CONFIG_IS_ENABLED(BLK)
ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
- struct sil_sata *sata = sata_dev_desc[dev].priv;
+ sil_sata_t *sata = (sil_sata_t *)sata_dev_desc[dev].priv;
+#else
+ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
+{
+ struct sil_sata_priv *priv = dev_get_platdata(dev);
+ int port_number = priv->port_num;
+ sil_sata_t *sata = priv->sil_sata_desc[port_number];
+#endif
ulong rc;
if (sata->lba48) {
- rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
- if (sil_sata_get_wcache(dev) && sil_sata_get_flush_ext(dev))
- sil_sata_cmd_flush_cache_ext(dev);
+ rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, WRITE_CMD);
+ if (sata->wcache && sata->flush_ext)
+ sil_sata_cmd_flush_cache_ext(sata);
} else {
- rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
- if (sil_sata_get_wcache(dev) && sil_sata_get_flush(dev))
- sil_sata_cmd_flush_cache(dev);
+ rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, WRITE_CMD);
+ if (sata->wcache && sata->flush)
+ sil_sata_cmd_flush_cache(sata);
}
return rc;
}
-/*
- * SATA interface between low level driver and command layer
- */
-int init_sata(int dev)
-{
- static int init_done, idx;
- pci_dev_t devno;
- u16 word;
-
- if (init_done == 1 && dev < sata_info.maxport)
- return 0;
-
- init_done = 1;
-
- /* Find PCI device(s) */
- devno = pci_find_devices(supported, idx++);
- if (devno == -1)
- return 1;
-
- pci_read_config_word(devno, PCI_DEVICE_ID, &word);
-
- /* get the port count */
- word &= 0xf;
-
- sata_info.portbase = sata_info.maxport;
- sata_info.maxport = sata_info.portbase + word;
- sata_info.devno = devno;
-
- /* Read out all BARs */
- sata_info.iobase[0] = (ulong)pci_map_bar(devno,
- PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
- sata_info.iobase[1] = (ulong)pci_map_bar(devno,
- PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
- sata_info.iobase[2] = (ulong)pci_map_bar(devno,
- PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
-
- /* mask out the unused bits */
- sata_info.iobase[0] &= 0xffffff80;
- sata_info.iobase[1] &= 0xfffffc00;
- sata_info.iobase[2] &= 0xffffff80;
-
- /* Enable Bus Mastering and memory region */
- pci_write_config_word(devno, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- /* Check if mem accesses and Bus Mastering are enabled. */
- pci_read_config_word(devno, PCI_COMMAND, &word);
- if (!(word & PCI_COMMAND_MEMORY) ||
- (!(word & PCI_COMMAND_MASTER))) {
- printf("Error: Can not enable MEM access or Bus Mastering.\n");
- debug("PCI command: %04x\n", word);
- return 1;
- }
-
- /* GPIO off */
- writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
- /* clear global reset & mask interrupts during initialization */
- writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
-
- return 0;
-}
-
-int reset_sata(int dev)
+#if !CONFIG_IS_ENABLED(BLK)
+static int sil_init_sata(int dev)
{
- return 0;
-}
-
-/*
- * SATA interface between low level driver and command layer
- */
-int scan_sata(int dev)
+#else
+static int sil_init_sata(struct udevice *uc_dev, int dev)
{
- unsigned char serial[ATA_ID_SERNO_LEN + 1];
- unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
- unsigned char product[ATA_ID_PROD_LEN + 1];
- struct sil_sata *sata;
+ struct sil_sata_priv *priv = dev_get_platdata(uc_dev);
+#endif
+ sil_sata_t *sata;
void *port;
- int cnt;
- u16 *id;
u32 tmp;
+ int cnt;
- if (dev >= sata_info.maxport) {
- printf("SATA#%d is not present\n", dev);
- return 1;
- }
+ printf("SATA#%d:\n", dev);
- printf("SATA#%d\n", dev);
port = (void *)sata_info.iobase[1] +
PORT_REGS_SIZE * (dev - sata_info.portbase);
@@ -646,69 +594,270 @@ int scan_sata(int dev)
return 1;
}
- sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
+ sata = (sil_sata_t *)malloc(sizeof(struct sil_sata));
if (!sata) {
printf("%d no memory.\n", dev);
return 1;
}
memset((void *)sata, 0, sizeof(struct sil_sata));
- /* turn on port interrupt */
- tmp = readl((void *)(sata_info.iobase[0] + HOST_CTRL));
- tmp |= (1 << (dev - sata_info.portbase));
- writel(tmp, (void *)(sata_info.iobase[0] + HOST_CTRL));
-
/* Save the private struct to block device struct */
+#if !CONFIG_IS_ENABLED(BLK)
sata_dev_desc[dev].priv = (void *)sata;
+#else
+ priv->sil_sata_desc[dev] = sata;
+ priv->port_num = dev;
+#endif
+ sata->id = dev;
sata->port = port;
sata->devno = sata_info.devno;
sprintf(sata->name, "SATA#%d", dev);
- sil_cmd_soft_reset(dev);
+ sil_cmd_soft_reset(sata);
tmp = readl(port + PORT_SSTATUS);
tmp = (tmp >> 4) & 0xf;
printf(" (%s)\n", sata_spd_string(tmp));
+ return 0;
+}
+
+#if !CONFIG_IS_ENABLED(BLK)
+/*
+ * SATA interface between low level driver and command layer
+ */
+int init_sata(int dev)
+{
+ static int init_done, idx;
+ pci_dev_t devno;
+ u16 word;
+
+ if (init_done == 1 && dev < sata_info.maxport)
+ goto init_start;
+
+ init_done = 1;
+
+ /* Find PCI device(s) */
+ devno = pci_find_devices(supported, idx++);
+ if (devno == -1)
+ return 1;
+
+ pci_read_config_word(devno, PCI_DEVICE_ID, &word);
+
+ /* get the port count */
+ word &= 0xf;
+
+ sata_info.portbase = 0;
+ sata_info.maxport = sata_info.portbase + word;
+ sata_info.devno = devno;
+
+ /* Read out all BARs */
+ sata_info.iobase[0] = (ulong)pci_map_bar(devno,
+ PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ sata_info.iobase[1] = (ulong)pci_map_bar(devno,
+ PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
+
+ /* mask out the unused bits */
+ sata_info.iobase[0] &= 0xffffff80;
+ sata_info.iobase[1] &= 0xfffffc00;
+
+ /* Enable Bus Mastering and memory region */
+ pci_write_config_word(devno, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Check if mem accesses and Bus Mastering are enabled. */
+ pci_read_config_word(devno, PCI_COMMAND, &word);
+ if (!(word & PCI_COMMAND_MEMORY) ||
+ (!(word & PCI_COMMAND_MASTER))) {
+ printf("Error: Can not enable MEM access or Bus Mastering.\n");
+ debug("PCI command: %04x\n", word);
+ return 1;
+ }
+
+ /* GPIO off */
+ writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
+ /* clear global reset & mask interrupts during initialization */
+ writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
+
+init_start:
+ return sil_init_sata(dev);
+}
+
+int reset_sata(int dev)
+{
+ return 0;
+}
+
+/*
+ * SATA interface between low level driver and command layer
+ */
+int scan_sata(int dev)
+{
+ sil_sata_t *sata = (sil_sata_t *)sata_dev_desc[dev].priv;
+#else
+static int scan_sata(struct udevice *blk_dev, int dev)
+{
+ struct blk_desc *desc = dev_get_uclass_platdata(blk_dev);
+ struct sil_sata_priv *priv = dev_get_platdata(blk_dev);
+ sil_sata_t *sata = priv->sil_sata_desc[dev];
+#endif
+ unsigned char serial[ATA_ID_SERNO_LEN + 1];
+ unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
+ unsigned char product[ATA_ID_PROD_LEN + 1];
+ u16 *id;
+
id = (u16 *)malloc(ATA_ID_WORDS * 2);
if (!id) {
printf("Id malloc failed\n");
- free((void *)sata);
return 1;
}
- sil_cmd_identify_device(dev, id);
+ sil_cmd_identify_device(sata, id);
-#ifdef CONFIG_LBA48
- /* Check if support LBA48 */
- if (ata_id_has_lba48(id)) {
- sata_dev_desc[dev].lba48 = 1;
- sata->lba48 = 1;
- debug("Device supports LBA48\n");
- } else
- debug("Device supports LBA28\n");
-#endif
+ sil_sata_set_feature_by_id(sata, id);
/* Serial number */
ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
- memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
/* Firmware version */
ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
- memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
/* Product model */
ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
- memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
+#if !CONFIG_IS_ENABLED(BLK)
+ memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
+ memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
+ memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
/* Totoal sectors */
sata_dev_desc[dev].lba = ata_id_n_sectors(id);
-
- sil_sata_init_wcache(dev, id);
- sil_cmd_set_feature(dev);
+#ifdef CONFIG_LBA48
+ sata_dev_desc[dev].lba48 = sata->lba48;
+#endif
+#else
+ memcpy(desc->product, serial, sizeof(serial));
+ memcpy(desc->revision, firmware, sizeof(firmware));
+ memcpy(desc->vendor, product, sizeof(product));
+ desc->lba = ata_id_n_sectors(id);
+#ifdef CONFIG_LBA48
+ desc->lba48 = sata->lba48;
+#endif
+#endif
#ifdef DEBUG
- sil_cmd_identify_device(dev, id);
ata_dump_id(id);
#endif
free((void *)id);
return 0;
}
+
+#if CONFIG_IS_ENABLED(BLK)
+static const struct blk_ops sata_sil_blk_ops = {
+ .read = sata_read,
+ .write = sata_write,
+};
+
+U_BOOT_DRIVER(sata_sil_driver) = {
+ .name = "sata_sil_blk",
+ .id = UCLASS_BLK,
+ .ops = &sata_sil_blk_ops,
+ .platdata_auto_alloc_size = sizeof(struct sil_sata_priv),
+};
+
+static int sil_pci_probe(struct udevice *dev)
+{
+ struct udevice *blk;
+ char sata_name[10];
+ pci_dev_t devno;
+ u16 word;
+ int ret;
+ int i;
+
+ /* Get PCI device number */
+ devno = dm_pci_get_bdf(dev);
+ if (devno == -1)
+ return 1;
+
+ dm_pci_read_config16(dev, PCI_DEVICE_ID, &word);
+
+ /* get the port count */
+ word &= 0xf;
+
+ sata_info.portbase = 0;
+ sata_info.maxport = sata_info.portbase + word;
+ sata_info.devno = devno;
+
+ /* Read out all BARs */
+ sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
+ PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
+ PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
+
+ /* mask out the unused bits */
+ sata_info.iobase[0] &= 0xffffff80;
+ sata_info.iobase[1] &= 0xfffffc00;
+
+ /* Enable Bus Mastering and memory region */
+ dm_pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Check if mem accesses and Bus Mastering are enabled. */
+ dm_pci_read_config16(dev, PCI_COMMAND, &word);
+ if (!(word & PCI_COMMAND_MEMORY) ||
+ (!(word & PCI_COMMAND_MASTER))) {
+ printf("Error: Can not enable MEM access or Bus Mastering.\n");
+ debug("PCI command: %04x\n", word);
+ return 1;
+ }
+
+ /* GPIO off */
+ writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
+ /* clear global reset & mask interrupts during initialization */
+ writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
+
+ for (i = sata_info.portbase; i < sata_info.maxport; i++) {
+ snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
+ ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
+ IF_TYPE_SATA, -1, 512, 0, &blk);
+ if (ret) {
+ debug("Can't create device\n");
+ return ret;
+ }
+
+ ret = sil_init_sata(blk, i);
+ if (ret)
+ return -ENODEV;
+
+ ret = scan_sata(blk, i);
+ if (ret)
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int sata_sil_scan(struct udevice *dev)
+{
+ /* Nothing to do here */
+
+ return 0;
+}
+
+struct sil_ops sata_sil_ops = {
+ .scan = sata_sil_scan,
+};
+
+static const struct udevice_id sil_pci_ids[] = {
+ { .compatible = "sil-pci-sample" },
+ { }
+};
+
+U_BOOT_DRIVER(sil_ahci_pci) = {
+ .name = "sil_ahci_pci",
+ .id = UCLASS_AHCI,
+ .of_match = sil_pci_ids,
+ .ops = &sata_sil_ops,
+ .probe = sil_pci_probe,
+ .priv_auto_alloc_size = sizeof(struct sil_sata_priv),
+};
+
+U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);
+#endif
diff --git a/drivers/ata/sata_sil.h b/drivers/ata/sata_sil.h
index 8b7cbdf..dad8530 100644
--- a/drivers/ata/sata_sil.h
+++ b/drivers/ata/sata_sil.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
* Author: Tang Yuantian <b29983@freescale.com>
*/
@@ -13,7 +14,7 @@
/*
* SATA device driver struct for each dev
*/
-struct sil_sata {
+typedef struct sil_sata {
char name[12];
void *port; /* the port base address */
int lba48;
@@ -24,7 +25,8 @@ struct sil_sata {
int wcache;
int flush;
int flush_ext;
-};
+ int id;
+} sil_sata_t;
/* sata info for each controller */
struct sata_info {
@@ -210,4 +212,12 @@ enum {
CMD_ERR = 0x21,
};
+#if CONFIG_IS_ENABLED(BLK)
+#define ATA_MAX_PORTS 32
+struct sil_sata_priv {
+ int port_num;
+ sil_sata_t *sil_sata_desc[ATA_MAX_PORTS];
+};
+#endif
+
#endif
--
2.9.5
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [v2 2/2] ata: sata_sil: Add DM support for Silicon sata driver
2019-10-23 10:56 ` [U-Boot] [v2 2/2] ata: sata_sil: Add DM support for Silicon sata driver Peng Ma
@ 2019-11-18 9:02 ` Priyanka Jain
0 siblings, 0 replies; 3+ messages in thread
From: Priyanka Jain @ 2019-11-18 9:02 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Peng Ma <peng.ma@nxp.com>
>Sent: Wednesday, October 23, 2019 4:27 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; wd at denx.de; Priyanka Jain
><priyanka.jain@nxp.com>
>Cc: jagan at openedev.com; sjg at chromium.org; Andy Tang
><andy.tang@nxp.com>; andre.przywara at arm.com; sr at denx.de;
>smoch at web.de; u-boot at lists.denx.de; Peng Ma <peng.ma@nxp.com>
>Subject: [v2 2/2] ata: sata_sil: Add DM support for Silicon sata driver
>
>Add DM support for Silicon(SIL3131 / SIL3132 / SIL3124) sata driver as few of
>the PowerPC platforms such as P series based boards need to use SATA_SIL
>with DM,
>
>Also fix below warning while PowerPC P series boards compilation,
>
>===================== WARNING ======================"
>This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
>enabled. Please update the storage controller driver to use"
>CONFIG_AHCI before the v2019.07 release."
>Failure to update by the deadline may result in board removal."
>See doc/driver-model/MIGRATION.txt for more info."
>===================================================="
>
>Signed-off-by: Peng Ma <peng.ma@nxp.com>
>---
>Changed for v2:
> - Rewrite the subject and description
>
> drivers/ata/Kconfig | 1 +
> drivers/ata/sata_sil.c | 539 +++++++++++++++++++++++++++++++------------------
> drivers/ata/sata_sil.h | 14 +-
> 3 files changed, 357 insertions(+), 197 deletions(-)
>
>diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 57121f6..fe589d3
>100644
>--- a/drivers/ata/Kconfig
>+++ b/drivers/ata/Kconfig
>@@ -110,6 +110,7 @@ config SATA_MV
> config SATA_SIL
> bool "Enable Silicon Image SIL3131 / SIL3132 / SIL3124 SATA driver
>support"
> select LIBATA
>+ select AHCI if BLK
> help
> Enable this driver to support the SIL3131, SIL3132 and SIL3124
> SATA controllers.
>diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c index
>a8598d9..20502b3 100644
>--- a/drivers/ata/sata_sil.c
>+++ b/drivers/ata/sata_sil.c
>@@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright (C) 2011 Freescale Semiconductor, Inc.
>+ * Copyright 2019 NXP
> * Author: Tang Yuantian <b29983@freescale.com>
> */
>
>@@ -14,18 +15,29 @@
> #include <sata.h>
> #include <libata.h>
> #include <sata.h>
>+
>+#if CONFIG_IS_ENABLED(BLK)
>+#include <dm.h>
>+#include <blk.h>
>+#endif
>+
> #include "sata_sil.h"
>
>-/* Convert sectorsize to wordsize */
>-#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
> #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
>
>+/* just compatible ahci_ops */
>+struct sil_ops {
>+ int *rev0;
>+ int *rev1;
>+ int (*scan)(struct udevice *dev);
>+};
>+
> static struct sata_info sata_info;
>
> static struct pci_device_id supported[] = {
>- {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131},
>- {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132},
>- {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124},
>+ { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131)
>},
>+ { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132)
>},
>+ { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124)
>},
> {}
> };
>
>@@ -113,9 +125,9 @@ static int sil_init_port(void *port)
> return 0;
> }
>
>-static void sil_read_fis(int dev, int tag, struct sata_fis_d2h *fis)
>+static void sil_read_fis(struct sil_sata *sata, int tag,
>+ struct sata_fis_d2h *fis)
> {
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
> void *port = sata->port;
> struct sil_prb *prb;
> int i;
>@@ -128,9 +140,9 @@ static void sil_read_fis(int dev, int tag, struct
>sata_fis_d2h *fis)
> *dst++ = readl(src++);
> }
>
>-static int sil_exec_cmd(int dev, struct sil_cmd_block *pcmd, int tag)
>+static int sil_exec_cmd(struct sil_sata *sata, struct sil_cmd_block *pcmd,
>+ int tag)
> {
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
> void *port = sata->port;
> u64 paddr = virt_to_bus(sata->devno, pcmd);
> u32 irq_mask, irq_stat;
>@@ -164,9 +176,8 @@ static int sil_exec_cmd(int dev, struct sil_cmd_block
>*pcmd, int tag)
> return rc;
> }
>
>-static int sil_cmd_set_feature(int dev)
>+static int sil_cmd_set_feature(struct sil_sata *sata)
> {
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
> struct sil_cmd_block cmdb, *pcmd = &cmdb;
> struct sata_fis_d2h fis;
> u8 udma_cap;
>@@ -191,9 +202,9 @@ static int sil_cmd_set_feature(int dev)
> if (udma_cap == ATA_UDMA3)
> pcmd->prb.fis.sector_count = XFER_UDMA_3;
>
>- ret = sil_exec_cmd(dev, pcmd, 0);
>+ ret = sil_exec_cmd(sata, pcmd, 0);
> if (ret) {
>- sil_read_fis(dev, 0, &fis);
>+ sil_read_fis(sata, 0, &fis);
> printf("Err: exe cmd(0x%x).\n",
> readl(sata->port + PORT_SERROR));
> sil_sata_dump_fis(&fis);
>@@ -203,9 +214,34 @@ static int sil_cmd_set_feature(int dev)
> return 0;
> }
>
>-static int sil_cmd_identify_device(int dev, u16 *id)
>+static void sil_sata_init_wcache(struct sil_sata *sata, u16 *id) {
>+ if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
>+ sata->wcache = 1;
>+ if (ata_id_has_flush(id))
>+ sata->flush = 1;
>+ if (ata_id_has_flush_ext(id))
>+ sata->flush_ext = 1;
>+}
>+
>+static void sil_sata_set_feature_by_id(struct sil_sata *sata, u16 *id)
>+{ #ifdef CONFIG_LBA48
>+ /* Check if support LBA48 */
>+ if (ata_id_has_lba48(id)) {
>+ sata->lba48 = 1;
>+ debug("Device supports LBA48\n");
>+ } else {
>+ debug("Device supports LBA28\n");
>+ }
>+#endif
>+
>+ sil_sata_init_wcache(sata, id);
>+ sil_cmd_set_feature(sata);
>+}
>+
>+static int sil_cmd_identify_device(struct sil_sata *sata, u16 *id)
> {
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
> struct sil_cmd_block cmdb, *pcmd = &cmdb;
> struct sata_fis_d2h fis;
> int ret;
>@@ -220,9 +256,9 @@ static int sil_cmd_identify_device(int dev, u16 *id)
> pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
> pcmd->sge.flags = cpu_to_le32(SGE_TRM);
>
>- ret = sil_exec_cmd(dev, pcmd, 0);
>+ ret = sil_exec_cmd(sata, pcmd, 0);
> if (ret) {
>- sil_read_fis(dev, 0, &fis);
>+ sil_read_fis(sata, 0, &fis);
> printf("Err: id cmd(0x%x).\n", readl(sata->port +
>PORT_SERROR));
> sil_sata_dump_fis(&fis);
> return 1;
>@@ -232,17 +268,16 @@ static int sil_cmd_identify_device(int dev, u16 *id)
> return 0;
> }
>
>-static int sil_cmd_soft_reset(int dev)
>+static int sil_cmd_soft_reset(struct sil_sata *sata)
> {
> struct sil_cmd_block cmdb, *pcmd = &cmdb;
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
> struct sata_fis_d2h fis;
> void *port = sata->port;
> int ret;
>
> /* put the port into known state */
> if (sil_init_port(port)) {
>- printf("SRST: port %d not ready\n", dev);
>+ printf("SRST: port %d not ready\n", sata->id);
> return 1;
> }
>
>@@ -252,9 +287,9 @@ static int sil_cmd_soft_reset(int dev)
> pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
> pcmd->prb.fis.pm_port_c = 0xf;
>
>- ret = sil_exec_cmd(dev, &cmdb, 0);
>+ ret = sil_exec_cmd(sata, &cmdb, 0);
> if (ret) {
>- sil_read_fis(dev, 0, &fis);
>+ sil_read_fis(sata, 0, &fis);
> printf("SRST cmd error.\n");
> sil_sata_dump_fis(&fis);
> return 1;
>@@ -263,10 +298,9 @@ static int sil_cmd_soft_reset(int dev)
> return 0;
> }
>
>-static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
>- u8 *buffer, int is_write)
>+static ulong sil_sata_rw_cmd(struct sil_sata *sata, ulong start, ulong blkcnt,
>+ u8 *buffer, int is_write)
> {
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
> struct sil_cmd_block cmdb, *pcmd = &cmdb;
> struct sata_fis_d2h fis;
> u64 block;
>@@ -296,9 +330,9 @@ static ulong sil_sata_rw_cmd(int dev, ulong start,
>ulong blkcnt,
> pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
> pcmd->sge.flags = cpu_to_le32(SGE_TRM);
>
>- ret = sil_exec_cmd(dev, pcmd, 0);
>+ ret = sil_exec_cmd(sata, pcmd, 0);
> if (ret) {
>- sil_read_fis(dev, 0, &fis);
>+ sil_read_fis(sata, 0, &fis);
> printf("Err: rw cmd(0x%08x).\n",
> readl(sata->port + PORT_SERROR));
> sil_sata_dump_fis(&fis);
>@@ -308,10 +342,9 @@ static ulong sil_sata_rw_cmd(int dev, ulong start,
>ulong blkcnt,
> return blkcnt;
> }
>
>-static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
>- u8 *buffer, int is_write)
>+static ulong sil_sata_rw_cmd_ext(struct sil_sata *sata, ulong start,
>+ ulong blkcnt, u8 *buffer, int is_write)
> {
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
> struct sil_cmd_block cmdb, *pcmd = &cmdb;
> struct sata_fis_d2h fis;
> u64 block;
>@@ -344,9 +377,9 @@ static ulong sil_sata_rw_cmd_ext(int dev, ulong start,
>ulong blkcnt,
> pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
> pcmd->sge.flags = cpu_to_le32(SGE_TRM);
>
>- ret = sil_exec_cmd(dev, pcmd, 0);
>+ ret = sil_exec_cmd(sata, pcmd, 0);
> if (ret) {
>- sil_read_fis(dev, 0, &fis);
>+ sil_read_fis(sata, 0, &fis);
> printf("Err: rw ext cmd(0x%08x).\n",
> readl(sata->port + PORT_SERROR));
> sil_sata_dump_fis(&fis);
>@@ -356,8 +389,9 @@ static ulong sil_sata_rw_cmd_ext(int dev, ulong start,
>ulong blkcnt,
> return blkcnt;
> }
>
>-static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
>- const void *buffer, int is_write)
>+static ulong sil_sata_rw_lba28(struct sil_sata *sata, ulong blknr,
>+ lbaint_t blkcnt, const void *buffer,
>+ int is_write)
> {
> ulong start, blks, max_blks;
> u8 *addr;
>@@ -369,12 +403,12 @@ static ulong sil_sata_rw_lba28(int dev, ulong blknr,
>lbaint_t blkcnt,
> max_blks = ATA_MAX_SECTORS;
> do {
> if (blks > max_blks) {
>- sil_sata_rw_cmd(dev, start, max_blks, addr, is_write);
>+ sil_sata_rw_cmd(sata, start, max_blks, addr, is_write);
> start += max_blks;
> blks -= max_blks;
> addr += ATA_SECT_SIZE * max_blks;
> } else {
>- sil_sata_rw_cmd(dev, start, blks, addr, is_write);
>+ sil_sata_rw_cmd(sata, start, blks, addr, is_write);
> start += blks;
> blks = 0;
> addr += ATA_SECT_SIZE * blks;
>@@ -384,8 +418,9 @@ static ulong sil_sata_rw_lba28(int dev, ulong blknr,
>lbaint_t blkcnt,
> return blkcnt;
> }
>
>-static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
>- const void *buffer, int is_write)
>+static ulong sil_sata_rw_lba48(struct sil_sata *sata, ulong blknr,
>+ lbaint_t blkcnt, const void *buffer,
>+ int is_write)
> {
> ulong start, blks, max_blks;
> u8 *addr;
>@@ -397,14 +432,14 @@ static ulong sil_sata_rw_lba48(int dev, ulong blknr,
>lbaint_t blkcnt,
> max_blks = ATA_MAX_SECTORS_LBA48;
> do {
> if (blks > max_blks) {
>- sil_sata_rw_cmd_ext(dev, start, max_blks,
>- addr, is_write);
>+ sil_sata_rw_cmd_ext(sata, start, max_blks,
>+ addr, is_write);
> start += max_blks;
> blks -= max_blks;
> addr += ATA_SECT_SIZE * max_blks;
> } else {
>- sil_sata_rw_cmd_ext(dev, start, blks,
>- addr, is_write);
>+ sil_sata_rw_cmd_ext(sata, start, blks,
>+ addr, is_write);
> start += blks;
> blks = 0;
> addr += ATA_SECT_SIZE * blks;
>@@ -414,7 +449,7 @@ static ulong sil_sata_rw_lba48(int dev, ulong blknr,
>lbaint_t blkcnt,
> return blkcnt;
> }
>
>-static void sil_sata_cmd_flush_cache(int dev)
>+static void sil_sata_cmd_flush_cache(struct sil_sata *sata)
> {
> struct sil_cmd_block cmdb, *pcmd = &cmdb;
>
>@@ -423,10 +458,10 @@ static void sil_sata_cmd_flush_cache(int dev)
> pcmd->prb.fis.pm_port_c = (1 << 7);
> pcmd->prb.fis.command = ATA_CMD_FLUSH;
>
>- sil_exec_cmd(dev, pcmd, 0);
>+ sil_exec_cmd(sata, pcmd, 0);
> }
>
>-static void sil_sata_cmd_flush_cache_ext(int dev)
>+static void sil_sata_cmd_flush_cache_ext(struct sil_sata *sata)
> {
> struct sil_cmd_block cmdb, *pcmd = &cmdb;
>
>@@ -435,54 +470,30 @@ static void sil_sata_cmd_flush_cache_ext(int dev)
> pcmd->prb.fis.pm_port_c = (1 << 7);
> pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
>
>- sil_exec_cmd(dev, pcmd, 0);
>-}
>-
>-static void sil_sata_init_wcache(int dev, u16 *id) -{
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
>-
>- if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
>- sata->wcache = 1;
>- if (ata_id_has_flush(id))
>- sata->flush = 1;
>- if (ata_id_has_flush_ext(id))
>- sata->flush_ext = 1;
>-}
>-
>-static int sil_sata_get_wcache(int dev) -{
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
>-
>- return sata->wcache;
>-}
>-
>-static int sil_sata_get_flush(int dev)
>-{
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
>-
>- return sata->flush;
>-}
>-
>-static int sil_sata_get_flush_ext(int dev) -{
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
>-
>- return sata->flush_ext;
>+ sil_exec_cmd(sata, pcmd, 0);
> }
>
> /*
> * SATA interface between low level driver and command layer
> */
>+#if !CONFIG_IS_ENABLED(BLK)
> ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) {
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
>+ sil_sata_t *sata = (sil_sata_t *)sata_dev_desc[dev].priv; #else static
>+ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
>+ void *buffer)
>+{
>+ struct sil_sata_priv *priv = dev_get_platdata(dev);
>+ int port_number = priv->port_num;
>+ sil_sata_t *sata = priv->sil_sata_desc[port_number]; #endif
> ulong rc;
>
> if (sata->lba48)
>- rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
>+ rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, READ_CMD);
> else
>- rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
>+ rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, READ_CMD);
>
> return rc;
> }
>@@ -490,111 +501,48 @@ ulong sata_read(int dev, ulong blknr, lbaint_t
>blkcnt, void *buffer)
> /*
> * SATA interface between low level driver and command layer
> */
>+#if !CONFIG_IS_ENABLED(BLK)
> ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) {
>- struct sil_sata *sata = sata_dev_desc[dev].priv;
>+ sil_sata_t *sata = (sil_sata_t *)sata_dev_desc[dev].priv; #else ulong
>+sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
>+ const void *buffer)
>+{
>+ struct sil_sata_priv *priv = dev_get_platdata(dev);
>+ int port_number = priv->port_num;
>+ sil_sata_t *sata = priv->sil_sata_desc[port_number]; #endif
> ulong rc;
>
> if (sata->lba48) {
>- rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
>- if (sil_sata_get_wcache(dev) && sil_sata_get_flush_ext(dev))
>- sil_sata_cmd_flush_cache_ext(dev);
>+ rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer,
>WRITE_CMD);
>+ if (sata->wcache && sata->flush_ext)
>+ sil_sata_cmd_flush_cache_ext(sata);
> } else {
>- rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
>- if (sil_sata_get_wcache(dev) && sil_sata_get_flush(dev))
>- sil_sata_cmd_flush_cache(dev);
>+ rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer,
>WRITE_CMD);
>+ if (sata->wcache && sata->flush)
>+ sil_sata_cmd_flush_cache(sata);
> }
>
> return rc;
> }
>
>-/*
>- * SATA interface between low level driver and command layer
>- */
>-int init_sata(int dev)
>-{
>- static int init_done, idx;
>- pci_dev_t devno;
>- u16 word;
>-
>- if (init_done == 1 && dev < sata_info.maxport)
>- return 0;
>-
>- init_done = 1;
>-
>- /* Find PCI device(s) */
>- devno = pci_find_devices(supported, idx++);
>- if (devno == -1)
>- return 1;
>-
>- pci_read_config_word(devno, PCI_DEVICE_ID, &word);
>-
>- /* get the port count */
>- word &= 0xf;
>-
>- sata_info.portbase = sata_info.maxport;
>- sata_info.maxport = sata_info.portbase + word;
>- sata_info.devno = devno;
>-
>- /* Read out all BARs */
>- sata_info.iobase[0] = (ulong)pci_map_bar(devno,
>- PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
>- sata_info.iobase[1] = (ulong)pci_map_bar(devno,
>- PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
>- sata_info.iobase[2] = (ulong)pci_map_bar(devno,
>- PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
>-
>- /* mask out the unused bits */
>- sata_info.iobase[0] &= 0xffffff80;
>- sata_info.iobase[1] &= 0xfffffc00;
>- sata_info.iobase[2] &= 0xffffff80;
>-
>- /* Enable Bus Mastering and memory region */
>- pci_write_config_word(devno, PCI_COMMAND,
>- PCI_COMMAND_MEMORY |
>PCI_COMMAND_MASTER);
>-
>- /* Check if mem accesses and Bus Mastering are enabled. */
>- pci_read_config_word(devno, PCI_COMMAND, &word);
>- if (!(word & PCI_COMMAND_MEMORY) ||
>- (!(word & PCI_COMMAND_MASTER))) {
>- printf("Error: Can not enable MEM access or Bus
>Mastering.\n");
>- debug("PCI command: %04x\n", word);
>- return 1;
>- }
>-
>- /* GPIO off */
>- writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
>- /* clear global reset & mask interrupts during initialization */
>- writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
>-
>- return 0;
>-}
>-
>-int reset_sata(int dev)
>+#if !CONFIG_IS_ENABLED(BLK)
>+static int sil_init_sata(int dev)
> {
>- return 0;
>-}
>-
>-/*
>- * SATA interface between low level driver and command layer
>- */
>-int scan_sata(int dev)
>+#else
>+static int sil_init_sata(struct udevice *uc_dev, int dev)
> {
>- unsigned char serial[ATA_ID_SERNO_LEN + 1];
>- unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
>- unsigned char product[ATA_ID_PROD_LEN + 1];
>- struct sil_sata *sata;
>+ struct sil_sata_priv *priv = dev_get_platdata(uc_dev); #endif
>+ sil_sata_t *sata;
> void *port;
>- int cnt;
>- u16 *id;
> u32 tmp;
>+ int cnt;
>
>- if (dev >= sata_info.maxport) {
>- printf("SATA#%d is not present\n", dev);
>- return 1;
>- }
>+ printf("SATA#%d:\n", dev);
>
>- printf("SATA#%d\n", dev);
> port = (void *)sata_info.iobase[1] +
> PORT_REGS_SIZE * (dev - sata_info.portbase);
>
>@@ -646,69 +594,270 @@ int scan_sata(int dev)
> return 1;
> }
>
>- sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
>+ sata = (sil_sata_t *)malloc(sizeof(struct sil_sata));
> if (!sata) {
> printf("%d no memory.\n", dev);
> return 1;
> }
> memset((void *)sata, 0, sizeof(struct sil_sata));
>
>- /* turn on port interrupt */
>- tmp = readl((void *)(sata_info.iobase[0] + HOST_CTRL));
>- tmp |= (1 << (dev - sata_info.portbase));
>- writel(tmp, (void *)(sata_info.iobase[0] + HOST_CTRL));
>-
> /* Save the private struct to block device struct */
>+#if !CONFIG_IS_ENABLED(BLK)
> sata_dev_desc[dev].priv = (void *)sata;
>+#else
>+ priv->sil_sata_desc[dev] = sata;
>+ priv->port_num = dev;
>+#endif
>+ sata->id = dev;
> sata->port = port;
> sata->devno = sata_info.devno;
> sprintf(sata->name, "SATA#%d", dev);
>- sil_cmd_soft_reset(dev);
>+ sil_cmd_soft_reset(sata);
> tmp = readl(port + PORT_SSTATUS);
> tmp = (tmp >> 4) & 0xf;
> printf(" (%s)\n", sata_spd_string(tmp));
>
>+ return 0;
>+}
>+
>+#if !CONFIG_IS_ENABLED(BLK)
>+/*
>+ * SATA interface between low level driver and command layer */ int
>+init_sata(int dev) {
>+ static int init_done, idx;
>+ pci_dev_t devno;
>+ u16 word;
>+
>+ if (init_done == 1 && dev < sata_info.maxport)
>+ goto init_start;
>+
>+ init_done = 1;
>+
>+ /* Find PCI device(s) */
>+ devno = pci_find_devices(supported, idx++);
>+ if (devno == -1)
>+ return 1;
>+
>+ pci_read_config_word(devno, PCI_DEVICE_ID, &word);
>+
>+ /* get the port count */
>+ word &= 0xf;
>+
>+ sata_info.portbase = 0;
>+ sata_info.maxport = sata_info.portbase + word;
>+ sata_info.devno = devno;
>+
>+ /* Read out all BARs */
>+ sata_info.iobase[0] = (ulong)pci_map_bar(devno,
>+ PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
>+ sata_info.iobase[1] = (ulong)pci_map_bar(devno,
>+ PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
>+
>+ /* mask out the unused bits */
>+ sata_info.iobase[0] &= 0xffffff80;
>+ sata_info.iobase[1] &= 0xfffffc00;
>+
>+ /* Enable Bus Mastering and memory region */
>+ pci_write_config_word(devno, PCI_COMMAND,
>+ PCI_COMMAND_MEMORY |
>PCI_COMMAND_MASTER);
>+
>+ /* Check if mem accesses and Bus Mastering are enabled. */
>+ pci_read_config_word(devno, PCI_COMMAND, &word);
>+ if (!(word & PCI_COMMAND_MEMORY) ||
>+ (!(word & PCI_COMMAND_MASTER))) {
>+ printf("Error: Can not enable MEM access or Bus
>Mastering.\n");
>+ debug("PCI command: %04x\n", word);
>+ return 1;
>+ }
>+
>+ /* GPIO off */
>+ writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
>+ /* clear global reset & mask interrupts during initialization */
>+ writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
>+
>+init_start:
>+ return sil_init_sata(dev);
>+}
>+
>+int reset_sata(int dev)
>+{
>+ return 0;
>+}
>+
>+/*
>+ * SATA interface between low level driver and command layer */ int
>+scan_sata(int dev) {
>+ sil_sata_t *sata = (sil_sata_t *)sata_dev_desc[dev].priv; #else static
>+int scan_sata(struct udevice *blk_dev, int dev) {
>+ struct blk_desc *desc = dev_get_uclass_platdata(blk_dev);
>+ struct sil_sata_priv *priv = dev_get_platdata(blk_dev);
>+ sil_sata_t *sata = priv->sil_sata_desc[dev]; #endif
>+ unsigned char serial[ATA_ID_SERNO_LEN + 1];
>+ unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
>+ unsigned char product[ATA_ID_PROD_LEN + 1];
>+ u16 *id;
>+
> id = (u16 *)malloc(ATA_ID_WORDS * 2);
> if (!id) {
> printf("Id malloc failed\n");
>- free((void *)sata);
> return 1;
> }
>- sil_cmd_identify_device(dev, id);
>+ sil_cmd_identify_device(sata, id);
>
>-#ifdef CONFIG_LBA48
>- /* Check if support LBA48 */
>- if (ata_id_has_lba48(id)) {
>- sata_dev_desc[dev].lba48 = 1;
>- sata->lba48 = 1;
>- debug("Device supports LBA48\n");
>- } else
>- debug("Device supports LBA28\n");
>-#endif
>+ sil_sata_set_feature_by_id(sata, id);
>
> /* Serial number */
> ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
>- memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
>
> /* Firmware version */
> ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
>- memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
>
> /* Product model */
> ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
>- memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
>
>+#if !CONFIG_IS_ENABLED(BLK)
>+ memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
>+ memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
>+ memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
> /* Totoal sectors */
> sata_dev_desc[dev].lba = ata_id_n_sectors(id);
>-
>- sil_sata_init_wcache(dev, id);
>- sil_cmd_set_feature(dev);
>+#ifdef CONFIG_LBA48
>+ sata_dev_desc[dev].lba48 = sata->lba48; #endif #else
>+ memcpy(desc->product, serial, sizeof(serial));
>+ memcpy(desc->revision, firmware, sizeof(firmware));
>+ memcpy(desc->vendor, product, sizeof(product));
>+ desc->lba = ata_id_n_sectors(id);
>+#ifdef CONFIG_LBA48
>+ desc->lba48 = sata->lba48;
>+#endif
>+#endif
>
> #ifdef DEBUG
>- sil_cmd_identify_device(dev, id);
> ata_dump_id(id);
> #endif
> free((void *)id);
>
> return 0;
> }
>+
>+#if CONFIG_IS_ENABLED(BLK)
>+static const struct blk_ops sata_sil_blk_ops = {
>+ .read = sata_read,
>+ .write = sata_write,
>+};
>+
>+U_BOOT_DRIVER(sata_sil_driver) = {
>+ .name = "sata_sil_blk",
>+ .id = UCLASS_BLK,
>+ .ops = &sata_sil_blk_ops,
>+ .platdata_auto_alloc_size = sizeof(struct sil_sata_priv), };
>+
>+static int sil_pci_probe(struct udevice *dev) {
>+ struct udevice *blk;
>+ char sata_name[10];
>+ pci_dev_t devno;
>+ u16 word;
>+ int ret;
>+ int i;
>+
>+ /* Get PCI device number */
>+ devno = dm_pci_get_bdf(dev);
>+ if (devno == -1)
>+ return 1;
>+
>+ dm_pci_read_config16(dev, PCI_DEVICE_ID, &word);
>+
>+ /* get the port count */
>+ word &= 0xf;
>+
>+ sata_info.portbase = 0;
>+ sata_info.maxport = sata_info.portbase + word;
>+ sata_info.devno = devno;
>+
>+ /* Read out all BARs */
>+ sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
>+ PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
>+ sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
>+ PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
>+
>+ /* mask out the unused bits */
>+ sata_info.iobase[0] &= 0xffffff80;
>+ sata_info.iobase[1] &= 0xfffffc00;
>+
>+ /* Enable Bus Mastering and memory region */
>+ dm_pci_write_config16(dev, PCI_COMMAND,
>+ PCI_COMMAND_MEMORY |
>PCI_COMMAND_MASTER);
>+
>+ /* Check if mem accesses and Bus Mastering are enabled. */
>+ dm_pci_read_config16(dev, PCI_COMMAND, &word);
>+ if (!(word & PCI_COMMAND_MEMORY) ||
>+ (!(word & PCI_COMMAND_MASTER))) {
>+ printf("Error: Can not enable MEM access or Bus
>Mastering.\n");
>+ debug("PCI command: %04x\n", word);
>+ return 1;
>+ }
>+
>+ /* GPIO off */
>+ writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
>+ /* clear global reset & mask interrupts during initialization */
>+ writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
>+
>+ for (i = sata_info.portbase; i < sata_info.maxport; i++) {
>+ snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
>+ ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
>+ IF_TYPE_SATA, -1, 512, 0, &blk);
>+ if (ret) {
>+ debug("Can't create device\n");
>+ return ret;
>+ }
>+
>+ ret = sil_init_sata(blk, i);
>+ if (ret)
>+ return -ENODEV;
>+
>+ ret = scan_sata(blk, i);
>+ if (ret)
>+ return -ENODEV;
>+ }
>+
>+ return 0;
>+}
>+
>+static int sata_sil_scan(struct udevice *dev) {
>+ /* Nothing to do here */
>+
>+ return 0;
>+}
>+
>+struct sil_ops sata_sil_ops = {
>+ .scan = sata_sil_scan,
>+};
>+
>+static const struct udevice_id sil_pci_ids[] = {
>+ { .compatible = "sil-pci-sample" },
>+ { }
>+};
>+
>+U_BOOT_DRIVER(sil_ahci_pci) = {
>+ .name = "sil_ahci_pci",
>+ .id = UCLASS_AHCI,
>+ .of_match = sil_pci_ids,
>+ .ops = &sata_sil_ops,
>+ .probe = sil_pci_probe,
>+ .priv_auto_alloc_size = sizeof(struct sil_sata_priv), };
>+
>+U_BOOT_PCI_DEVICE(sil_ahci_pci, supported); #endif
>diff --git a/drivers/ata/sata_sil.h b/drivers/ata/sata_sil.h index
>8b7cbdf..dad8530 100644
>--- a/drivers/ata/sata_sil.h
>+++ b/drivers/ata/sata_sil.h
>@@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
> * Copyright (C) 2011 Freescale Semiconductor, Inc.
>+ * Copyright 2019 NXP
> * Author: Tang Yuantian <b29983@freescale.com>
> */
>
>@@ -13,7 +14,7 @@
> /*
> * SATA device driver struct for each dev
> */
>-struct sil_sata {
>+typedef struct sil_sata {
> char name[12];
> void *port; /* the port base address */
> int lba48;
>@@ -24,7 +25,8 @@ struct sil_sata {
> int wcache;
> int flush;
> int flush_ext;
>-};
>+ int id;
>+} sil_sata_t;
>
> /* sata info for each controller */
> struct sata_info {
>@@ -210,4 +212,12 @@ enum {
> CMD_ERR = 0x21,
> };
>
>+#if CONFIG_IS_ENABLED(BLK)
>+#define ATA_MAX_PORTS 32
>+struct sil_sata_priv {
>+ int port_num;
>+ sil_sata_t *sil_sata_desc[ATA_MAX_PORTS];
>+};
>+#endif
>+
> #endif
>--
>2.9.5
Please fix below checkpatch warning
WARNING: do not add new typedefs
#862: FILE: drivers/ata/sata_sil.h:17:
+typedef struct sil_sata {
--priyankajain
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2019-10-23 10:56 [U-Boot] [v2 1/2] ata: fsl_sata: Add DM support for Freescale PowerPC SATA driver Peng Ma
2019-10-23 10:56 ` [U-Boot] [v2 2/2] ata: sata_sil: Add DM support for Silicon sata driver Peng Ma
2019-11-18 9:02 ` Priyanka Jain
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