[MODERATED] Re: [PATCH v7 00/10] TAAv7 0

[Josh Poimboeuf <jpoimboe@redhat.com>]

On Wed, Oct 23, 2019 at 05:46:04PM +0200, speck for Borislav Petkov wrote:
> On Mon, Oct 21, 2019 at 01:22:01PM -0700, speck for Pawan Gupta wrote:
> > From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
> > Subject: [PATCH v7 00/10] TAAv7
> 
> Ok, I ran the pile on a box here:
> 
> vendor_id       : GenuineIntel
> cpu family      : 6
> model           : 158
> model name      : Intel(R) Core(TM) i5-9600K CPU @ 3.70GHz
> stepping        : 12
> 
> There is some microcode for it:
> 
> [    0.000000] microcode: microcode updated early to revision 0xc6, date = 2019-08-14
> [    1.005808] microcode: sig=0x906ec, pf=0x2, revision=0xc6
> 
> And booting it says:
> 
> [    0.197056] tsx_init: enter
> [    0.197207] tsx_ctrl_is_supported: CAP MSR: 0x9
> 
> This is added by me and it shows that the box is a pre MDS_NO=1 one,
> i.e., MD_CLEAR mitigates TAA too AFAIU.
> 
> Which means, there's no TSX_CTRL_MSR and I cannot disable TSX there.
> 
> Which means, boxes like this one don't need the microcode as long as
> they have MD_CLEAR microcode.
> 
> [    0.197363] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization
> [    0.197540] Spectre V2 : Mitigation: Full generic retpoline
> [    0.197696] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch
> [    0.197871] Spectre V2 : Enabling Restricted Speculation for firmware calls
> [    0.198032] Spectre V2 : mitigation: Enabling conditional Indirect Branch Prediction Barrier
> [    0.198208] Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl and seccomp
> [    0.198386] MDS: Mitigation: Clear CPU buffers
> [    0.198540] TAA: Mitigation: Clear CPU buffers
> 
> Makes sense?

FWIW, makes sense to me.  It will be especially interesting to see tests
on an MDS_NO=1 box with the new microcode.

-- 
Josh