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From: Alvaro Gamez Machado <alvaro.gamez@hazent.com>
To: Mark Brown <broonie@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>,
	Shubhrajyoti Datta <shubhraj@xilinx.com>,
	linux-spi@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH] spi: set bits_per_word based on controller's bits_per_word_mask
Date: Thu, 24 Oct 2019 15:18:57 +0200	[thread overview]
Message-ID: <20191024131856.GA32609@salem.gmr.ssr.upm.es> (raw)
In-Reply-To: <20191024131129.GE46373@sirena.co.uk>

On Thu, Oct 24, 2019 at 02:11:29PM +0100, Mark Brown wrote:
> On Thu, Oct 24, 2019 at 02:54:37PM +0200, Alvaro Gamez Machado wrote:
> 
> > I think then the only way this would be feasible is to check if 8 bits is an
> > acceptable number for the master and, if it isn't, apply the lowest
> > available data width. I believe this cannot break anything, as it leaves 8
> > as the default unless the master can't work with that number, in which case
> > it really doesn't matter what client device wants because the hardware can't
> > provide it.
> 
> No, that still leaves the slave driver thinking it's sending 8 bits when
> really it's sending something else - the default is just 8 bits, if the
> controller can't do it then the transfer can't happen and there's an
> error.  It's not a good idea to carry on if we're likely to introduce
> data corruption.

Well, yes. But I don't think that's a software issue but a hardware one.

If you have a board that has a SPI master that cannot talk to an 8 bits
device and you expect to communicate with anything that accepts 8 bits
you're not going to be able to. Either the kernel raises an error or it
shuts up and tries its best. I understand the first option is better, but I
also think that's not a software issue, that hardware simply cannot work as
is regardless of what we do in software. The hardware devices simply can't
talk to each other.


-- 
Alvaro G. M.

  reply	other threads:[~2019-10-24 13:19 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-24 11:07 [PATCH] Allowing Xilinx's AXI Quad widths different than 8 bits on userspace Alvaro Gamez Machado
2019-10-24 11:07 ` [PATCH] spi: xilinx: add description of new property xlnx,num-transfer-bits Alvaro Gamez Machado
2019-10-24 11:57   ` Mark Brown
2019-10-24 11:57   ` Applied "spi: xilinx: add description of new property xlnx,num-transfer-bits" to the spi tree Mark Brown
2019-10-24 11:07 ` [PATCH] spi: xilinx: Add DT support for selecting transfer word width Alvaro Gamez Machado
2019-10-24 11:57   ` Applied "spi: xilinx: Add DT support for selecting transfer word width" to the spi tree Mark Brown
2019-10-24 11:07 ` [PATCH] spi: set bits_per_word based on controller's bits_per_word_mask Alvaro Gamez Machado
2019-10-24 11:13   ` Mark Brown
2019-10-24 12:54     ` Alvaro Gamez Machado
2019-10-24 13:11       ` Mark Brown
2019-10-24 13:18         ` Alvaro Gamez Machado [this message]
2019-10-24 13:41           ` Mark Brown
2019-10-24 14:07             ` Alvaro Gamez Machado
2019-10-24 17:40               ` Mark Brown
2019-10-25  6:39                 ` Alvaro Gamez Machado
2019-10-25 11:56                   ` Mark Brown
2019-10-28  9:43                     ` Alvaro Gamez Machado

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