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Thu, 24 Oct 2019 14:18:04 +0000 (UTC) Received: from redhat.com (ovpn-125-229.rdu2.redhat.com [10.10.125.229]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5B5AC5D712; Thu, 24 Oct 2019 14:18:01 +0000 (UTC) Date: Thu, 24 Oct 2019 10:17:59 -0400 From: Jerome Glisse To: Kenneth Lee Cc: Zhangfei Gao , Greg Kroah-Hartman , Arnd Bergmann , Herbert Xu , jonathan.cameron@huawei.com, grant.likely@arm.com, jean-philippe , ilias.apalodimas@linaro.org, francois.ozog@linaro.org, Wangzhou , "haojian . zhuang" , Zaibo Xu , linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, Kenneth Lee , linux-accelerators@lists.ozlabs.org Subject: Re: [PATCH v6 2/3] uacce: add uacce driver Message-ID: <20191024141759.GA4793@redhat.com> References: <1571214873-27359-1-git-send-email-zhangfei.gao@linaro.org> <1571214873-27359-3-git-send-email-zhangfei.gao@linaro.org> <20191022184929.GC5169@redhat.com> <20191024064129.GB17723@kllp10> MIME-Version: 1.0 In-Reply-To: <20191024064129.GB17723@kllp10> User-Agent: Mutt/1.12.1 (2019-06-15) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: qxqBDIHWOzK-fIZtGMOReA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Thu, Oct 24, 2019 at 02:41:29PM +0800, Kenneth Lee wrote: > On Tue, Oct 22, 2019 at 02:49:29PM -0400, Jerome Glisse wrote: > > Date: Tue, 22 Oct 2019 14:49:29 -0400 > > From: Jerome Glisse > > To: Zhangfei Gao > > Cc: Greg Kroah-Hartman , Arnd Bergmann > > , Herbert Xu , > > jonathan.cameron@huawei.com, grant.likely@arm.com, jean-philippe > > , ilias.apalodimas@linaro.org, > > francois.ozog@linaro.org, kenneth-lee-2012@foxmail.com, Wangzhou > > , "haojian . zhuang" , > > Zaibo Xu , linux-kernel@vger.kernel.org, > > linux-crypto@vger.kernel.org, Kenneth Lee , > > linux-accelerators@lists.ozlabs.org > > Subject: Re: [PATCH v6 2/3] uacce: add uacce driver > > Message-ID: <20191022184929.GC5169@redhat.com> > >=20 > > On Wed, Oct 16, 2019 at 04:34:32PM +0800, Zhangfei Gao wrote: > > > From: Kenneth Lee > > >=20 > > > Uacce (Unified/User-space-access-intended Accelerator Framework) targ= ets to > > > provide Shared Virtual Addressing (SVA) between accelerators and proc= esses. > > > So accelerator can access any data structure of the main cpu. > > > This differs from the data sharing between cpu and io device, which s= hare > > > data content rather than address. > > > Since unified address, hardware and user space of process can share t= he > > > same virtual address in the communication. > > >=20 > > > Uacce create a chrdev for every registration, the queue is allocated = to > > > the process when the chrdev is opened. Then the process can access th= e > > > hardware resource by interact with the queue file. By mmap the queue > > > file space to user space, the process can directly put requests to th= e > > > hardware without syscall to the kernel space. > >=20 > > You need to remove all API that is not use by your first driver as > > it will most likely bit rot without users. It is way better to add > > things when a driver start to make use of it. >=20 > Yes. Good point. Thank you:) >=20 > >=20 > > I am still not convince of the value of adding a new framework here > > with only a single device as an example. It looks similar to some of > > the fpga devices. Saddly because framework layering is not something > > that exist i guess inventing a new framework is the only answer when > > you can not quite fit into an existing one. > >=20 > > More fundamental question is why do you need to change the IOMMU > > domain of the device ? I do not see any reason for that unless the > > PASID has some restriction on ARM that i do not know of. >=20 > But I think this is the only way. As my understanding, by default, the > system creates a DMA IOMMU domain for each device behine an IOMMU. If > you want to call iommu interface directly, we have to rebind the device > to an unmanaged domain. Why would you need to call iommu directly ? On some GPUs we do use PASID and we do not rebind to different domain, we just don't mess with that. So i do not see any reason to change the domain. Cheers, J=E9r=F4me