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From: Andes <uboot@andestech.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 5/8] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL
Date: Fri, 25 Oct 2019 14:10:24 +0800	[thread overview]
Message-ID: <20191025061027.20962-6-uboot@andestech.com> (raw)
In-Reply-To: <20191025061027.20962-1-uboot@andestech.com>

From: Rick Chen <rick@andestech.com>

The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
---
 arch/riscv/cpu/ax25/cache.c | 60 ++++++++++++++++++++++++++++++++++-----------
 1 file changed, 46 insertions(+), 14 deletions(-)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 41de30c..9437e81 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -11,18 +11,46 @@
 #include <asm/csr.h>
 
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
 /* mcctlcommand */
 #define CCTL_REG_MCCTLCOMMAND_NUM	0x7cc
 
 /* D-cache operation */
 #define CCTL_L1D_WBINVAL_ALL	6
 #endif
+#endif
+
+#ifdef CONFIG_V5L2_CACHE
+static void _cache_enable(void)
+{
+	struct udevice *dev = NULL;
+
+	uclass_find_first_device(UCLASS_CACHE, &dev);
+
+	if (dev)
+		cache_enable(dev);
+}
+
+static void _cache_disable(void)
+{
+	struct udevice *dev = NULL;
+
+	uclass_find_first_device(UCLASS_CACHE, &dev);
+
+	if (dev)
+		cache_disable(dev);
+}
+#endif
 
 void flush_dcache_all(void)
 {
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
 	csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
 #endif
+#endif
+#endif
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)
@@ -39,6 +67,7 @@ void icache_enable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
 	asm volatile (
 		"csrr t1, mcache_ctl\n\t"
 		"ori t0, t1, 0x1\n\t"
@@ -46,12 +75,14 @@ void icache_enable(void)
 	);
 #endif
 #endif
+#endif
 }
 
 void icache_disable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
 	asm volatile (
 		"fence.i\n\t"
 		"csrr t1, mcache_ctl\n\t"
@@ -60,24 +91,23 @@ void icache_disable(void)
 	);
 #endif
 #endif
+#endif
 }
 
 void dcache_enable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
-	struct udevice *dev = NULL;
-
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
 	asm volatile (
 		"csrr t1, mcache_ctl\n\t"
 		"ori t0, t1, 0x2\n\t"
 		"csrw mcache_ctl, t0\n\t"
 	);
-
-	uclass_find_first_device(UCLASS_CACHE, &dev);
-
-	if (dev)
-		cache_enable(dev);
+#endif
+#ifdef CONFIG_V5L2_CACHE
+	_cache_enable();
+#endif
 #endif
 #endif
 }
@@ -86,19 +116,17 @@ void dcache_disable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
-	struct udevice *dev = NULL;
-
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
 	csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
 	asm volatile (
 		"csrr t1, mcache_ctl\n\t"
 		"andi t0, t1, ~0x2\n\t"
 		"csrw mcache_ctl, t0\n\t"
 	);
-
-	uclass_find_first_device(UCLASS_CACHE, &dev);
-
-	if (dev)
-		cache_disable(dev);
+#endif
+#ifdef CONFIG_V5L2_CACHE
+	_cache_disable();
+#endif
 #endif
 #endif
 }
@@ -108,6 +136,7 @@ int icache_status(void)
 	int ret = 0;
 
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
 	asm volatile (
 		"csrr t1, mcache_ctl\n\t"
 		"andi	%0, t1, 0x01\n\t"
@@ -116,6 +145,7 @@ int icache_status(void)
 		: "memory"
 	);
 #endif
+#endif
 
 	return ret;
 }
@@ -125,6 +155,7 @@ int dcache_status(void)
 	int ret = 0;
 
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
 	asm volatile (
 		"csrr t1, mcache_ctl\n\t"
 		"andi	%0, t1, 0x02\n\t"
@@ -133,6 +164,7 @@ int dcache_status(void)
 		: "memory"
 	);
 #endif
+#endif
 
 	return ret;
 }
-- 
2.7.4

  parent reply	other threads:[~2019-10-25  6:10 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-25  6:10 [U-Boot] [PATCH 0/8] RISC-V AX25-AE350 support SPL Andes
2019-10-25  6:10 ` [U-Boot] [PATCH 1/8] riscv: ax25: add SPL support Andes
2019-10-29 14:29   ` Bin Meng
2019-10-30  0:42     ` Rick Chen
2019-10-30 10:06       ` Bin Meng
2019-10-31  2:11         ` Rick Chen
2019-10-25  6:10 ` [U-Boot] [PATCH 2/8] riscv: ax25-ae350: add SPL configuration Andes
2019-10-29 14:39   ` Bin Meng
2019-10-30  2:06     ` Rick Chen
2019-10-25  6:10 ` [U-Boot] [PATCH 3/8] riscv: ax25-ae350: Use generic memory size setup Andes
2019-10-29 14:42   ` Bin Meng
2019-10-30  2:19     ` Rick Chen
2019-10-25  6:10 ` [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations Andes
2019-10-29 14:51   ` Bin Meng
2019-10-30  2:50     ` Rick Chen
2019-10-30 10:38       ` Bin Meng
2019-10-31  1:00         ` Alan Kao
2019-10-31  3:36           ` Bin Meng
2019-10-31  7:48             ` Alan Kao
2019-10-31  8:10               ` Bin Meng
2019-10-31  8:12           ` Anup Patel
2019-10-31 10:43             ` Anup Patel
2019-11-01  5:25               ` Rick Chen
2019-11-05  1:50                 ` Rick Chen
2019-11-05  6:34                   ` Anup Patel
2019-11-06  6:44                     ` Rick Chen
2019-11-06  8:48                       ` Anup Patel
2019-11-06  8:58                         ` Anup Patel
2019-11-06  9:21                           ` Rick Chen
2019-11-06 11:11                             ` Anup Patel
2019-11-07  1:34                               ` Rick Chen
2019-11-07  5:15                                 ` Anup Patel
2019-11-07  5:45                                   ` Anup Patel
2019-11-07  6:10                                     ` Rick Chen
2019-11-07  6:18                                       ` Anup Patel
2019-11-07  9:41                                         ` Auer, Lukas
2019-11-07 10:44                                           ` Anup Patel
2019-11-07 11:41                                             ` Rick Chen
2019-11-07 12:22                                               ` Anup Patel
2019-11-08  1:23                                                 ` Rick Chen
2019-11-08 12:14                                                   ` Anup Patel
2019-11-07 18:44                                               ` Atish Patra
2019-11-08  1:13                                                 ` Rick Chen
2019-11-08  7:27                                                   ` Rick Chen
2019-11-08  8:59                                                     ` Auer, Lukas
2019-11-11  7:19                                                       ` Rick Chen
2019-11-12  9:47                                                         ` Auer, Lukas
2019-11-13  3:42                                                           ` Rick Chen
2019-11-14  7:27                                                             ` Anup Patel
2019-11-14 17:10                                                               ` Auer, Lukas
2019-11-07 11:44                                             ` Auer, Lukas
2019-11-07 12:27                                               ` Anup Patel
2019-11-07 13:37                                                 ` Auer, Lukas
2019-10-31  2:23         ` Rick Chen
2019-10-25  6:10 ` Andes [this message]
2019-10-29 14:59   ` [U-Boot] [PATCH 5/8] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL Bin Meng
2019-10-31  2:31     ` Rick Chen
2019-10-31  3:00       ` Bin Meng
2019-10-25  6:10 ` [U-Boot] [PATCH 6/8] spl: cache: Allow cache drivers in SPL Andes
2019-10-29 15:14   ` Bin Meng
2019-10-31  2:52     ` Rick Chen
2019-10-31  3:01       ` Bin Meng
2019-10-31  3:22         ` Rick Chen
2019-10-25  6:10 ` [U-Boot] [PATCH 7/8] riscv: Fix clear bss loop in the start-up code Andes
2019-10-29 15:16   ` Bin Meng
2019-10-31  3:10     ` Rick Chen
2019-10-31 12:55       ` Bin Meng
2019-11-01  5:24         ` Rick Chen
2019-10-25  6:10 ` [U-Boot] [PATCH 8/8] riscv: dts: Support four cores SMP Andes
2019-10-29 15:17   ` Bin Meng
2019-10-31  5:57     ` Rick Chen

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