* [PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
@ 2019-10-25 23:26 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2019-10-25 23:26 UTC (permalink / raw)
To: intel-gfx
The location of RING_MI_MODE (used to stop the ring across resets) moved
for Tigerlake. Fixup the new location and include a selftest to verify
the location in the default context image.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 18 +++++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 73 ++++++++++++++++++++++++++
2 files changed, 88 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 523de1fd4452..a87496659cca 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2935,14 +2935,26 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
&execlists->csb_status[reset_value]);
}
+static int ctx_ring_mi_mode(const struct intel_engine_cs *engine)
+{
+ if (INTEL_GEN(engine->i915) >= 12)
+ return 0x60;
+ else if (INTEL_GEN(engine->i915) >= 9)
+ return 0x54;
+ else
+ return -1;
+}
+
static void __execlists_reset_reg_state(const struct intel_context *ce,
const struct intel_engine_cs *engine)
{
u32 *regs = ce->lrc_reg_state;
+ int x;
- if (INTEL_GEN(engine->i915) >= 9) {
- regs[GEN9_CTX_RING_MI_MODE + 1] &= ~STOP_RING;
- regs[GEN9_CTX_RING_MI_MODE + 1] |= STOP_RING << 16;
+ x = ctx_ring_mi_mode(engine);
+ if (x != -1) {
+ regs[x + 1] &= ~STOP_RING;
+ regs[x + 1] |= STOP_RING << 16;
}
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d5d268be554e..902110689f50 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -3165,6 +3165,78 @@ static int live_lrc_layout(void *arg)
return err;
}
+static int find_offset(const u32 *lri, u32 offset)
+{
+ int i;
+
+ for (i = 0; i < PAGE_SIZE / sizeof(u32); i++)
+ if (lri[i] == offset)
+ return i;
+
+ return -1;
+}
+
+static int live_lrc_fixed(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err;
+
+ /*
+ * Check the assumed register offsets match the actual locations in
+ * the context image.
+ */
+
+ err = 0;
+ for_each_engine(engine, gt, id) {
+ const struct {
+ u32 reg;
+ u32 offset;
+ const char *name;
+ } tbl[] = {
+ {
+ i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),
+ ctx_ring_mi_mode(engine),
+ "RING_MI_MODE",
+ },
+ { },
+ }, *t;
+ u32 *hw;
+
+ if (!engine->default_state)
+ continue;
+
+ hw = i915_gem_object_pin_map(engine->default_state,
+ I915_MAP_WB);
+ if (IS_ERR(hw)) {
+ err = PTR_ERR(hw);
+ break;
+ }
+ hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
+
+ for (t = tbl; t->name; t++) {
+ int dw = find_offset(hw, t->reg);
+
+ if (dw != t->offset) {
+ pr_err("%s: Offset for %s [0x%x] mismatch, found %x, expected %x\n",
+ engine->name,
+ t->name,
+ t->reg,
+ dw,
+ t->offset);
+ err = -EINVAL;
+ }
+ }
+
+ i915_gem_object_unpin_map(engine->default_state);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
static int __live_lrc_state(struct i915_gem_context *fixme,
struct intel_engine_cs *engine,
struct i915_vma *scratch)
@@ -3437,6 +3509,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_lrc_layout),
+ SUBTEST(live_lrc_fixed),
SUBTEST(live_lrc_state),
SUBTEST(live_gpr_clear),
};
--
2.24.0.rc1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
@ 2019-10-25 23:26 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2019-10-25 23:26 UTC (permalink / raw)
To: intel-gfx
The location of RING_MI_MODE (used to stop the ring across resets) moved
for Tigerlake. Fixup the new location and include a selftest to verify
the location in the default context image.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 18 +++++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 73 ++++++++++++++++++++++++++
2 files changed, 88 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 523de1fd4452..a87496659cca 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2935,14 +2935,26 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
&execlists->csb_status[reset_value]);
}
+static int ctx_ring_mi_mode(const struct intel_engine_cs *engine)
+{
+ if (INTEL_GEN(engine->i915) >= 12)
+ return 0x60;
+ else if (INTEL_GEN(engine->i915) >= 9)
+ return 0x54;
+ else
+ return -1;
+}
+
static void __execlists_reset_reg_state(const struct intel_context *ce,
const struct intel_engine_cs *engine)
{
u32 *regs = ce->lrc_reg_state;
+ int x;
- if (INTEL_GEN(engine->i915) >= 9) {
- regs[GEN9_CTX_RING_MI_MODE + 1] &= ~STOP_RING;
- regs[GEN9_CTX_RING_MI_MODE + 1] |= STOP_RING << 16;
+ x = ctx_ring_mi_mode(engine);
+ if (x != -1) {
+ regs[x + 1] &= ~STOP_RING;
+ regs[x + 1] |= STOP_RING << 16;
}
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d5d268be554e..902110689f50 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -3165,6 +3165,78 @@ static int live_lrc_layout(void *arg)
return err;
}
+static int find_offset(const u32 *lri, u32 offset)
+{
+ int i;
+
+ for (i = 0; i < PAGE_SIZE / sizeof(u32); i++)
+ if (lri[i] == offset)
+ return i;
+
+ return -1;
+}
+
+static int live_lrc_fixed(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err;
+
+ /*
+ * Check the assumed register offsets match the actual locations in
+ * the context image.
+ */
+
+ err = 0;
+ for_each_engine(engine, gt, id) {
+ const struct {
+ u32 reg;
+ u32 offset;
+ const char *name;
+ } tbl[] = {
+ {
+ i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),
+ ctx_ring_mi_mode(engine),
+ "RING_MI_MODE",
+ },
+ { },
+ }, *t;
+ u32 *hw;
+
+ if (!engine->default_state)
+ continue;
+
+ hw = i915_gem_object_pin_map(engine->default_state,
+ I915_MAP_WB);
+ if (IS_ERR(hw)) {
+ err = PTR_ERR(hw);
+ break;
+ }
+ hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
+
+ for (t = tbl; t->name; t++) {
+ int dw = find_offset(hw, t->reg);
+
+ if (dw != t->offset) {
+ pr_err("%s: Offset for %s [0x%x] mismatch, found %x, expected %x\n",
+ engine->name,
+ t->name,
+ t->reg,
+ dw,
+ t->offset);
+ err = -EINVAL;
+ }
+ }
+
+ i915_gem_object_unpin_map(engine->default_state);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
static int __live_lrc_state(struct i915_gem_context *fixme,
struct intel_engine_cs *engine,
struct i915_vma *scratch)
@@ -3437,6 +3509,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_lrc_layout),
+ SUBTEST(live_lrc_fixed),
SUBTEST(live_lrc_state),
SUBTEST(live_gpr_clear),
};
--
2.24.0.rc1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
@ 2019-10-26 1:40 ` Patchwork
0 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-10-26 1:40 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
URL : https://patchwork.freedesktop.org/series/68591/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7191 -> Patchwork_14994
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14994 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14994, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14994:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_blt:
- fi-bsw-n3050: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-bsw-n3050/igt@i915_selftest@live_blt.html
- fi-hsw-peppy: [PASS][2] -> [DMESG-FAIL][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-hsw-peppy/igt@i915_selftest@live_blt.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-hsw-peppy/igt@i915_selftest@live_blt.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_selftest@live_gt_lrc}:
- fi-bdw-5557u: [PASS][4] -> [DMESG-FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-bdw-5557u/igt@i915_selftest@live_gt_lrc.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-bdw-5557u/igt@i915_selftest@live_gt_lrc.html
- fi-bsw-kefka: [PASS][6] -> [DMESG-FAIL][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-bsw-kefka/igt@i915_selftest@live_gt_lrc.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-bsw-kefka/igt@i915_selftest@live_gt_lrc.html
- fi-bsw-n3050: NOTRUN -> [DMESG-FAIL][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-bsw-n3050/igt@i915_selftest@live_gt_lrc.html
Known issues
------------
Here are the changes found in Patchwork_14994 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#111045] / [fdo#111096])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_close_race@basic-process:
- fi-icl-u3: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-u3/igt@gem_close_race@basic-process.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-icl-u3/igt@gem_close_race@basic-process.html
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [INCOMPLETE][13] ([fdo#107713]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-kefka: [INCOMPLETE][15] -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-guc}: [INCOMPLETE][17] ([fdo#107713] / [fdo#108569]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (50 -> 43)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7191 -> Patchwork_14994
CI-20190529: 20190529
CI_DRM_7191: 59c58784011dbec9a742d33b3d8d673393b95112 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5242: 15c11e2df77f769b5fa9ca5b40a94f266370a479 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14994: 2197c5ab1f1ad9d570d725fc529230b2afd8f266 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2197c5ab1f1a drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
@ 2019-10-26 1:40 ` Patchwork
0 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-10-26 1:40 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
URL : https://patchwork.freedesktop.org/series/68591/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7191 -> Patchwork_14994
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14994 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14994, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14994:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_blt:
- fi-bsw-n3050: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-bsw-n3050/igt@i915_selftest@live_blt.html
- fi-hsw-peppy: [PASS][2] -> [DMESG-FAIL][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-hsw-peppy/igt@i915_selftest@live_blt.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-hsw-peppy/igt@i915_selftest@live_blt.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_selftest@live_gt_lrc}:
- fi-bdw-5557u: [PASS][4] -> [DMESG-FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-bdw-5557u/igt@i915_selftest@live_gt_lrc.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-bdw-5557u/igt@i915_selftest@live_gt_lrc.html
- fi-bsw-kefka: [PASS][6] -> [DMESG-FAIL][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-bsw-kefka/igt@i915_selftest@live_gt_lrc.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-bsw-kefka/igt@i915_selftest@live_gt_lrc.html
- fi-bsw-n3050: NOTRUN -> [DMESG-FAIL][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-bsw-n3050/igt@i915_selftest@live_gt_lrc.html
Known issues
------------
Here are the changes found in Patchwork_14994 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#111045] / [fdo#111096])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_close_race@basic-process:
- fi-icl-u3: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-u3/igt@gem_close_race@basic-process.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-icl-u3/igt@gem_close_race@basic-process.html
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [INCOMPLETE][13] ([fdo#107713]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-kefka: [INCOMPLETE][15] -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-guc}: [INCOMPLETE][17] ([fdo#107713] / [fdo#108569]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (50 -> 43)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7191 -> Patchwork_14994
CI-20190529: 20190529
CI_DRM_7191: 59c58784011dbec9a742d33b3d8d673393b95112 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5242: 15c11e2df77f769b5fa9ca5b40a94f266370a479 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14994: 2197c5ab1f1ad9d570d725fc529230b2afd8f266 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2197c5ab1f1a drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14994/index.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
2019-10-26 8:22 Chris Wilson
@ 2019-10-28 12:10 ` Joonas Lahtinen
0 siblings, 0 replies; 8+ messages in thread
From: Joonas Lahtinen @ 2019-10-28 12:10 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Quoting Chris Wilson (2019-10-26 11:22:20)
> The location of RING_MI_MODE (used to stop the ring across resets) moved
> for Tigerlake. Fixup the new location and include a selftest to verify
> the location in the default context image.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
2019-10-26 6:17 [PATCH] " Chris Wilson
@ 2019-10-26 14:46 ` Rodrigo Vivi
0 siblings, 0 replies; 8+ messages in thread
From: Rodrigo Vivi @ 2019-10-26 14:46 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Sat, Oct 26, 2019 at 07:17:36AM +0100, Chris Wilson wrote:
> The location of RING_MI_MODE (used to stop the ring across resets) moved
> for Tigerlake. Fixup the new location and include a selftest to verify
> the location in the default context image.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 18 +++++--
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 73 ++++++++++++++++++++++++++
> 2 files changed, 88 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 523de1fd4452..09a12d20987b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2935,14 +2935,26 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
> &execlists->csb_status[reset_value]);
> }
>
> +static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
> +{
> + if (INTEL_GEN(engine->i915) >= 12)
> + return 0x60;
> + else if (INTEL_GEN(engine->i915) >= 9)
> + return 0x54;
> + else
> + return 0x58;
> +}
where are those defined on spec so I could help on review?
anyway, it seems we want now:
intel_lrc_reg.h
- #define GEN9_CTX_RING_MI_MODE 0x54
> +
> static void __execlists_reset_reg_state(const struct intel_context *ce,
> const struct intel_engine_cs *engine)
> {
> u32 *regs = ce->lrc_reg_state;
> + int x;
>
> - if (INTEL_GEN(engine->i915) >= 9) {
> - regs[GEN9_CTX_RING_MI_MODE + 1] &= ~STOP_RING;
> - regs[GEN9_CTX_RING_MI_MODE + 1] |= STOP_RING << 16;
> + x = lrc_ring_mi_mode(engine);
> + if (x != -1) {
> + regs[x + 1] &= ~STOP_RING;
> + regs[x + 1] |= STOP_RING << 16;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index d5d268be554e..46fa17e9ae0b 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -3165,6 +3165,78 @@ static int live_lrc_layout(void *arg)
> return err;
> }
>
> +static int find_offset(const u32 *lri, u32 offset)
> +{
> + int i;
> +
> + for (i = 0; i < PAGE_SIZE / sizeof(u32); i++)
> + if (lri[i] == offset)
> + return i;
> +
> + return -1;
> +}
> +
> +static int live_lrc_fixed(void *arg)
> +{
> + struct intel_gt *gt = arg;
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> + int err;
> +
> + /*
> + * Check the assumed register offsets match the actual locations in
> + * the context image.
> + */
> +
> + err = 0;
> + for_each_engine(engine, gt, id) {
> + const struct {
> + u32 reg;
> + u32 offset;
> + const char *name;
> + } tbl[] = {
> + {
> + i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),
> + lrc_ring_mi_mode(engine),
> + "RING_MI_MODE",
> + },
> + { },
> + }, *t;
> + u32 *hw;
> +
> + if (!engine->default_state)
> + continue;
> +
> + hw = i915_gem_object_pin_map(engine->default_state,
> + I915_MAP_WB);
> + if (IS_ERR(hw)) {
> + err = PTR_ERR(hw);
> + break;
> + }
> + hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
> +
> + for (t = tbl; t->name; t++) {
> + int dw = find_offset(hw, t->reg);
> +
> + if (dw != t->offset) {
> + pr_err("%s: Offset for %s [0x%x] mismatch, found %x, expected %x\n",
> + engine->name,
> + t->name,
> + t->reg,
> + dw,
> + t->offset);
> + err = -EINVAL;
> + }
> + }
> +
> + i915_gem_object_unpin_map(engine->default_state);
> + if (err)
> + break;
> + }
> +
> + return err;
> +}
> +
> static int __live_lrc_state(struct i915_gem_context *fixme,
> struct intel_engine_cs *engine,
> struct i915_vma *scratch)
> @@ -3437,6 +3509,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
> {
> static const struct i915_subtest tests[] = {
> SUBTEST(live_lrc_layout),
> + SUBTEST(live_lrc_fixed),
> SUBTEST(live_lrc_state),
> SUBTEST(live_gpr_clear),
> };
> --
> 2.24.0.rc1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
@ 2019-10-26 8:22 Chris Wilson
2019-10-28 12:10 ` Joonas Lahtinen
0 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2019-10-26 8:22 UTC (permalink / raw)
To: intel-gfx
The location of RING_MI_MODE (used to stop the ring across resets) moved
for Tigerlake. Fixup the new location and include a selftest to verify
the location in the default context image.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 20 +++++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 73 ++++++++++++++++++++++++++
2 files changed, 90 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 523de1fd4452..16340740139d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2935,14 +2935,28 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
&execlists->csb_status[reset_value]);
}
+static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
+{
+ if (INTEL_GEN(engine->i915) >= 12)
+ return 0x60;
+ else if (INTEL_GEN(engine->i915) >= 9)
+ return 0x54;
+ else if (engine->class == RENDER_CLASS)
+ return 0x58;
+ else
+ return -1;
+}
+
static void __execlists_reset_reg_state(const struct intel_context *ce,
const struct intel_engine_cs *engine)
{
u32 *regs = ce->lrc_reg_state;
+ int x;
- if (INTEL_GEN(engine->i915) >= 9) {
- regs[GEN9_CTX_RING_MI_MODE + 1] &= ~STOP_RING;
- regs[GEN9_CTX_RING_MI_MODE + 1] |= STOP_RING << 16;
+ x = lrc_ring_mi_mode(engine);
+ if (x != -1) {
+ regs[x + 1] &= ~STOP_RING;
+ regs[x + 1] |= STOP_RING << 16;
}
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d5d268be554e..46fa17e9ae0b 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -3165,6 +3165,78 @@ static int live_lrc_layout(void *arg)
return err;
}
+static int find_offset(const u32 *lri, u32 offset)
+{
+ int i;
+
+ for (i = 0; i < PAGE_SIZE / sizeof(u32); i++)
+ if (lri[i] == offset)
+ return i;
+
+ return -1;
+}
+
+static int live_lrc_fixed(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err;
+
+ /*
+ * Check the assumed register offsets match the actual locations in
+ * the context image.
+ */
+
+ err = 0;
+ for_each_engine(engine, gt, id) {
+ const struct {
+ u32 reg;
+ u32 offset;
+ const char *name;
+ } tbl[] = {
+ {
+ i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),
+ lrc_ring_mi_mode(engine),
+ "RING_MI_MODE",
+ },
+ { },
+ }, *t;
+ u32 *hw;
+
+ if (!engine->default_state)
+ continue;
+
+ hw = i915_gem_object_pin_map(engine->default_state,
+ I915_MAP_WB);
+ if (IS_ERR(hw)) {
+ err = PTR_ERR(hw);
+ break;
+ }
+ hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
+
+ for (t = tbl; t->name; t++) {
+ int dw = find_offset(hw, t->reg);
+
+ if (dw != t->offset) {
+ pr_err("%s: Offset for %s [0x%x] mismatch, found %x, expected %x\n",
+ engine->name,
+ t->name,
+ t->reg,
+ dw,
+ t->offset);
+ err = -EINVAL;
+ }
+ }
+
+ i915_gem_object_unpin_map(engine->default_state);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
static int __live_lrc_state(struct i915_gem_context *fixme,
struct intel_engine_cs *engine,
struct i915_vma *scratch)
@@ -3437,6 +3509,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_lrc_layout),
+ SUBTEST(live_lrc_fixed),
SUBTEST(live_lrc_state),
SUBTEST(live_gpr_clear),
};
--
2.24.0.rc1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
@ 2019-10-26 6:17 Chris Wilson
2019-10-26 14:46 ` Rodrigo Vivi
0 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2019-10-26 6:17 UTC (permalink / raw)
To: intel-gfx
The location of RING_MI_MODE (used to stop the ring across resets) moved
for Tigerlake. Fixup the new location and include a selftest to verify
the location in the default context image.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 18 +++++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 73 ++++++++++++++++++++++++++
2 files changed, 88 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 523de1fd4452..09a12d20987b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2935,14 +2935,26 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
&execlists->csb_status[reset_value]);
}
+static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
+{
+ if (INTEL_GEN(engine->i915) >= 12)
+ return 0x60;
+ else if (INTEL_GEN(engine->i915) >= 9)
+ return 0x54;
+ else
+ return 0x58;
+}
+
static void __execlists_reset_reg_state(const struct intel_context *ce,
const struct intel_engine_cs *engine)
{
u32 *regs = ce->lrc_reg_state;
+ int x;
- if (INTEL_GEN(engine->i915) >= 9) {
- regs[GEN9_CTX_RING_MI_MODE + 1] &= ~STOP_RING;
- regs[GEN9_CTX_RING_MI_MODE + 1] |= STOP_RING << 16;
+ x = lrc_ring_mi_mode(engine);
+ if (x != -1) {
+ regs[x + 1] &= ~STOP_RING;
+ regs[x + 1] |= STOP_RING << 16;
}
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d5d268be554e..46fa17e9ae0b 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -3165,6 +3165,78 @@ static int live_lrc_layout(void *arg)
return err;
}
+static int find_offset(const u32 *lri, u32 offset)
+{
+ int i;
+
+ for (i = 0; i < PAGE_SIZE / sizeof(u32); i++)
+ if (lri[i] == offset)
+ return i;
+
+ return -1;
+}
+
+static int live_lrc_fixed(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err;
+
+ /*
+ * Check the assumed register offsets match the actual locations in
+ * the context image.
+ */
+
+ err = 0;
+ for_each_engine(engine, gt, id) {
+ const struct {
+ u32 reg;
+ u32 offset;
+ const char *name;
+ } tbl[] = {
+ {
+ i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),
+ lrc_ring_mi_mode(engine),
+ "RING_MI_MODE",
+ },
+ { },
+ }, *t;
+ u32 *hw;
+
+ if (!engine->default_state)
+ continue;
+
+ hw = i915_gem_object_pin_map(engine->default_state,
+ I915_MAP_WB);
+ if (IS_ERR(hw)) {
+ err = PTR_ERR(hw);
+ break;
+ }
+ hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
+
+ for (t = tbl; t->name; t++) {
+ int dw = find_offset(hw, t->reg);
+
+ if (dw != t->offset) {
+ pr_err("%s: Offset for %s [0x%x] mismatch, found %x, expected %x\n",
+ engine->name,
+ t->name,
+ t->reg,
+ dw,
+ t->offset);
+ err = -EINVAL;
+ }
+ }
+
+ i915_gem_object_unpin_map(engine->default_state);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
static int __live_lrc_state(struct i915_gem_context *fixme,
struct intel_engine_cs *engine,
struct i915_vma *scratch)
@@ -3437,6 +3509,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_lrc_layout),
+ SUBTEST(live_lrc_fixed),
SUBTEST(live_lrc_state),
SUBTEST(live_gpr_clear),
};
--
2.24.0.rc1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-10-28 12:10 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-25 23:26 [PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image Chris Wilson
2019-10-25 23:26 ` [Intel-gfx] " Chris Wilson
2019-10-26 1:40 ` ✗ Fi.CI.BAT: failure for " Patchwork
2019-10-26 1:40 ` [Intel-gfx] " Patchwork
2019-10-26 6:17 [PATCH] " Chris Wilson
2019-10-26 14:46 ` Rodrigo Vivi
2019-10-26 8:22 Chris Wilson
2019-10-28 12:10 ` Joonas Lahtinen
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