* [PATCH v10 0/2] Refactor Gen11+ SAGV support
@ 2019-11-01 12:35 ` Stanislav Lisovskiy
0 siblings, 0 replies; 12+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-01 12:35 UTC (permalink / raw)
To: intel-gfx
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
Stanislav Lisovskiy (2):
drm/i915: Refactor intel_can_enable_sagv
drm/i915: Restrict qgv points which don't have enough bandwidth.
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 108 +++++--
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 61 +++-
.../drm/i915/display/intel_display_types.h | 12 +
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 299 +++++++++++++++++-
drivers/gpu/drm/i915/intel_sideband.c | 27 +-
9 files changed, 487 insertions(+), 43 deletions(-)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v10 0/2] Refactor Gen11+ SAGV support
@ 2019-11-01 12:35 ` Stanislav Lisovskiy
0 siblings, 0 replies; 12+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-01 12:35 UTC (permalink / raw)
To: intel-gfx
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
Stanislav Lisovskiy (2):
drm/i915: Refactor intel_can_enable_sagv
drm/i915: Restrict qgv points which don't have enough bandwidth.
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 108 +++++--
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 61 +++-
.../drm/i915/display/intel_display_types.h | 12 +
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 299 +++++++++++++++++-
drivers/gpu/drm/i915/intel_sideband.c | 27 +-
9 files changed, 487 insertions(+), 43 deletions(-)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v10 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-01 12:35 ` Stanislav Lisovskiy
0 siblings, 0 replies; 12+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-01 12:35 UTC (permalink / raw)
To: intel-gfx
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
v5: - Added SAGV global state to dev_priv, because
we need to track all pipes, not only those
in atomic state. Each pipe has now correspondent
bit mask reflecting, whether it can tolerate
SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
usage check.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +
.../drm/i915/display/intel_display_types.h | 9 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/intel_pm.c | 299 +++++++++++++++++-
4 files changed, 304 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 348ce0456696..8d1881de0bab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14729,6 +14729,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (dev_priv->display.optimize_watermarks)
dev_priv->display.optimize_watermarks(state,
new_crtc_state);
+ if (state->crtc_sagv_mask & BIT(crtc->pipe))
+ dev_priv->crtc_sagv_mask |= BIT(crtc->pipe);
+ else
+ dev_priv->crtc_sagv_mask &= ~BIT(crtc->pipe);
}
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4341bd66a418..38cbabc79b2f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -490,6 +490,14 @@ struct intel_atomic_state {
*/
u8 active_pipe_changes;
+ /*
+ * Contains a mask which reflects whether correspondent pipe
+ * can tolerate SAGV or not, so that we can make a decision
+ * at atomic_commit_tail stage, whether we enable it or not
+ * based on global state in dev_priv.
+ */
+ u32 crtc_sagv_mask;
+
u8 active_pipes;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
@@ -650,6 +658,7 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
bool is_planar;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4bfd842e2914..60f1c4cc3eeb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1172,6 +1172,12 @@ struct drm_i915_private {
u32 sagv_block_time_us;
+ /*
+ * Contains a bit mask, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u32 crtc_sagv_mask;
+
struct {
/*
* Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5d2b460d3ee5..45a966ade1f7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3741,7 +3741,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static void skl_set_sagv_mask(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3751,21 +3751,23 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
enum pipe pipe;
int level, latency;
+ state->crtc_sagv_mask = 0;
+
if (!intel_has_sagv(dev_priv))
- return false;
+ return;
/*
* If there are no active CRTCs, no additional checks need be performed
*/
if (hweight8(state->active_pipes) == 0)
- return true;
+ return;
/*
* SKL+ workaround: bspec recommends we disable SAGV when we have
* more then one pipe enabled
*/
if (hweight8(state->active_pipes) > 1)
- return false;
+ return;
/* Since we're now guaranteed to only have one active CRTC... */
pipe = ffs(state->active_pipes) - 1;
@@ -3773,7 +3775,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
crtc_state = to_intel_crtc_state(crtc->base.state);
if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
- return false;
+ return;
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct skl_plane_wm *wm =
@@ -3801,9 +3803,127 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
* can't enable SAGV.
*/
if (latency < dev_priv->sagv_block_time_us)
- return false;
+ return;
+ }
+
+ state->crtc_sagv_mask |= BIT(crtc->pipe);
+}
+
+static void tgl_set_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_set_sagv_mask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int level, latency;
+ int i;
+ int plane_id;
+
+ state->crtc_sagv_mask = 0;
+
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * If there are no active CRTCs, no additional checks need be performed
+ */
+ if (hweight8(state->active_pipes) == 0)
+ return;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ unsigned int flags = crtc->base.state->adjusted_mode.flags;
+ bool can_sagv;
+
+ if (flags & DRM_MODE_FLAG_INTERLACE)
+ continue;
+
+ if (!new_crtc_state->base.active)
+ continue;
+
+ can_sagv = true;
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ struct skl_plane_wm *wm =
+ &new_crtc_state->wm.skl.optimal.planes[plane_id];
+
+ /* Skip this plane if it's not enabled */
+ if (!wm->wm[0].plane_en)
+ continue;
+
+ /* Find the highest enabled wm level for this plane */
+ for (level = ilk_wm_max_level(dev_priv);
+ !wm->wm[level].plane_en; --level) {
+ }
+
+ latency = dev_priv->wm.skl_latency[level];
+
+ /*
+ * If any of the planes on this pipe don't enable
+ * wm levels that incur memory latencies higher than
+ * sagv_block_time_us we can't enable SAGV.
+ */
+ if (latency < dev_priv->sagv_block_time_us) {
+ can_sagv = false;
+ break;
+ }
+ }
+ if (can_sagv)
+ state->crtc_sagv_mask |= BIT(crtc->pipe);
}
+}
+
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_set_sagv_mask(state);
+ else if (INTEL_GEN(dev_priv) == 11)
+ icl_set_sagv_mask(state);
+ else
+ skl_set_sagv_mask(state);
+ /*
+ * For SAGV we need to account all the pipes,
+ * not only the ones which are in state currently.
+ */
+ for_each_pipe(dev_priv, pipe) {
+ unsigned int active_pipes;
+ /*
+ * Figure out if we are changing active pipes here
+ * then after commit dev_priv->active_pipes will
+ * anyway be assigned to state->active_pipes.
+ */
+ if (state->active_pipe_changes)
+ active_pipes = state->active_pipes;
+ else
+ active_pipes = dev_priv->active_pipes;
+
+ /* Skip if pipe is inactive */
+ if (!(BIT(pipe) & active_pipes))
+ continue;
+
+ /*
+ * Pipe can be active in this state or in dev_priv
+ * as we haven't committed thise changes yet(and we shouldn't)
+ * - we need to check both.
+ */
+ if (state->active_pipe_changes & BIT(pipe)) {
+ bool state_sagv_masked = \
+ (BIT(pipe) & state->crtc_sagv_mask) == 0;
+ if (state_sagv_masked)
+ return false;
+ } else {
+ bool sagv_masked = \
+ (BIT(pipe) & dev_priv->crtc_sagv_mask) == 0;
+ if (sagv_masked)
+ return false;
+ }
+ }
return true;
}
@@ -3903,7 +4023,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
enum pipe pipe = crtc->pipe;
int hdisplay, vdisplay;
- if (!crtc_state->base.enable)
+ if (!crtc_state->base.active)
continue;
drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
@@ -3926,6 +4046,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
int color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
@@ -3948,7 +4069,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
WARN_ON(ret);
for (level = 0; level <= max_level; level++) {
- skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+ u32 latency = dev_priv->wm.skl_latency[level];
+
+ skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4213,6 +4337,68 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
return total_data_rate;
}
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+ struct skl_ddb_allocation *ddb /* out */)
+{
+ struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+ u16 alloc_size;
+ u16 total[I915_MAX_PLANES] = {};
+ u64 total_data_rate;
+ enum plane_id plane_id;
+ int num_active;
+ u64 plane_data_rate[I915_MAX_PLANES] = {};
+ u32 blocks;
+
+ /*
+ * No need to check gen here, we call this only for gen12
+ */
+ total_data_rate =
+ icl_get_total_relative_data_rate(crtc_state,
+ plane_data_rate);
+
+ skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+ total_data_rate,
+ ddb, alloc, &num_active);
+ alloc_size = skl_ddb_entry_size(alloc);
+ if (alloc_size == 0)
+ return -ENOSPC;
+
+ /* Allocate fixed number of blocks for cursor. */
+ total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
+ alloc_size -= total[PLANE_CURSOR];
+ crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
+ alloc->end - total[PLANE_CURSOR];
+ crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
+
+ /*
+ * Do check if we can fit L0 + sagv_block_time and
+ * disable SAGV if we can't.
+ */
+ blocks = 0;
+ for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ if (plane_id == PLANE_CURSOR) {
+ if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
+ total[PLANE_CURSOR])) {
+ blocks = U32_MAX;
+ break;
+ }
+ continue;
+ }
+
+ blocks += wm->sagv_wm0.min_ddb_alloc;
+ if (blocks > alloc_size)
+ return -ENOSPC;
+ }
+ return 0;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
struct skl_ddb_allocation *ddb /* out */)
@@ -4642,12 +4828,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
- u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -4768,20 +4954,45 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ bool yuv)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
+ u32 latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, wm_params,
- result_prev, result);
+ skl_compute_plane_wm(crtc_state, level, latency,
+ wm_params, result_prev, result);
result_prev = result;
}
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ &plane_wm->sagv_wm0);
+ } else
+ memcpy(&plane_wm->sagv_wm0, &levels[0],
+ sizeof(struct skl_wm_level));
}
static u32
@@ -4874,7 +5085,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -4896,7 +5107,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
return 0;
}
@@ -5168,6 +5379,8 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
return 0;
}
+static void tgl_set_sagv_wm0(struct intel_atomic_state *state);
+
static int
skl_compute_ddb(struct intel_atomic_state *state)
{
@@ -5178,6 +5391,11 @@ skl_compute_ddb(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int ret, i;
+ /* For Gen12+ for SAGV we have a special L0 wm values */
+ if (INTEL_GEN(dev_priv) >= 12)
+ if (intel_can_enable_sagv(state))
+ tgl_set_sagv_wm0(state);
+
memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
@@ -5444,6 +5662,56 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
return 0;
}
+void tgl_set_sagv_wm0(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ struct drm_device *dev = state->base.dev;
+ const struct drm_i915_private *dev_priv = to_i915(dev);
+ int i;
+
+ /*
+ * If we determined that we can actually enable SAGV, then
+ * actually use those levels tgl_check_pipe_fits_sagv_wm
+ * has already taken care of checking if L0 + sagv block time
+ * fits into ddb.
+ */
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ struct intel_plane *plane;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ enum plane_id plane_id = plane->id;
+
+ struct skl_plane_wm *plane_wm = \
+ &new_crtc_state->wm.skl.optimal.planes[plane_id];
+ struct skl_wm_level *sagv_wm0 = &plane_wm->sagv_wm0;
+ struct skl_wm_level *l0_wm0 = &plane_wm->wm[0];
+
+ memcpy(l0_wm0, sagv_wm0, sizeof(struct skl_wm_level));
+ }
+ }
+}
+
+static void tgl_set_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+ int ret, i;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
+ if (!ret) {
+ int pipe_bit = BIT(crtc->pipe);
+ state->crtc_sagv_mask |= pipe_bit;
+ }
+ }
+}
+
static int
skl_compute_wm(struct intel_atomic_state *state)
{
@@ -5456,6 +5724,9 @@ skl_compute_wm(struct intel_atomic_state *state)
/* Clear all dirty flags */
results->dirty_pipes = 0;
+ /* If we exit before check is done */
+ state->crtc_sagv_mask = 0;
+
ret = skl_ddb_add_affected_pipes(state);
if (ret)
return ret;
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v10 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-01 12:35 ` Stanislav Lisovskiy
0 siblings, 0 replies; 12+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-01 12:35 UTC (permalink / raw)
To: intel-gfx
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
v5: - Added SAGV global state to dev_priv, because
we need to track all pipes, not only those
in atomic state. Each pipe has now correspondent
bit mask reflecting, whether it can tolerate
SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
usage check.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +
.../drm/i915/display/intel_display_types.h | 9 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/intel_pm.c | 299 +++++++++++++++++-
4 files changed, 304 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 348ce0456696..8d1881de0bab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14729,6 +14729,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (dev_priv->display.optimize_watermarks)
dev_priv->display.optimize_watermarks(state,
new_crtc_state);
+ if (state->crtc_sagv_mask & BIT(crtc->pipe))
+ dev_priv->crtc_sagv_mask |= BIT(crtc->pipe);
+ else
+ dev_priv->crtc_sagv_mask &= ~BIT(crtc->pipe);
}
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4341bd66a418..38cbabc79b2f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -490,6 +490,14 @@ struct intel_atomic_state {
*/
u8 active_pipe_changes;
+ /*
+ * Contains a mask which reflects whether correspondent pipe
+ * can tolerate SAGV or not, so that we can make a decision
+ * at atomic_commit_tail stage, whether we enable it or not
+ * based on global state in dev_priv.
+ */
+ u32 crtc_sagv_mask;
+
u8 active_pipes;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
@@ -650,6 +658,7 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
bool is_planar;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4bfd842e2914..60f1c4cc3eeb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1172,6 +1172,12 @@ struct drm_i915_private {
u32 sagv_block_time_us;
+ /*
+ * Contains a bit mask, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u32 crtc_sagv_mask;
+
struct {
/*
* Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5d2b460d3ee5..45a966ade1f7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3741,7 +3741,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static void skl_set_sagv_mask(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3751,21 +3751,23 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
enum pipe pipe;
int level, latency;
+ state->crtc_sagv_mask = 0;
+
if (!intel_has_sagv(dev_priv))
- return false;
+ return;
/*
* If there are no active CRTCs, no additional checks need be performed
*/
if (hweight8(state->active_pipes) == 0)
- return true;
+ return;
/*
* SKL+ workaround: bspec recommends we disable SAGV when we have
* more then one pipe enabled
*/
if (hweight8(state->active_pipes) > 1)
- return false;
+ return;
/* Since we're now guaranteed to only have one active CRTC... */
pipe = ffs(state->active_pipes) - 1;
@@ -3773,7 +3775,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
crtc_state = to_intel_crtc_state(crtc->base.state);
if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
- return false;
+ return;
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct skl_plane_wm *wm =
@@ -3801,9 +3803,127 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
* can't enable SAGV.
*/
if (latency < dev_priv->sagv_block_time_us)
- return false;
+ return;
+ }
+
+ state->crtc_sagv_mask |= BIT(crtc->pipe);
+}
+
+static void tgl_set_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_set_sagv_mask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int level, latency;
+ int i;
+ int plane_id;
+
+ state->crtc_sagv_mask = 0;
+
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * If there are no active CRTCs, no additional checks need be performed
+ */
+ if (hweight8(state->active_pipes) == 0)
+ return;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ unsigned int flags = crtc->base.state->adjusted_mode.flags;
+ bool can_sagv;
+
+ if (flags & DRM_MODE_FLAG_INTERLACE)
+ continue;
+
+ if (!new_crtc_state->base.active)
+ continue;
+
+ can_sagv = true;
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ struct skl_plane_wm *wm =
+ &new_crtc_state->wm.skl.optimal.planes[plane_id];
+
+ /* Skip this plane if it's not enabled */
+ if (!wm->wm[0].plane_en)
+ continue;
+
+ /* Find the highest enabled wm level for this plane */
+ for (level = ilk_wm_max_level(dev_priv);
+ !wm->wm[level].plane_en; --level) {
+ }
+
+ latency = dev_priv->wm.skl_latency[level];
+
+ /*
+ * If any of the planes on this pipe don't enable
+ * wm levels that incur memory latencies higher than
+ * sagv_block_time_us we can't enable SAGV.
+ */
+ if (latency < dev_priv->sagv_block_time_us) {
+ can_sagv = false;
+ break;
+ }
+ }
+ if (can_sagv)
+ state->crtc_sagv_mask |= BIT(crtc->pipe);
}
+}
+
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_set_sagv_mask(state);
+ else if (INTEL_GEN(dev_priv) == 11)
+ icl_set_sagv_mask(state);
+ else
+ skl_set_sagv_mask(state);
+ /*
+ * For SAGV we need to account all the pipes,
+ * not only the ones which are in state currently.
+ */
+ for_each_pipe(dev_priv, pipe) {
+ unsigned int active_pipes;
+ /*
+ * Figure out if we are changing active pipes here
+ * then after commit dev_priv->active_pipes will
+ * anyway be assigned to state->active_pipes.
+ */
+ if (state->active_pipe_changes)
+ active_pipes = state->active_pipes;
+ else
+ active_pipes = dev_priv->active_pipes;
+
+ /* Skip if pipe is inactive */
+ if (!(BIT(pipe) & active_pipes))
+ continue;
+
+ /*
+ * Pipe can be active in this state or in dev_priv
+ * as we haven't committed thise changes yet(and we shouldn't)
+ * - we need to check both.
+ */
+ if (state->active_pipe_changes & BIT(pipe)) {
+ bool state_sagv_masked = \
+ (BIT(pipe) & state->crtc_sagv_mask) == 0;
+ if (state_sagv_masked)
+ return false;
+ } else {
+ bool sagv_masked = \
+ (BIT(pipe) & dev_priv->crtc_sagv_mask) == 0;
+ if (sagv_masked)
+ return false;
+ }
+ }
return true;
}
@@ -3903,7 +4023,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
enum pipe pipe = crtc->pipe;
int hdisplay, vdisplay;
- if (!crtc_state->base.enable)
+ if (!crtc_state->base.active)
continue;
drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
@@ -3926,6 +4046,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
int color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
@@ -3948,7 +4069,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
WARN_ON(ret);
for (level = 0; level <= max_level; level++) {
- skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+ u32 latency = dev_priv->wm.skl_latency[level];
+
+ skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4213,6 +4337,68 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
return total_data_rate;
}
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+ struct skl_ddb_allocation *ddb /* out */)
+{
+ struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+ u16 alloc_size;
+ u16 total[I915_MAX_PLANES] = {};
+ u64 total_data_rate;
+ enum plane_id plane_id;
+ int num_active;
+ u64 plane_data_rate[I915_MAX_PLANES] = {};
+ u32 blocks;
+
+ /*
+ * No need to check gen here, we call this only for gen12
+ */
+ total_data_rate =
+ icl_get_total_relative_data_rate(crtc_state,
+ plane_data_rate);
+
+ skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+ total_data_rate,
+ ddb, alloc, &num_active);
+ alloc_size = skl_ddb_entry_size(alloc);
+ if (alloc_size == 0)
+ return -ENOSPC;
+
+ /* Allocate fixed number of blocks for cursor. */
+ total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
+ alloc_size -= total[PLANE_CURSOR];
+ crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
+ alloc->end - total[PLANE_CURSOR];
+ crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
+
+ /*
+ * Do check if we can fit L0 + sagv_block_time and
+ * disable SAGV if we can't.
+ */
+ blocks = 0;
+ for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ if (plane_id == PLANE_CURSOR) {
+ if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
+ total[PLANE_CURSOR])) {
+ blocks = U32_MAX;
+ break;
+ }
+ continue;
+ }
+
+ blocks += wm->sagv_wm0.min_ddb_alloc;
+ if (blocks > alloc_size)
+ return -ENOSPC;
+ }
+ return 0;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
struct skl_ddb_allocation *ddb /* out */)
@@ -4642,12 +4828,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
- u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -4768,20 +4954,45 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ bool yuv)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
+ u32 latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, wm_params,
- result_prev, result);
+ skl_compute_plane_wm(crtc_state, level, latency,
+ wm_params, result_prev, result);
result_prev = result;
}
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ &plane_wm->sagv_wm0);
+ } else
+ memcpy(&plane_wm->sagv_wm0, &levels[0],
+ sizeof(struct skl_wm_level));
}
static u32
@@ -4874,7 +5085,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -4896,7 +5107,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
return 0;
}
@@ -5168,6 +5379,8 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
return 0;
}
+static void tgl_set_sagv_wm0(struct intel_atomic_state *state);
+
static int
skl_compute_ddb(struct intel_atomic_state *state)
{
@@ -5178,6 +5391,11 @@ skl_compute_ddb(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int ret, i;
+ /* For Gen12+ for SAGV we have a special L0 wm values */
+ if (INTEL_GEN(dev_priv) >= 12)
+ if (intel_can_enable_sagv(state))
+ tgl_set_sagv_wm0(state);
+
memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
@@ -5444,6 +5662,56 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
return 0;
}
+void tgl_set_sagv_wm0(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ struct drm_device *dev = state->base.dev;
+ const struct drm_i915_private *dev_priv = to_i915(dev);
+ int i;
+
+ /*
+ * If we determined that we can actually enable SAGV, then
+ * actually use those levels tgl_check_pipe_fits_sagv_wm
+ * has already taken care of checking if L0 + sagv block time
+ * fits into ddb.
+ */
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ struct intel_plane *plane;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ enum plane_id plane_id = plane->id;
+
+ struct skl_plane_wm *plane_wm = \
+ &new_crtc_state->wm.skl.optimal.planes[plane_id];
+ struct skl_wm_level *sagv_wm0 = &plane_wm->sagv_wm0;
+ struct skl_wm_level *l0_wm0 = &plane_wm->wm[0];
+
+ memcpy(l0_wm0, sagv_wm0, sizeof(struct skl_wm_level));
+ }
+ }
+}
+
+static void tgl_set_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+ int ret, i;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
+ if (!ret) {
+ int pipe_bit = BIT(crtc->pipe);
+ state->crtc_sagv_mask |= pipe_bit;
+ }
+ }
+}
+
static int
skl_compute_wm(struct intel_atomic_state *state)
{
@@ -5456,6 +5724,9 @@ skl_compute_wm(struct intel_atomic_state *state)
/* Clear all dirty flags */
results->dirty_pipes = 0;
+ /* If we exit before check is done */
+ state->crtc_sagv_mask = 0;
+
ret = skl_ddb_add_affected_pipes(state);
if (ret)
return ret;
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v10 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-01 12:35 ` Stanislav Lisovskiy
0 siblings, 0 replies; 12+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-01 12:35 UTC (permalink / raw)
To: intel-gfx
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 108 ++++++++++++++----
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 57 ++++++++-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 8 ++
drivers/gpu/drm/i915/intel_sideband.c | 27 ++++-
8 files changed, 183 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 49d5cb1b9e0a..3ab99704e5b8 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -7,6 +7,7 @@
#define __INTEL_ATOMIC_H__
#include <linux/types.h>
+#include "intel_display_types.h"
struct drm_atomic_state;
struct drm_connector;
@@ -39,6 +40,8 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
+int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
+
struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 22e83f857de8..c01b2e8f4f88 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,14 +8,17 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
};
+
struct intel_qgv_info {
- struct intel_qgv_point points[3];
+ struct intel_qgv_point points[NUM_SAGV_POINTS];
u8 num_points;
u8 num_channels;
u8 t_bl;
@@ -113,6 +116,27 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ GEN11_PCODE_POINTS_RESTRICTED_MASK,
+ GEN11_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -270,22 +294,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
- int num_planes)
-{
- if (INTEL_GEN(dev_priv) >= 11)
- /*
- * FIXME with SAGV disabled maybe we can assume
- * point 1 will always be used? Seems to match
- * the behaviour observed in the wild.
- */
- return min3(icl_max_bw(dev_priv, num_planes, 0),
- icl_max_bw(dev_priv, num_planes, 1),
- icl_max_bw(dev_priv, num_planes, 2));
- else
- return UINT_MAX;
-}
-
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{
/*
@@ -377,7 +385,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
- int i;
+ int i, ret;
+ struct intel_qgv_info qi = {};
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -421,16 +432,67 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
data_rate = intel_bw_data_rate(dev_priv, bw_state);
num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
-
data_rate = DIV_ROUND_UP(data_rate, 1000);
- if (data_rate > max_data_rate) {
- DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
- data_rate, max_data_rate, num_active_planes);
+ ret = icl_get_qgv_points(dev_priv, &qi);
+ if (ret < 0)
+ return 0;
+
+ for (i = 0; i < qi.num_points; i++) {
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ allowed_points |= 1 << i;
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
+
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (allowed_points == 0) {
+ DRM_DEBUG_KMS("Could not find any suitable QGV points\n");
return -EINVAL;
}
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV according to BSpec.
+ */
+ if (!intel_can_enable_sagv(state))
+ allowed_points = 1 << max_bw_point;
+
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ state->qgv_points_mask = (~allowed_points) & ((1 << qi.num_points) - 1);
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(state);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 9db10af012f4..66bf9bc10b73 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8d1881de0bab..cb1af52f3816 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14619,6 +14619,48 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
intel_atomic_helper_free_state(i915);
}
+static void intel_qgv_points_mask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ u32 new_mask = dev_priv->qgv_points_mask | state->qgv_points_mask;
+
+ /*
+ * Restrict required qgv points before updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+ ret);
+ else
+ dev_priv->qgv_points_mask = new_mask;
+}
+
+static void intel_qgv_points_unmask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ u32 new_mask = dev_priv->qgv_points_mask & state->qgv_points_mask;
+
+ /*
+ * Allow required qgv points after updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+ ret);
+ else
+ dev_priv->qgv_points_mask = new_mask;
+}
+
static void intel_atomic_commit_tail(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
@@ -14646,6 +14688,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
}
+ if ((INTEL_GEN(dev_priv) >= 11))
+ intel_qgv_points_mask(state);
+
intel_commit_modeset_disables(state);
/* FIXME: Eventually get rid of our crtc->config pointer */
@@ -14664,8 +14709,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11)
+ if (!intel_can_enable_sagv(state))
+ intel_disable_sagv(dev_priv);
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -14747,8 +14793,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->modeset && intel_can_enable_sagv(state))
+ intel_enable_sagv(dev_priv);
+ } else
+ intel_qgv_points_unmask(state);
drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 38cbabc79b2f..9e9710f5e115 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -528,6 +528,9 @@ struct intel_atomic_state {
struct i915_sw_fence commit_ready;
struct llist_node freed;
+
+ /* Gen11+ only */
+ u32 qgv_points_mask;
};
struct intel_plane_state {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 60f1c4cc3eeb..65985a45ed8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1239,11 +1239,13 @@ struct drm_i915_private {
} dram_info;
struct intel_bw_info {
- unsigned int deratedbw[3]; /* for each QGV point */
+ unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each QGV point */
u8 num_qgv_points;
u8 num_planes;
} max_bw[6];
+ u32 qgv_points_mask;
+
struct drm_private_obj bw_obj;
struct intel_runtime_pm runtime_pm;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 53c280c4e741..cc7fbf243f72 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8947,6 +8947,9 @@ enum {
#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
#define GEN6_PCODE_READY (1 << 31)
#define GEN6_PCODE_ERROR_MASK 0xFF
@@ -8957,6 +8960,8 @@ enum {
#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
#define GEN7_PCODE_TIMEOUT 0x2
#define GEN7_PCODE_ILLEGAL_DATA 0x3
+#define GEN11_PCODE_MAIL_BOX_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -8978,6 +8983,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
@@ -8990,6 +8996,8 @@ enum {
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index e06b35b844a0..ff9dbed094d8 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,29 @@ static inline int gen7_check_mailbox_status(u32 mbox)
}
}
+static inline int gen11_check_mailbox_status(u32 mbox)
+{
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
+ case GEN6_PCODE_SUCCESS:
+ return 0;
+ case GEN6_PCODE_ILLEGAL_CMD:
+ return -ENXIO;
+ case GEN7_PCODE_TIMEOUT:
+ return -ETIMEDOUT;
+ case GEN7_PCODE_ILLEGAL_DATA:
+ return -EINVAL;
+ case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
+ return -EOVERFLOW;
+ case GEN11_PCODE_MAIL_BOX_LOCKED:
+ return -EAGAIN;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
+ default:
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
+ return 0;
+ }
+}
+
static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
u32 mbox, u32 *val, u32 *val1,
int fast_timeout_us,
@@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
if (is_read && val1)
*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
- if (INTEL_GEN(i915) > 6)
+ if (INTEL_GEN(i915) >= 11)
+ return gen11_check_mailbox_status(mbox);
+ else if (INTEL_GEN(i915) > 6)
return gen7_check_mailbox_status(mbox);
else
return gen6_check_mailbox_status(mbox);
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v10 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-01 12:35 ` Stanislav Lisovskiy
0 siblings, 0 replies; 12+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-01 12:35 UTC (permalink / raw)
To: intel-gfx
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 108 ++++++++++++++----
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 57 ++++++++-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 8 ++
drivers/gpu/drm/i915/intel_sideband.c | 27 ++++-
8 files changed, 183 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 49d5cb1b9e0a..3ab99704e5b8 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -7,6 +7,7 @@
#define __INTEL_ATOMIC_H__
#include <linux/types.h>
+#include "intel_display_types.h"
struct drm_atomic_state;
struct drm_connector;
@@ -39,6 +40,8 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
+int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
+
struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 22e83f857de8..c01b2e8f4f88 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,14 +8,17 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
};
+
struct intel_qgv_info {
- struct intel_qgv_point points[3];
+ struct intel_qgv_point points[NUM_SAGV_POINTS];
u8 num_points;
u8 num_channels;
u8 t_bl;
@@ -113,6 +116,27 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ GEN11_PCODE_POINTS_RESTRICTED_MASK,
+ GEN11_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -270,22 +294,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
- int num_planes)
-{
- if (INTEL_GEN(dev_priv) >= 11)
- /*
- * FIXME with SAGV disabled maybe we can assume
- * point 1 will always be used? Seems to match
- * the behaviour observed in the wild.
- */
- return min3(icl_max_bw(dev_priv, num_planes, 0),
- icl_max_bw(dev_priv, num_planes, 1),
- icl_max_bw(dev_priv, num_planes, 2));
- else
- return UINT_MAX;
-}
-
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{
/*
@@ -377,7 +385,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
- int i;
+ int i, ret;
+ struct intel_qgv_info qi = {};
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -421,16 +432,67 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
data_rate = intel_bw_data_rate(dev_priv, bw_state);
num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
-
data_rate = DIV_ROUND_UP(data_rate, 1000);
- if (data_rate > max_data_rate) {
- DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
- data_rate, max_data_rate, num_active_planes);
+ ret = icl_get_qgv_points(dev_priv, &qi);
+ if (ret < 0)
+ return 0;
+
+ for (i = 0; i < qi.num_points; i++) {
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ allowed_points |= 1 << i;
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
+
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (allowed_points == 0) {
+ DRM_DEBUG_KMS("Could not find any suitable QGV points\n");
return -EINVAL;
}
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV according to BSpec.
+ */
+ if (!intel_can_enable_sagv(state))
+ allowed_points = 1 << max_bw_point;
+
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ state->qgv_points_mask = (~allowed_points) & ((1 << qi.num_points) - 1);
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(state);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 9db10af012f4..66bf9bc10b73 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8d1881de0bab..cb1af52f3816 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14619,6 +14619,48 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
intel_atomic_helper_free_state(i915);
}
+static void intel_qgv_points_mask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ u32 new_mask = dev_priv->qgv_points_mask | state->qgv_points_mask;
+
+ /*
+ * Restrict required qgv points before updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+ ret);
+ else
+ dev_priv->qgv_points_mask = new_mask;
+}
+
+static void intel_qgv_points_unmask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ u32 new_mask = dev_priv->qgv_points_mask & state->qgv_points_mask;
+
+ /*
+ * Allow required qgv points after updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+ ret);
+ else
+ dev_priv->qgv_points_mask = new_mask;
+}
+
static void intel_atomic_commit_tail(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
@@ -14646,6 +14688,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
}
+ if ((INTEL_GEN(dev_priv) >= 11))
+ intel_qgv_points_mask(state);
+
intel_commit_modeset_disables(state);
/* FIXME: Eventually get rid of our crtc->config pointer */
@@ -14664,8 +14709,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11)
+ if (!intel_can_enable_sagv(state))
+ intel_disable_sagv(dev_priv);
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -14747,8 +14793,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->modeset && intel_can_enable_sagv(state))
+ intel_enable_sagv(dev_priv);
+ } else
+ intel_qgv_points_unmask(state);
drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 38cbabc79b2f..9e9710f5e115 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -528,6 +528,9 @@ struct intel_atomic_state {
struct i915_sw_fence commit_ready;
struct llist_node freed;
+
+ /* Gen11+ only */
+ u32 qgv_points_mask;
};
struct intel_plane_state {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 60f1c4cc3eeb..65985a45ed8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1239,11 +1239,13 @@ struct drm_i915_private {
} dram_info;
struct intel_bw_info {
- unsigned int deratedbw[3]; /* for each QGV point */
+ unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each QGV point */
u8 num_qgv_points;
u8 num_planes;
} max_bw[6];
+ u32 qgv_points_mask;
+
struct drm_private_obj bw_obj;
struct intel_runtime_pm runtime_pm;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 53c280c4e741..cc7fbf243f72 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8947,6 +8947,9 @@ enum {
#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
#define GEN6_PCODE_READY (1 << 31)
#define GEN6_PCODE_ERROR_MASK 0xFF
@@ -8957,6 +8960,8 @@ enum {
#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
#define GEN7_PCODE_TIMEOUT 0x2
#define GEN7_PCODE_ILLEGAL_DATA 0x3
+#define GEN11_PCODE_MAIL_BOX_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -8978,6 +8983,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
@@ -8990,6 +8996,8 @@ enum {
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index e06b35b844a0..ff9dbed094d8 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,29 @@ static inline int gen7_check_mailbox_status(u32 mbox)
}
}
+static inline int gen11_check_mailbox_status(u32 mbox)
+{
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
+ case GEN6_PCODE_SUCCESS:
+ return 0;
+ case GEN6_PCODE_ILLEGAL_CMD:
+ return -ENXIO;
+ case GEN7_PCODE_TIMEOUT:
+ return -ETIMEDOUT;
+ case GEN7_PCODE_ILLEGAL_DATA:
+ return -EINVAL;
+ case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
+ return -EOVERFLOW;
+ case GEN11_PCODE_MAIL_BOX_LOCKED:
+ return -EAGAIN;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
+ default:
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
+ return 0;
+ }
+}
+
static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
u32 mbox, u32 *val, u32 *val1,
int fast_timeout_us,
@@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
if (is_read && val1)
*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
- if (INTEL_GEN(i915) > 6)
+ if (INTEL_GEN(i915) >= 11)
+ return gen11_check_mailbox_status(mbox);
+ else if (INTEL_GEN(i915) > 6)
return gen7_check_mailbox_status(mbox);
else
return gen6_check_mailbox_status(mbox);
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev7)
@ 2019-11-01 14:10 ` Patchwork
0 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-11-01 14:10 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev7)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3f4410bb65da drm/i915: Refactor intel_can_enable_sagv
-:189: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#189: FILE: drivers/gpu/drm/i915/intel_pm.c:3836:
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
-:269: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#269: FILE: drivers/gpu/drm/i915/intel_pm.c:3916:
+ bool state_sagv_masked = \
-:274: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#274: FILE: drivers/gpu/drm/i915/intel_pm.c:3921:
+ bool sagv_masked = \
-:318: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#318: FILE: drivers/gpu/drm/i915/intel_pm.c:4342:
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+ struct skl_ddb_allocation *ddb /* out */)
-:436: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#436: FILE: drivers/gpu/drm/i915/intel_pm.c:4991:
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
-:438: CHECK:BRACES: Unbalanced braces around else statement
#438: FILE: drivers/gpu/drm/i915/intel_pm.c:4993:
+ } else
-:440: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#440: FILE: drivers/gpu/drm/i915/intel_pm.c:4995:
+ memcpy(&plane_wm->sagv_wm0, &levels[0],
+ sizeof(struct skl_wm_level));
-:503: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#503: FILE: drivers/gpu/drm/i915/intel_pm.c:5681:
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
-:509: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#509: FILE: drivers/gpu/drm/i915/intel_pm.c:5687:
+ struct skl_plane_wm *plane_wm = \
-:532: WARNING:LINE_SPACING: Missing a blank line after declarations
#532: FILE: drivers/gpu/drm/i915/intel_pm.c:5710:
+ int pipe_bit = BIT(crtc->pipe);
+ state->crtc_sagv_mask |= pipe_bit;
total: 0 errors, 4 warnings, 6 checks, 468 lines checked
93776c9f8bb6 drm/i915: Restrict qgv points which don't have enough bandwidth.
-:87: CHECK:LINE_SPACING: Please don't use multiple blank lines
#87: FILE: drivers/gpu/drm/i915/display/intel_bw.c:19:
+
-:118: CHECK:LINE_SPACING: Please don't use multiple blank lines
#118: FILE: drivers/gpu/drm/i915/display/intel_bw.c:139:
+
+
-:323: CHECK:BRACES: braces {} should be used on all arms of this statement
#323: FILE: drivers/gpu/drm/i915/display/intel_display.c:14796:
+ if (INTEL_GEN(dev_priv) < 11) {
[...]
+ } else
[...]
-:326: CHECK:BRACES: Unbalanced braces around else statement
#326: FILE: drivers/gpu/drm/i915/display/intel_display.c:14799:
+ } else
total: 0 errors, 0 warnings, 4 checks, 347 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev7)
@ 2019-11-01 14:10 ` Patchwork
0 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-11-01 14:10 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev7)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3f4410bb65da drm/i915: Refactor intel_can_enable_sagv
-:189: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#189: FILE: drivers/gpu/drm/i915/intel_pm.c:3836:
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
-:269: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#269: FILE: drivers/gpu/drm/i915/intel_pm.c:3916:
+ bool state_sagv_masked = \
-:274: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#274: FILE: drivers/gpu/drm/i915/intel_pm.c:3921:
+ bool sagv_masked = \
-:318: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#318: FILE: drivers/gpu/drm/i915/intel_pm.c:4342:
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+ struct skl_ddb_allocation *ddb /* out */)
-:436: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#436: FILE: drivers/gpu/drm/i915/intel_pm.c:4991:
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
-:438: CHECK:BRACES: Unbalanced braces around else statement
#438: FILE: drivers/gpu/drm/i915/intel_pm.c:4993:
+ } else
-:440: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#440: FILE: drivers/gpu/drm/i915/intel_pm.c:4995:
+ memcpy(&plane_wm->sagv_wm0, &levels[0],
+ sizeof(struct skl_wm_level));
-:503: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#503: FILE: drivers/gpu/drm/i915/intel_pm.c:5681:
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
-:509: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#509: FILE: drivers/gpu/drm/i915/intel_pm.c:5687:
+ struct skl_plane_wm *plane_wm = \
-:532: WARNING:LINE_SPACING: Missing a blank line after declarations
#532: FILE: drivers/gpu/drm/i915/intel_pm.c:5710:
+ int pipe_bit = BIT(crtc->pipe);
+ state->crtc_sagv_mask |= pipe_bit;
total: 0 errors, 4 warnings, 6 checks, 468 lines checked
93776c9f8bb6 drm/i915: Restrict qgv points which don't have enough bandwidth.
-:87: CHECK:LINE_SPACING: Please don't use multiple blank lines
#87: FILE: drivers/gpu/drm/i915/display/intel_bw.c:19:
+
-:118: CHECK:LINE_SPACING: Please don't use multiple blank lines
#118: FILE: drivers/gpu/drm/i915/display/intel_bw.c:139:
+
+
-:323: CHECK:BRACES: braces {} should be used on all arms of this statement
#323: FILE: drivers/gpu/drm/i915/display/intel_display.c:14796:
+ if (INTEL_GEN(dev_priv) < 11) {
[...]
+ } else
[...]
-:326: CHECK:BRACES: Unbalanced braces around else statement
#326: FILE: drivers/gpu/drm/i915/display/intel_display.c:14799:
+ } else
total: 0 errors, 0 warnings, 4 checks, 347 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support (rev7)
@ 2019-11-01 14:12 ` Patchwork
0 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-11-01 14:12 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev7)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Refactor intel_can_enable_sagv
+drivers/gpu/drm/i915/intel_pm.c:5665:6: warning: symbol 'tgl_set_sagv_wm0' was not declared. Should it be static?
Commit: drm/i915: Restrict qgv points which don't have enough bandwidth.
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support (rev7)
@ 2019-11-01 14:12 ` Patchwork
0 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-11-01 14:12 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev7)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Refactor intel_can_enable_sagv
+drivers/gpu/drm/i915/intel_pm.c:5665:6: warning: symbol 'tgl_set_sagv_wm0' was not declared. Should it be static?
Commit: drm/i915: Restrict qgv points which don't have enough bandwidth.
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev7)
@ 2019-11-01 14:40 ` Patchwork
0 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-11-01 14:40 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev7)
URL : https://patchwork.freedesktop.org/series/68028/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7240 -> Patchwork_15104
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15104 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15104, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15104:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-icl-u3/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-icl-u3/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_fence@basic-wait-default:
- {fi-tgl-u}: [PASS][5] -> [DMESG-WARN][6] +61 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-tgl-u/igt@gem_exec_fence@basic-wait-default.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-tgl-u/igt@gem_exec_fence@basic-wait-default.html
* igt@gem_ringfill@basic-default-forked:
- {fi-tgl-y}: [PASS][7] -> [DMESG-WARN][8] +204 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-tgl-y/igt@gem_ringfill@basic-default-forked.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-tgl-y/igt@gem_ringfill@basic-default-forked.html
* igt@gem_sync@basic-all:
- {fi-tgl-u}: [INCOMPLETE][9] ([fdo#111880]) -> [DMESG-WARN][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-tgl-u/igt@gem_sync@basic-all.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-tgl-u/igt@gem_sync@basic-all.html
* igt@kms_addfb_basic@addfb25-y-tiled-small:
- {fi-tgl-y}: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-tgl-y/igt@kms_addfb_basic@addfb25-y-tiled-small.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-tgl-y/igt@kms_addfb_basic@addfb25-y-tiled-small.html
* igt@kms_addfb_basic@bo-too-small:
- {fi-tgl-u}: NOTRUN -> [DMESG-WARN][13] +151 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-tgl-u/igt@kms_addfb_basic@bo-too-small.html
* igt@kms_flip@basic-flip-vs-dpms:
- {fi-icl-guc}: [PASS][14] -> [DMESG-WARN][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-icl-guc/igt@kms_flip@basic-flip-vs-dpms.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-icl-guc/igt@kms_flip@basic-flip-vs-dpms.html
Known issues
------------
Here are the changes found in Patchwork_15104 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [PASS][16] -> [DMESG-WARN][17] ([fdo#107724])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-read:
- fi-icl-u3: [DMESG-WARN][18] ([fdo#107724]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-icl-u3/igt@gem_mmap_gtt@basic-read.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-icl-u3/igt@gem_mmap_gtt@basic-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112120]: https://bugs.freedesktop.org/show_bug.cgi?id=112120
Participating hosts (53 -> 45)
------------------------------
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7240 -> Patchwork_15104
CI-20190529: 20190529
CI_DRM_7240: 5049f287f8c59edd42b65000331ed352ebc57e7f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5258: c8a88b614ac057b01809a17b9e87a197195b44ad @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15104: 93776c9f8bb655966ba4a9a93c1f01863870135e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
93776c9f8bb6 drm/i915: Restrict qgv points which don't have enough bandwidth.
3f4410bb65da drm/i915: Refactor intel_can_enable_sagv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev7)
@ 2019-11-01 14:40 ` Patchwork
0 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-11-01 14:40 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev7)
URL : https://patchwork.freedesktop.org/series/68028/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7240 -> Patchwork_15104
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15104 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15104, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15104:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-icl-u3/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-icl-u3/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_fence@basic-wait-default:
- {fi-tgl-u}: [PASS][5] -> [DMESG-WARN][6] +61 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-tgl-u/igt@gem_exec_fence@basic-wait-default.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-tgl-u/igt@gem_exec_fence@basic-wait-default.html
* igt@gem_ringfill@basic-default-forked:
- {fi-tgl-y}: [PASS][7] -> [DMESG-WARN][8] +204 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-tgl-y/igt@gem_ringfill@basic-default-forked.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-tgl-y/igt@gem_ringfill@basic-default-forked.html
* igt@gem_sync@basic-all:
- {fi-tgl-u}: [INCOMPLETE][9] ([fdo#111880]) -> [DMESG-WARN][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-tgl-u/igt@gem_sync@basic-all.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-tgl-u/igt@gem_sync@basic-all.html
* igt@kms_addfb_basic@addfb25-y-tiled-small:
- {fi-tgl-y}: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-tgl-y/igt@kms_addfb_basic@addfb25-y-tiled-small.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-tgl-y/igt@kms_addfb_basic@addfb25-y-tiled-small.html
* igt@kms_addfb_basic@bo-too-small:
- {fi-tgl-u}: NOTRUN -> [DMESG-WARN][13] +151 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-tgl-u/igt@kms_addfb_basic@bo-too-small.html
* igt@kms_flip@basic-flip-vs-dpms:
- {fi-icl-guc}: [PASS][14] -> [DMESG-WARN][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-icl-guc/igt@kms_flip@basic-flip-vs-dpms.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-icl-guc/igt@kms_flip@basic-flip-vs-dpms.html
Known issues
------------
Here are the changes found in Patchwork_15104 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [PASS][16] -> [DMESG-WARN][17] ([fdo#107724])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-read:
- fi-icl-u3: [DMESG-WARN][18] ([fdo#107724]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7240/fi-icl-u3/igt@gem_mmap_gtt@basic-read.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/fi-icl-u3/igt@gem_mmap_gtt@basic-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112120]: https://bugs.freedesktop.org/show_bug.cgi?id=112120
Participating hosts (53 -> 45)
------------------------------
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7240 -> Patchwork_15104
CI-20190529: 20190529
CI_DRM_7240: 5049f287f8c59edd42b65000331ed352ebc57e7f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5258: c8a88b614ac057b01809a17b9e87a197195b44ad @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15104: 93776c9f8bb655966ba4a9a93c1f01863870135e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
93776c9f8bb6 drm/i915: Restrict qgv points which don't have enough bandwidth.
3f4410bb65da drm/i915: Refactor intel_can_enable_sagv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15104/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-11-01 14:40 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-01 12:35 [PATCH v10 0/2] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2019-11-01 12:35 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-01 12:35 ` [PATCH v10 1/2] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
2019-11-01 12:35 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-01 12:35 ` [PATCH v10 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2019-11-01 12:35 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-01 14:10 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev7) Patchwork
2019-11-01 14:10 ` [Intel-gfx] " Patchwork
2019-11-01 14:12 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-11-01 14:12 ` [Intel-gfx] " Patchwork
2019-11-01 14:40 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-11-01 14:40 ` [Intel-gfx] " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.