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Sat, 2 Nov 2019 11:23:39 +0000 From: To: , CC: , , , , Subject: [PATCH v4 09/20] mtd: spi-nor: Drop spansion_quad_enable() Thread-Topic: [PATCH v4 09/20] mtd: spi-nor: Drop spansion_quad_enable() Thread-Index: AQHVkW/5Ftew1U8fT02D5+RP5z+bOw== Date: Sat, 2 Nov 2019 11:23:39 +0000 Message-ID: <20191102112316.20715-10-tudor.ambarus@microchip.com> References: <20191102112316.20715-1-tudor.ambarus@microchip.com> In-Reply-To: <20191102112316.20715-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR07CA0143.eurprd07.prod.outlook.com (2603:10a6:802:16::30) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [86.120.239.29] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0ec7a733-5f32-45ef-31b3-08d75f871bfc x-ms-traffictypediagnostic: MN2PR11MB3711: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 0ec7a733-5f32-45ef-31b3-08d75f871bfc X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Nov 2019 11:23:39.3799 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: YGKdYB3iSRrXcqg3x0VfwuS5tXeXnL+qi1GdbJp+E7E2AH6Gk1yDOOI8R3YwDvY7WRQqPKWwYNM8lVNgF+EVyBhqJZdlYUZuPJuguKEDirA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3711 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Drop the default spansion_quad_enable() method and replace it with spansion_read_cr_quad_enable(). The function was buggy, it didn't care about the previous values of the Status and Configuration Registers. spansion_read_cr_quad_enable() is a Read-Modify-Write-Check function that keeps track of what were the previous values of the Status and Configuration Registers. In terms of instruction types sent to the flash, the only difference between the spansion_quad_enable() and spansion_read_cr_quad_enable() is that the later calls spi_nor_read_sr(). We can safely assume that all flashes support spi_nor_read_sr(), because all flashes call it in spi_nor_sr_ready(). The transition from spansion_quad_enable() to spansion_read_cr_quad_enable() will not affect anybody, drop the buggy code. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 58 ++++-----------------------------------= ---- 1 file changed, 5 insertions(+), 53 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 99a9a6aba41d..f5193733a0f6 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1971,54 +1971,6 @@ static int macronix_quad_enable(struct spi_nor *nor) } =20 /** - * spansion_quad_enable() - set QE bit in Configuraiton Register. - * @nor: pointer to a 'struct spi_nor' - * - * Set the Quad Enable (QE) bit in the Configuration Register. - * This function is kept for legacy purpose because it has been used for a - * long time without anybody complaining but it should be considered as - * deprecated and maybe buggy. - * First, this function doesn't care about the previous values of the Stat= us - * and Configuration Registers when it sets the QE bit (bit 1) in the - * Configuration Register: all other bits are cleared, which may have unwa= nted - * side effects like removing some block protections. - * Secondly, it uses the Read Configuration Register (35h) instruction tho= ugh - * some very old and few memories don't support this instruction. If a pul= l-up - * resistor is present on the MISO/IO1 line, we might still be able to pas= s the - * "read back" test because the QSPI memory doesn't recognize the command, - * so leaves the MISO/IO1 line state unchanged, hence spi_nor_read_cr() re= turns - * 0xFF. - * - * bit 1 of the Configuration Register is the QE bit for Spansion like QSP= I - * memories. - * - * Return: 0 on success, -errno otherwise. - */ -static int spansion_quad_enable(struct spi_nor *nor) -{ - u8 *sr_cr =3D nor->bouncebuf; - int ret; - - sr_cr[0] =3D 0; - sr_cr[1] =3D CR_QUAD_EN_SPAN; - ret =3D spi_nor_write_sr(nor, sr_cr, 2); - if (ret) - return ret; - - /* read back and check it */ - ret =3D spi_nor_read_cr(nor, nor->bouncebuf); - if (ret) - return ret; - - if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) { - dev_dbg(nor->dev, "Spansion Quad bit not set\n"); - return -EINVAL; - } - - return 0; -} - -/** * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Registe= r. * @nor: pointer to a 'struct spi_nor' * @@ -2170,9 +2122,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) * * Read-modify-write function that clears the Block Protection bits from t= he * Status Register without affecting other bits. The function is tightly - * coupled with the spansion_quad_enable() function. Both assume that the = Write - * Register with 16 bits, together with the Read Configuration Register (3= 5h) - * instructions are supported. + * coupled with the spansion_read_cr_quad_enable() function. Both assume t= hat + * the Write Register with 16 bits, together with the Read Configuration + * Register (35h) instructions are supported. * * Return: 0 on success, -errno otherwise. */ @@ -4654,7 +4606,7 @@ static void spi_nor_info_init_params(struct spi_nor *= nor) u8 i, erase_mask; =20 /* Initialize legacy flash parameters and settings. */ - params->quad_enable =3D spansion_quad_enable; + params->quad_enable =3D spansion_read_cr_quad_enable; params->set_4byte =3D spansion_set_4byte; params->setup =3D spi_nor_default_setup; =20 @@ -4869,7 +4821,7 @@ static int spi_nor_init(struct spi_nor *nor) int err; =20 if (nor->clear_sr_bp) { - if (nor->params.quad_enable =3D=3D spansion_quad_enable) + if (nor->params.quad_enable =3D=3D spansion_read_cr_quad_enable) nor->clear_sr_bp =3D spi_nor_spansion_clear_sr_bp; =20 err =3D nor->clear_sr_bp(nor); --=20 2.9.5 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E63DDCA9EC7 for ; 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Sat, 2 Nov 2019 11:23:39 +0000 From: To: , Subject: [PATCH v4 09/20] mtd: spi-nor: Drop spansion_quad_enable() Thread-Topic: [PATCH v4 09/20] mtd: spi-nor: Drop spansion_quad_enable() Thread-Index: AQHVkW/5Ftew1U8fT02D5+RP5z+bOw== Date: Sat, 2 Nov 2019 11:23:39 +0000 Message-ID: <20191102112316.20715-10-tudor.ambarus@microchip.com> References: <20191102112316.20715-1-tudor.ambarus@microchip.com> In-Reply-To: <20191102112316.20715-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR07CA0143.eurprd07.prod.outlook.com (2603:10a6:802:16::30) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [86.120.239.29] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0ec7a733-5f32-45ef-31b3-08d75f871bfc x-ms-traffictypediagnostic: MN2PR11MB3711: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org From: Tudor Ambarus Drop the default spansion_quad_enable() method and replace it with spansion_read_cr_quad_enable(). The function was buggy, it didn't care about the previous values of the Status and Configuration Registers. spansion_read_cr_quad_enable() is a Read-Modify-Write-Check function that keeps track of what were the previous values of the Status and Configuration Registers. In terms of instruction types sent to the flash, the only difference between the spansion_quad_enable() and spansion_read_cr_quad_enable() is that the later calls spi_nor_read_sr(). We can safely assume that all flashes support spi_nor_read_sr(), because all flashes call it in spi_nor_sr_ready(). The transition from spansion_quad_enable() to spansion_read_cr_quad_enable() will not affect anybody, drop the buggy code. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 58 ++++--------------------------------------- 1 file changed, 5 insertions(+), 53 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 99a9a6aba41d..f5193733a0f6 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1971,54 +1971,6 @@ static int macronix_quad_enable(struct spi_nor *nor) } /** - * spansion_quad_enable() - set QE bit in Configuraiton Register. - * @nor: pointer to a 'struct spi_nor' - * - * Set the Quad Enable (QE) bit in the Configuration Register. - * This function is kept for legacy purpose because it has been used for a - * long time without anybody complaining but it should be considered as - * deprecated and maybe buggy. - * First, this function doesn't care about the previous values of the Status - * and Configuration Registers when it sets the QE bit (bit 1) in the - * Configuration Register: all other bits are cleared, which may have unwanted - * side effects like removing some block protections. - * Secondly, it uses the Read Configuration Register (35h) instruction though - * some very old and few memories don't support this instruction. If a pull-up - * resistor is present on the MISO/IO1 line, we might still be able to pass the - * "read back" test because the QSPI memory doesn't recognize the command, - * so leaves the MISO/IO1 line state unchanged, hence spi_nor_read_cr() returns - * 0xFF. - * - * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI - * memories. - * - * Return: 0 on success, -errno otherwise. - */ -static int spansion_quad_enable(struct spi_nor *nor) -{ - u8 *sr_cr = nor->bouncebuf; - int ret; - - sr_cr[0] = 0; - sr_cr[1] = CR_QUAD_EN_SPAN; - ret = spi_nor_write_sr(nor, sr_cr, 2); - if (ret) - return ret; - - /* read back and check it */ - ret = spi_nor_read_cr(nor, nor->bouncebuf); - if (ret) - return ret; - - if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) { - dev_dbg(nor->dev, "Spansion Quad bit not set\n"); - return -EINVAL; - } - - return 0; -} - -/** * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register. * @nor: pointer to a 'struct spi_nor' * @@ -2170,9 +2122,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) * * Read-modify-write function that clears the Block Protection bits from the * Status Register without affecting other bits. The function is tightly - * coupled with the spansion_quad_enable() function. Both assume that the Write - * Register with 16 bits, together with the Read Configuration Register (35h) - * instructions are supported. + * coupled with the spansion_read_cr_quad_enable() function. Both assume that + * the Write Register with 16 bits, together with the Read Configuration + * Register (35h) instructions are supported. * * Return: 0 on success, -errno otherwise. */ @@ -4654,7 +4606,7 @@ static void spi_nor_info_init_params(struct spi_nor *nor) u8 i, erase_mask; /* Initialize legacy flash parameters and settings. */ - params->quad_enable = spansion_quad_enable; + params->quad_enable = spansion_read_cr_quad_enable; params->set_4byte = spansion_set_4byte; params->setup = spi_nor_default_setup; @@ -4869,7 +4821,7 @@ static int spi_nor_init(struct spi_nor *nor) int err; if (nor->clear_sr_bp) { - if (nor->params.quad_enable == spansion_quad_enable) + if (nor->params.quad_enable == spansion_read_cr_quad_enable) nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp; err = nor->clear_sr_bp(nor); -- 2.9.5 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/