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Sat, 2 Nov 2019 11:23:28 +0000 From: To: , CC: , , , , Subject: [PATCH v4 03/20] mtd: spi-nor: Check for errors after each Register Operation Thread-Topic: [PATCH v4 03/20] mtd: spi-nor: Check for errors after each Register Operation Thread-Index: AQHVkW/zzztfMFx5dk6cR4KWQTA7vg== Date: Sat, 2 Nov 2019 11:23:28 +0000 Message-ID: <20191102112316.20715-4-tudor.ambarus@microchip.com> References: <20191102112316.20715-1-tudor.ambarus@microchip.com> In-Reply-To: <20191102112316.20715-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR07CA0143.eurprd07.prod.outlook.com (2603:10a6:802:16::30) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [86.120.239.29] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 019422f8-7a8b-4f8a-806b-08d75f8715c1 x-ms-traffictypediagnostic: MN2PR11MB3711: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3383; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 019422f8-7a8b-4f8a-806b-08d75f8715c1 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Nov 2019 11:23:28.8789 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: AumR4FLEbdKDNY/HOW6kJPFaaIZB5NY9CtTRHgp0NfnViSRy5feAzGC/52VQgXkYTpMQnA5VGQH9fVRqyOspV1Xsf1VtHAYGN1aEKIJ9cLA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3711 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Check for the return vales of each Register Operation. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 81 ++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 60 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 0cb3122e74ad..5debb0f7ca13 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -595,11 +595,15 @@ static int st_micron_set_4byte(struct spi_nor *nor, b= ool enable) { int ret; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + ret =3D macronix_set_4byte(nor, enable); - spi_nor_write_disable(nor); + if (ret) + return ret; =20 - return ret; + return spi_nor_write_disable(nor); } =20 static int spansion_set_4byte(struct spi_nor *nor, bool enable) @@ -665,11 +669,15 @@ static int winbond_set_4byte(struct spi_nor *nor, boo= l enable) * Register to be set to 1, so all 3-byte-address reads come from the * second 16M. We must clear the register to enable normal behavior. */ - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + ret =3D spi_nor_write_ear(nor, 0); - spi_nor_write_disable(nor); + if (ret) + return ret; =20 - return ret; + return spi_nor_write_disable(nor); } =20 static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) @@ -859,7 +867,9 @@ static int spi_nor_write_sr_cr(struct spi_nor *nor, con= st u8 *sr_cr) { int ret; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 if (nor->spimem) { struct spi_mem_op op =3D @@ -889,7 +899,10 @@ static int spi_nor_write_sr_and_check(struct spi_nor *= nor, u8 status_new, { int ret; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + ret =3D spi_nor_write_sr(nor, status_new); if (ret) return ret; @@ -1397,7 +1410,9 @@ static int spi_nor_erase_multi_sectors(struct spi_nor= *nor, u64 addr, u32 len) list_for_each_entry_safe(cmd, next, &erase_list, list) { nor->erase_opcode =3D cmd->opcode; while (cmd->count) { - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto destroy_erase_cmd_list; =20 ret =3D spi_nor_erase_sector(nor, addr); if (ret) @@ -1452,7 +1467,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) if (len =3D=3D mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { unsigned long timeout; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto erase_err; =20 ret =3D spi_nor_erase_chip(nor); if (ret) @@ -1479,7 +1496,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) /* "sector"-at-a-time erase */ } else if (spi_nor_has_uniform_erase(nor)) { while (len) { - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto erase_err; =20 ret =3D spi_nor_erase_sector(nor, addr); if (ret) @@ -1500,7 +1519,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) goto erase_err; } =20 - spi_nor_write_disable(nor); + ret =3D spi_nor_write_disable(nor); =20 erase_err: spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); @@ -1849,9 +1868,13 @@ static int macronix_quad_enable(struct spi_nor *nor) if (nor->bouncebuf[0] & SR_QUAD_EN_MX) return 0; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 - spi_nor_write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX); + ret =3D spi_nor_write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX); + if (ret) + return ret; =20 ret =3D spi_nor_wait_till_ready(nor); if (ret) @@ -2022,7 +2045,9 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) /* Update the Quad Enable bit. */ *sr2 |=3D SR2_QUAD_EN_BIT7; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 ret =3D spi_nor_write_sr2(nor, sr2); if (ret) @@ -2063,7 +2088,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) if (ret) return ret; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 ret =3D spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask); if (ret) @@ -2680,7 +2707,9 @@ static int sst_write(struct mtd_info *mtd, loff_t to,= size_t len, if (ret) return ret; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto sst_write_err; =20 nor->sst_write_second =3D false; =20 @@ -2718,14 +2747,19 @@ static int sst_write(struct mtd_info *mtd, loff_t t= o, size_t len, } nor->sst_write_second =3D false; =20 - spi_nor_write_disable(nor); + ret =3D spi_nor_write_disable(nor); + if (ret) + goto sst_write_err; + ret =3D spi_nor_wait_till_ready(nor); if (ret) goto sst_write_err; =20 /* Write out trailing byte if it exists. */ if (actual !=3D len) { - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto sst_write_err; =20 nor->program_opcode =3D SPINOR_OP_BP; ret =3D spi_nor_write_data(nor, to, 1, buf + actual); @@ -2735,8 +2769,10 @@ static int sst_write(struct mtd_info *mtd, loff_t to= , size_t len, ret =3D spi_nor_wait_till_ready(nor); if (ret) goto sst_write_err; - spi_nor_write_disable(nor); + actual +=3D 1; + + ret =3D spi_nor_write_disable(nor); } sst_write_err: *retlen +=3D actual; @@ -2787,7 +2823,10 @@ static int spi_nor_write(struct mtd_info *mtd, loff_= t to, size_t len, =20 addr =3D spi_nor_convert_addr(nor, addr); =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto write_err; + ret =3D spi_nor_write_data(nor, addr, page_remain, buf + i); if (ret < 0) goto write_err; --=20 2.9.5 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55299CA9EC7 for ; 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Sat, 2 Nov 2019 11:23:28 +0000 From: To: , Subject: [PATCH v4 03/20] mtd: spi-nor: Check for errors after each Register Operation Thread-Topic: [PATCH v4 03/20] mtd: spi-nor: Check for errors after each Register Operation Thread-Index: AQHVkW/zzztfMFx5dk6cR4KWQTA7vg== Date: Sat, 2 Nov 2019 11:23:28 +0000 Message-ID: <20191102112316.20715-4-tudor.ambarus@microchip.com> References: <20191102112316.20715-1-tudor.ambarus@microchip.com> In-Reply-To: <20191102112316.20715-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR07CA0143.eurprd07.prod.outlook.com (2603:10a6:802:16::30) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [86.120.239.29] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 019422f8-7a8b-4f8a-806b-08d75f8715c1 x-ms-traffictypediagnostic: MN2PR11MB3711: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3383; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org From: Tudor Ambarus Check for the return vales of each Register Operation. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 81 ++++++++++++++++++++++++++++++++----------- 1 file changed, 60 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 0cb3122e74ad..5debb0f7ca13 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -595,11 +595,15 @@ static int st_micron_set_4byte(struct spi_nor *nor, bool enable) { int ret; - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + ret = macronix_set_4byte(nor, enable); - spi_nor_write_disable(nor); + if (ret) + return ret; - return ret; + return spi_nor_write_disable(nor); } static int spansion_set_4byte(struct spi_nor *nor, bool enable) @@ -665,11 +669,15 @@ static int winbond_set_4byte(struct spi_nor *nor, bool enable) * Register to be set to 1, so all 3-byte-address reads come from the * second 16M. We must clear the register to enable normal behavior. */ - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + ret = spi_nor_write_ear(nor, 0); - spi_nor_write_disable(nor); + if (ret) + return ret; - return ret; + return spi_nor_write_disable(nor); } static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) @@ -859,7 +867,9 @@ static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr) { int ret; - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + return ret; if (nor->spimem) { struct spi_mem_op op = @@ -889,7 +899,10 @@ static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 status_new, { int ret; - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + ret = spi_nor_write_sr(nor, status_new); if (ret) return ret; @@ -1397,7 +1410,9 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) list_for_each_entry_safe(cmd, next, &erase_list, list) { nor->erase_opcode = cmd->opcode; while (cmd->count) { - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + goto destroy_erase_cmd_list; ret = spi_nor_erase_sector(nor, addr); if (ret) @@ -1452,7 +1467,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { unsigned long timeout; - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + goto erase_err; ret = spi_nor_erase_chip(nor); if (ret) @@ -1479,7 +1496,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) /* "sector"-at-a-time erase */ } else if (spi_nor_has_uniform_erase(nor)) { while (len) { - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + goto erase_err; ret = spi_nor_erase_sector(nor, addr); if (ret) @@ -1500,7 +1519,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) goto erase_err; } - spi_nor_write_disable(nor); + ret = spi_nor_write_disable(nor); erase_err: spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); @@ -1849,9 +1868,13 @@ static int macronix_quad_enable(struct spi_nor *nor) if (nor->bouncebuf[0] & SR_QUAD_EN_MX) return 0; - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + return ret; - spi_nor_write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX); + ret = spi_nor_write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX); + if (ret) + return ret; ret = spi_nor_wait_till_ready(nor); if (ret) @@ -2022,7 +2045,9 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) /* Update the Quad Enable bit. */ *sr2 |= SR2_QUAD_EN_BIT7; - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + return ret; ret = spi_nor_write_sr2(nor, sr2); if (ret) @@ -2063,7 +2088,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) if (ret) return ret; - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + return ret; ret = spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask); if (ret) @@ -2680,7 +2707,9 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, if (ret) return ret; - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + goto sst_write_err; nor->sst_write_second = false; @@ -2718,14 +2747,19 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, } nor->sst_write_second = false; - spi_nor_write_disable(nor); + ret = spi_nor_write_disable(nor); + if (ret) + goto sst_write_err; + ret = spi_nor_wait_till_ready(nor); if (ret) goto sst_write_err; /* Write out trailing byte if it exists. */ if (actual != len) { - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + goto sst_write_err; nor->program_opcode = SPINOR_OP_BP; ret = spi_nor_write_data(nor, to, 1, buf + actual); @@ -2735,8 +2769,10 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, ret = spi_nor_wait_till_ready(nor); if (ret) goto sst_write_err; - spi_nor_write_disable(nor); + actual += 1; + + ret = spi_nor_write_disable(nor); } sst_write_err: *retlen += actual; @@ -2787,7 +2823,10 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, addr = spi_nor_convert_addr(nor, addr); - spi_nor_write_enable(nor); + ret = spi_nor_write_enable(nor); + if (ret) + goto write_err; + ret = spi_nor_write_data(nor, addr, page_remain, buf + i); if (ret < 0) goto write_err; -- 2.9.5 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/