From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D621CA9ED2 for ; Mon, 4 Nov 2019 08:24:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1E05B222C6 for ; Mon, 4 Nov 2019 08:24:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727938AbfKDIYU (ORCPT ); Mon, 4 Nov 2019 03:24:20 -0500 Received: from metis.ext.pengutronix.de ([85.220.165.71]:46841 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726441AbfKDIYT (ORCPT ); Mon, 4 Nov 2019 03:24:19 -0500 Received: from pty.hi.pengutronix.de ([2001:67c:670:100:1d::c5]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1iRXel-0000b5-8H; Mon, 04 Nov 2019 09:24:11 +0100 Received: from ukl by pty.hi.pengutronix.de with local (Exim 4.89) (envelope-from ) id 1iRXek-00081I-88; Mon, 04 Nov 2019 09:24:10 +0100 Date: Mon, 4 Nov 2019 09:24:10 +0100 From: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= To: =?iso-8859-1?Q?Cl=E9ment_P=E9ron?= Cc: Thierry Reding , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , kernel@pengutronix.de Subject: Re: [PATCH v2 3/7] pwm: sun4i: Add an optional probe for bus clock Message-ID: <20191104082410.qdgcnphkamlzaipf@pengutronix.de> References: <20191103203334.10539-1-peron.clem@gmail.com> <20191103203334.10539-4-peron.clem@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20191103203334.10539-4-peron.clem@gmail.com> User-Agent: NeoMutt/20170113 (1.7.2) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c5 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, On Sun, Nov 03, 2019 at 09:33:30PM +0100, Clément Péron wrote: > From: Jernej Skrabec > > H6 PWM core needs bus clock to be enabled in order to work. > > Add an optional probe for it and a fallback for previous > bindings without name on module clock. > > Signed-off-by: Jernej Skrabec > Signed-off-by: Clément Péron > --- > drivers/pwm/pwm-sun4i.c | 36 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index d194b8ebdb00..b5e7ac364f59 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c > @@ -78,6 +78,7 @@ struct sun4i_pwm_data { > > struct sun4i_pwm_chip { > struct pwm_chip chip; > + struct clk *bus_clk; > struct clk *clk; > struct reset_control *rst; > void __iomem *base; > @@ -367,6 +368,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev) Adding more context here: | pwm->clk = devm_clk_get(&pdev->dev, NULL); > if (IS_ERR(pwm->clk)) > return PTR_ERR(pwm->clk); > > + /* Get all clocks and reset line */ > + pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); > + if (IS_ERR(pwm->clk)) { > + dev_err(&pdev->dev, "get clock failed %ld\n", > + PTR_ERR(pwm->clk)); > + return PTR_ERR(pwm->clk); > + } I guess you want to drop the first assignment to pwm->clk. > + /* Fallback for old dtbs with a single clock and no name */ > + if (!pwm->clk) { > + pwm->clk = devm_clk_get(&pdev->dev, NULL); > + if (IS_ERR(pwm->clk)) { > + dev_err(&pdev->dev, "get clock failed %ld\n", > + PTR_ERR(pwm->clk)); > + return PTR_ERR(pwm->clk); > + } > + } There is a slight change of behaviour if I'm not mistaken. If you have this: clocks = <&clk1>; clock-names = "mod"; pwm { compatible = "allwinner,sun4i-a10-pwm" clocks = <&clk2>; } you now use clk1 instead of clk2 before. Assuming this is only a theoretical problem, at least pointing this out in the commit log would be good I think. > + pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); > + if (IS_ERR(pwm->bus_clk)) { > + dev_err(&pdev->dev, "get bus_clock failed %ld\n", > + PTR_ERR(pwm->bus_clk)); > + return PTR_ERR(pwm->bus_clk); > + } > + > pwm->rst = devm_reset_control_get_optional(&pdev->dev, NULL); > if (IS_ERR(pwm->rst)) { > if (PTR_ERR(pwm->rst) == -EPROBE_DEFER) > @@ -381,6 +407,13 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > return ret; > } > > + /* Enable bus clock */ > + ret = clk_prepare_enable(pwm->bus_clk); > + if (ret) { > + dev_err(&pdev->dev, "Cannot prepare_enable bus_clk\n"); I'd do s/prepare_enable/prepare and enable/ here. > + goto err_bus; > + } > + > pwm->chip.dev = &pdev->dev; > pwm->chip.ops = &sun4i_pwm_ops; > pwm->chip.base = -1; > @@ -401,6 +434,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > return 0; > > err_pwm_add: > + clk_disable_unprepare(pwm->bus_clk); > +err_bus: > reset_control_assert(pwm->rst); > > return ret; What is that clock used for? Is it required to access the hardware registers? Or is it only required while the PWM is enabled? If so you could enable the clock more finegrainded. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34822CA9ED3 for ; Mon, 4 Nov 2019 08:24:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09C912190F for ; Mon, 4 Nov 2019 08:24:21 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iRXet-0000QT-Pg; Mon, 04 Nov 2019 08:24:19 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iRXep-0000PV-V3 for linux-arm-kernel@lists.infradead.org; Mon, 04 Nov 2019 08:24:17 +0000 Received: from pty.hi.pengutronix.de ([2001:67c:670:100:1d::c5]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1iRXel-0000b5-8H; Mon, 04 Nov 2019 09:24:11 +0100 Received: from ukl by pty.hi.pengutronix.de with local (Exim 4.89) (envelope-from ) id 1iRXek-00081I-88; Mon, 04 Nov 2019 09:24:10 +0100 Date: Mon, 4 Nov 2019 09:24:10 +0100 From: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= To: =?iso-8859-1?Q?Cl=E9ment_P=E9ron?= Subject: Re: [PATCH v2 3/7] pwm: sun4i: Add an optional probe for bus clock Message-ID: <20191104082410.qdgcnphkamlzaipf@pengutronix.de> References: <20191103203334.10539-1-peron.clem@gmail.com> <20191103203334.10539-4-peron.clem@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191103203334.10539-4-peron.clem@gmail.com> User-Agent: NeoMutt/20170113 (1.7.2) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c5 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191104_002416_004027_F72A3DB1 X-CRM114-Status: GOOD ( 22.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-pwm@vger.kernel.org, Jernej Skrabec , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Maxime Ripard , Rob Herring , Chen-Yu Tsai , Thierry Reding , kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, On Sun, Nov 03, 2019 at 09:33:30PM +0100, Cl=E9ment P=E9ron wrote: > From: Jernej Skrabec > = > H6 PWM core needs bus clock to be enabled in order to work. > = > Add an optional probe for it and a fallback for previous > bindings without name on module clock. > = > Signed-off-by: Jernej Skrabec > Signed-off-by: Cl=E9ment P=E9ron > --- > drivers/pwm/pwm-sun4i.c | 36 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > = > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index d194b8ebdb00..b5e7ac364f59 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c > @@ -78,6 +78,7 @@ struct sun4i_pwm_data { > = > struct sun4i_pwm_chip { > struct pwm_chip chip; > + struct clk *bus_clk; > struct clk *clk; > struct reset_control *rst; > void __iomem *base; > @@ -367,6 +368,31 @@ static int sun4i_pwm_probe(struct platform_device *p= dev) Adding more context here: | pwm->clk =3D devm_clk_get(&pdev->dev, NULL); > if (IS_ERR(pwm->clk)) > return PTR_ERR(pwm->clk); > = > + /* Get all clocks and reset line */ > + pwm->clk =3D devm_clk_get_optional(&pdev->dev, "mod"); > + if (IS_ERR(pwm->clk)) { > + dev_err(&pdev->dev, "get clock failed %ld\n", > + PTR_ERR(pwm->clk)); > + return PTR_ERR(pwm->clk); > + } I guess you want to drop the first assignment to pwm->clk. > + /* Fallback for old dtbs with a single clock and no name */ > + if (!pwm->clk) { > + pwm->clk =3D devm_clk_get(&pdev->dev, NULL); > + if (IS_ERR(pwm->clk)) { > + dev_err(&pdev->dev, "get clock failed %ld\n", > + PTR_ERR(pwm->clk)); > + return PTR_ERR(pwm->clk); > + } > + } There is a slight change of behaviour if I'm not mistaken. If you have this: clocks =3D <&clk1>; clock-names =3D "mod"; pwm { compatible =3D "allwinner,sun4i-a10-pwm" clocks =3D <&clk2>; } you now use clk1 instead of clk2 before. Assuming this is only a theoretical problem, at least pointing this out in the commit log would be good I think. > + pwm->bus_clk =3D devm_clk_get_optional(&pdev->dev, "bus"); > + if (IS_ERR(pwm->bus_clk)) { > + dev_err(&pdev->dev, "get bus_clock failed %ld\n", > + PTR_ERR(pwm->bus_clk)); > + return PTR_ERR(pwm->bus_clk); > + } > + > pwm->rst =3D devm_reset_control_get_optional(&pdev->dev, NULL); > if (IS_ERR(pwm->rst)) { > if (PTR_ERR(pwm->rst) =3D=3D -EPROBE_DEFER) > @@ -381,6 +407,13 @@ static int sun4i_pwm_probe(struct platform_device *p= dev) > return ret; > } > = > + /* Enable bus clock */ > + ret =3D clk_prepare_enable(pwm->bus_clk); > + if (ret) { > + dev_err(&pdev->dev, "Cannot prepare_enable bus_clk\n"); I'd do s/prepare_enable/prepare and enable/ here. > + goto err_bus; > + } > + > pwm->chip.dev =3D &pdev->dev; > pwm->chip.ops =3D &sun4i_pwm_ops; > pwm->chip.base =3D -1; > @@ -401,6 +434,8 @@ static int sun4i_pwm_probe(struct platform_device *pd= ev) > return 0; > = > err_pwm_add: > + clk_disable_unprepare(pwm->bus_clk); > +err_bus: > reset_control_assert(pwm->rst); > = > return ret; What is that clock used for? Is it required to access the hardware registers? Or is it only required while the PWM is enabled? If so you could enable the clock more finegrainded. Best regards Uwe -- = Pengutronix e.K. | Uwe Kleine-K=F6nig | Industrial Linux Solutions | http://www.pengutronix.de/ | _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel