[PATCH v4 0/3] reset: npcm: add NPCM reset driver support

[PATCH v4 0/3] reset: npcm: add NPCM reset driver support

[Tomer Maimon]

This patch set adds reset controller support 
for the Nuvoton NPCM Baseboard Management Controller (BMC).

Apart of controlling all NPCM BMC reset module lines the NPCM reset driver
support NPCM BMC software reset to restarting the NPCM BMC.

Supporting NPCM USB-PHY reset as follow:

NPCM BMC USB-PHY connected to two modules USB device (UDC) and USB host.

If we will restart the USB-PHY at the UDC probe and later the 
USB host probe will restart USB-PHY again it will disable the UDC
and vice versa.

The solution is to reset the USB-PHY at the reset probe stage before 
the UDC and the USB host are initializing.

NPCM reset driver tested on NPCM750 evaluation board.

Addressed comments from:.
 - Rob Herring : https://lkml.org/lkml/2019/11/5/918

Changes since version 3:
 - Modify to dt-bindings in the commit subject.
 - Remove footer from all the sent patches.
 
Changes since version 2:
 - Remove unnecessary details in the dt-binding documentation.
 - Modify device tree binding constants.
 - initialize gcr_regmap parameter to NULL.
 - Add of_xlate support.
 - Enable NPCM reset driver by default.
 - Remove unused header include.
 - Using devm_platform_ioremap_resource instead of_address_to_resource 
	and devm_ioremap_resource.
 - Modify number of resets.
 - Using devm_reset_controller_register instead reset_controller_register.
 - Remove unnecessary probe print.
  
Changes since version 1:
 - Check if gcr_regmap parameter initialized before using it.

Tomer Maimon (3):
  dt-bindings: reset: add NPCM reset controller documentation
  dt-bindings: reset: Add binding constants for NPCM7xx reset controller
  reset: npcm: add NPCM reset controller driver

 .../bindings/reset/nuvoton,npcm-reset.txt     |  32 ++
 drivers/reset/Kconfig                         |   7 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-npcm.c                    | 281 ++++++++++++++++++
 .../dt-bindings/reset/nuvoton,npcm7xx-reset.h |  91 ++++++
 5 files changed, 412 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
 create mode 100644 drivers/reset/reset-npcm.c
 create mode 100644 include/dt-bindings/reset/nuvoton,npcm7xx-reset.h

-- 
2.22.0

[PATCH v4 1/3] dt-bindings: reset: add NPCM reset controller documentation

[Tomer Maimon]

Added device tree binding documentation for Nuvoton BMC
NPCM reset controller.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 .../bindings/reset/nuvoton,npcm-reset.txt     | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt

diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
new file mode 100644
index 000000000000..6e802703af60
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
@@ -0,0 +1,32 @@
+Nuvoton NPCM Reset controller
+
+Required properties:
+- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
+- reg : specifies physical base address and size of the register.
+- #reset-cells: must be set to 2
+
+Optional property:
+- nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
+  NPCM7xx contain four software reset that represent numbers 1 to 4.
+
+  If 'nuvoton,sw-reset-number' is not specfied software reset is disabled.
+
+Example:
+	rstc: rstc@f0801000 {
+		compatible = "nuvoton,npcm750-reset";
+		reg = <0xf0801000 0x70>;
+		#reset-cells = <2>;
+		nuvoton,sw-reset-number = <2>;
+	};
+
+Specifying reset lines connected to IP NPCM7XX modules
+======================================================
+example:
+
+        spi0: spi@..... {
+                ...
+                resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
+                ...
+        };
+
+The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
-- 
2.22.0

[PATCH v4 2/3] dt-bindings: reset: Add binding constants for NPCM7xx reset controller

[Tomer Maimon]

Add device tree binding constants for Nuvoton BMC NPCM7xx
reset controller.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 .../dt-bindings/reset/nuvoton,npcm7xx-reset.h | 91 +++++++++++++++++++
 1 file changed, 91 insertions(+)
 create mode 100644 include/dt-bindings/reset/nuvoton,npcm7xx-reset.h

diff --git a/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h b/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
new file mode 100644
index 000000000000..df088e68a9ba
--- /dev/null
+++ b/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (c) 2019 Nuvoton Technology corporation.
+
+#ifndef _DT_BINDINGS_NPCM7XX_RESET_H
+#define _DT_BINDINGS_NPCM7XX_RESET_H
+
+#define NPCM7XX_RESET_IPSRST1		0x20
+#define NPCM7XX_RESET_IPSRST2		0x24
+#define NPCM7XX_RESET_IPSRST3		0x34
+
+/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */
+#define NPCM7XX_RESET_FIU3		1
+#define NPCM7XX_RESET_UDC1		5
+#define NPCM7XX_RESET_EMC1		6
+#define NPCM7XX_RESET_UART_2_3		7
+#define NPCM7XX_RESET_UDC2		8
+#define NPCM7XX_RESET_PECI		9
+#define NPCM7XX_RESET_AES		10
+#define NPCM7XX_RESET_UART_0_1		11
+#define NPCM7XX_RESET_MC		12
+#define NPCM7XX_RESET_SMB2		13
+#define NPCM7XX_RESET_SMB3		14
+#define NPCM7XX_RESET_SMB4		15
+#define NPCM7XX_RESET_SMB5		16
+#define NPCM7XX_RESET_PWM_M0		18
+#define NPCM7XX_RESET_TIMER_0_4		19
+#define NPCM7XX_RESET_TIMER_5_9		20
+#define NPCM7XX_RESET_EMC2		21
+#define NPCM7XX_RESET_UDC4		22
+#define NPCM7XX_RESET_UDC5		23
+#define NPCM7XX_RESET_UDC6		24
+#define NPCM7XX_RESET_UDC3		25
+#define NPCM7XX_RESET_ADC		27
+#define NPCM7XX_RESET_SMB6		28
+#define NPCM7XX_RESET_SMB7		29
+#define NPCM7XX_RESET_SMB0		30
+#define NPCM7XX_RESET_SMB1		31
+
+/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */
+#define NPCM7XX_RESET_MFT0		0
+#define NPCM7XX_RESET_MFT1		1
+#define NPCM7XX_RESET_MFT2		2
+#define NPCM7XX_RESET_MFT3		3
+#define NPCM7XX_RESET_MFT4		4
+#define NPCM7XX_RESET_MFT5		5
+#define NPCM7XX_RESET_MFT6		6
+#define NPCM7XX_RESET_MFT7		7
+#define NPCM7XX_RESET_MMC		8
+#define NPCM7XX_RESET_SDHC		9
+#define NPCM7XX_RESET_GFX_SYS		10
+#define NPCM7XX_RESET_AHB_PCIBRG	11
+#define NPCM7XX_RESET_VDMA		12
+#define NPCM7XX_RESET_ECE		13
+#define NPCM7XX_RESET_VCD		14
+#define NPCM7XX_RESET_OTP		16
+#define NPCM7XX_RESET_SIOX1		18
+#define NPCM7XX_RESET_SIOX2		19
+#define NPCM7XX_RESET_3DES		21
+#define NPCM7XX_RESET_PSPI1		22
+#define NPCM7XX_RESET_PSPI2		23
+#define NPCM7XX_RESET_GMAC2		25
+#define NPCM7XX_RESET_USB_HOST		26
+#define NPCM7XX_RESET_GMAC1		28
+#define NPCM7XX_RESET_CP		31
+
+/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */
+#define NPCM7XX_RESET_PWM_M1		0
+#define NPCM7XX_RESET_SMB12		1
+#define NPCM7XX_RESET_SPIX		2
+#define NPCM7XX_RESET_SMB13		3
+#define NPCM7XX_RESET_UDC0		4
+#define NPCM7XX_RESET_UDC7		5
+#define NPCM7XX_RESET_UDC8		6
+#define NPCM7XX_RESET_UDC9		7
+#define NPCM7XX_RESET_PCI_MAILBOX	9
+#define NPCM7XX_RESET_SMB14		12
+#define NPCM7XX_RESET_SHA		13
+#define NPCM7XX_RESET_SEC_ECC		14
+#define NPCM7XX_RESET_PCIE_RC		15
+#define NPCM7XX_RESET_TIMER_10_14	16
+#define NPCM7XX_RESET_RNG		17
+#define NPCM7XX_RESET_SMB15		18
+#define NPCM7XX_RESET_SMB8		19
+#define NPCM7XX_RESET_SMB9		20
+#define NPCM7XX_RESET_SMB10		21
+#define NPCM7XX_RESET_SMB11		22
+#define NPCM7XX_RESET_ESPI		23
+#define NPCM7XX_RESET_USB_PHY_1		24
+#define NPCM7XX_RESET_USB_PHY_2		25
+
+#endif
-- 
2.22.0

[PATCH v4 3/3] reset: npcm: add NPCM reset controller driver

[Tomer Maimon]

Add Nuvoton NPCM BMC reset controller driver.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 drivers/reset/Kconfig      |   7 +
 drivers/reset/Makefile     |   1 +
 drivers/reset/reset-npcm.c | 281 +++++++++++++++++++++++++++++++++++++
 3 files changed, 289 insertions(+)
 create mode 100644 drivers/reset/reset-npcm.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 7b07281aa0ae..9e3eac30e7db 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -89,6 +89,13 @@ config RESET_MESON_AUDIO_ARB
 	  This enables the reset driver for Audio Memory Arbiter of
 	  Amlogic's A113 based SoCs
 
+config RESET_NPCM
+	bool "NPCM BMC Reset Driver" if COMPILE_TEST
+	default ARCH_NPCM
+	help
+	  This enables the reset controller driver for Nuvoton NPCM
+	  BMC SoCs.
+
 config RESET_OXNAS
 	bool
 
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index cf60ce526064..00767c03f5f2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
+obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
 obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
 obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c
new file mode 100644
index 000000000000..ad09d466d7f9
--- /dev/null
+++ b/drivers/reset/reset-npcm.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2019 Nuvoton Technology corporation.
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/of_address.h>
+
+/* NPCM7xx GCR registers */
+#define NPCM_MDLR_OFFSET	0x7C
+#define NPCM_MDLR_USBD0		BIT(9)
+#define NPCM_MDLR_USBD1		BIT(8)
+#define NPCM_MDLR_USBD2_4	BIT(21)
+#define NPCM_MDLR_USBD5_9	BIT(22)
+
+#define NPCM_USB1PHYCTL_OFFSET	0x140
+#define NPCM_USB2PHYCTL_OFFSET	0x144
+#define NPCM_USBXPHYCTL_RS	BIT(28)
+
+/* NPCM7xx Reset registers */
+#define NPCM_SWRSTR		0x14
+#define NPCM_SWRST		BIT(2)
+
+#define NPCM_IPSRST1		0x20
+#define NPCM_IPSRST1_USBD1	BIT(5)
+#define NPCM_IPSRST1_USBD2	BIT(8)
+#define NPCM_IPSRST1_USBD3	BIT(25)
+#define NPCM_IPSRST1_USBD4	BIT(22)
+#define NPCM_IPSRST1_USBD5	BIT(23)
+#define NPCM_IPSRST1_USBD6	BIT(24)
+
+#define NPCM_IPSRST2		0x24
+#define NPCM_IPSRST2_USB_HOST	BIT(26)
+
+#define NPCM_IPSRST3		0x34
+#define NPCM_IPSRST3_USBD0	BIT(4)
+#define NPCM_IPSRST3_USBD7	BIT(5)
+#define NPCM_IPSRST3_USBD8	BIT(6)
+#define NPCM_IPSRST3_USBD9	BIT(7)
+#define NPCM_IPSRST3_USBPHY1	BIT(24)
+#define NPCM_IPSRST3_USBPHY2	BIT(25)
+
+#define NPCM_RC_RESETS_PER_REG	32
+#define NPCM_MASK_RESETS	GENMASK(4, 0)
+
+struct npcm_rc_data {
+	struct reset_controller_dev rcdev;
+	struct notifier_block restart_nb;
+	u32 sw_reset_number;
+	void __iomem *base;
+	spinlock_t lock;
+};
+
+#define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev)
+
+static int npcm_rc_restart(struct notifier_block *nb, unsigned long mode,
+			   void *cmd)
+{
+	struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data,
+					       restart_nb);
+
+	writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);
+	mdelay(1000);
+
+	pr_emerg("%s: unable to restart system\n", __func__);
+
+	return NOTIFY_DONE;
+}
+
+static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev,
+				  unsigned long id, bool set)
+{
+	struct npcm_rc_data *rc = to_rc_data(rcdev);
+	unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
+	unsigned int ctrl_offset = id >> 8;
+	unsigned long flags;
+	u32 stat;
+
+	spin_lock_irqsave(&rc->lock, flags);
+	stat = readl(rc->base + ctrl_offset);
+	if (set)
+		writel(stat | rst_bit, rc->base + ctrl_offset);
+	else
+		writel(stat & ~rst_bit, rc->base + ctrl_offset);
+	spin_unlock_irqrestore(&rc->lock, flags);
+
+	return 0;
+}
+
+static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	return npcm_rc_setclear_reset(rcdev, id, true);
+}
+
+static int npcm_rc_deassert(struct reset_controller_dev *rcdev,
+			    unsigned long id)
+{
+	return npcm_rc_setclear_reset(rcdev, id, false);
+}
+
+static int npcm_rc_status(struct reset_controller_dev *rcdev,
+			  unsigned long id)
+{
+	struct npcm_rc_data *rc = to_rc_data(rcdev);
+	unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
+	unsigned int ctrl_offset = id >> 8;
+
+	return (readl(rc->base + ctrl_offset) & rst_bit);
+}
+
+/*
+ *  The following procedure should be observed in USB PHY, USB device and
+ *  USB host initialization at BMC boot
+ */
+static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
+{
+	struct device_node *np = pdev->dev.of_node;
+	u32 mdlr, iprst1, iprst2, iprst3;
+	struct regmap *gcr_regmap = NULL;
+	u32 ipsrst1_bits = 0;
+	u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
+	u32 ipsrst3_bits = 0;
+
+	if (of_device_is_compatible(np, "nuvoton,npcm750-reset")) {
+		gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
+		if (IS_ERR(gcr_regmap)) {
+			dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr\n");
+			return PTR_ERR(gcr_regmap);
+		}
+	}
+	if (!gcr_regmap)
+		return -ENXIO;
+
+	/* checking which USB device is enabled */
+	regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
+	if (!(mdlr & NPCM_MDLR_USBD0))
+		ipsrst3_bits |= NPCM_IPSRST3_USBD0;
+	if (!(mdlr & NPCM_MDLR_USBD1))
+		ipsrst1_bits |= NPCM_IPSRST1_USBD1;
+	if (!(mdlr & NPCM_MDLR_USBD2_4))
+		ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
+				 NPCM_IPSRST1_USBD3 |
+				 NPCM_IPSRST1_USBD4);
+	if (!(mdlr & NPCM_MDLR_USBD0)) {
+		ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
+				 NPCM_IPSRST1_USBD6);
+		ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
+				 NPCM_IPSRST3_USBD8 |
+				 NPCM_IPSRST3_USBD9);
+	}
+
+	/* assert reset USB PHY and USB devices */
+	iprst1 = readl(rc->base + NPCM_IPSRST1);
+	iprst2 = readl(rc->base + NPCM_IPSRST2);
+	iprst3 = readl(rc->base + NPCM_IPSRST3);
+
+	iprst1 |= ipsrst1_bits;
+	iprst2 |= ipsrst2_bits;
+	iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
+		   NPCM_IPSRST3_USBPHY2);
+
+	writel(iprst1, rc->base + NPCM_IPSRST1);
+	writel(iprst2, rc->base + NPCM_IPSRST2);
+	writel(iprst3, rc->base + NPCM_IPSRST3);
+
+	/* clear USB PHY RS bit */
+	regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
+			   NPCM_USBXPHYCTL_RS, 0);
+	regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
+			   NPCM_USBXPHYCTL_RS, 0);
+
+	/* deassert reset USB PHY */
+	iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
+	writel(iprst3, rc->base + NPCM_IPSRST3);
+
+	udelay(50);
+
+	/* set USB PHY RS bit */
+	regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
+			   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
+	regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
+			   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
+
+	/* deassert reset USB devices*/
+	iprst1 &= ~ipsrst1_bits;
+	iprst2 &= ~ipsrst2_bits;
+	iprst3 &= ~ipsrst3_bits;
+
+	writel(iprst1, rc->base + NPCM_IPSRST1);
+	writel(iprst2, rc->base + NPCM_IPSRST2);
+	writel(iprst3, rc->base + NPCM_IPSRST3);
+
+	return 0;
+}
+
+static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
+			    const struct of_phandle_args *reset_spec)
+{
+	unsigned int offset, bit;
+
+	offset = reset_spec->args[0];
+	bit = reset_spec->args[1];
+
+	return (offset << 8) | bit;
+}
+
+static const struct reset_control_ops npcm_rc_ops = {
+	.assert		= npcm_rc_assert,
+	.deassert	= npcm_rc_deassert,
+	.status		= npcm_rc_status,
+};
+
+static int npcm_rc_probe(struct platform_device *pdev)
+{
+	struct npcm_rc_data *rc;
+	int ret;
+
+	rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
+	if (!rc)
+		return -ENOMEM;
+
+	rc->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(rc->base))
+		return PTR_ERR(rc->base);
+
+	spin_lock_init(&rc->lock);
+
+	rc->rcdev.owner = THIS_MODULE;
+	rc->rcdev.nr_resets = NPCM_RC_RESETS_PER_REG;
+	rc->rcdev.ops = &npcm_rc_ops;
+	rc->rcdev.of_node = pdev->dev.of_node;
+	rc->rcdev.of_reset_n_cells = 2;
+	rc->rcdev.of_xlate = npcm_reset_xlate;
+
+	platform_set_drvdata(pdev, rc);
+
+	ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
+	if (ret) {
+		dev_err(&pdev->dev, "unable to register device\n");
+		return ret;
+	}
+
+	if (npcm_usb_reset(pdev, rc))
+		dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n");
+
+	if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number",
+				  &rc->sw_reset_number)) {
+		if (rc->sw_reset_number && rc->sw_reset_number < 5) {
+			rc->restart_nb.priority = 192,
+			rc->restart_nb.notifier_call = npcm_rc_restart,
+			ret = register_restart_handler(&rc->restart_nb);
+			if (ret)
+				dev_warn(&pdev->dev, "failed to register restart handler\n");
+		}
+	}
+
+	return ret;
+}
+
+static const struct of_device_id npcm_rc_match[] = {
+	{ .compatible = "nuvoton,npcm750-reset" },
+	{ }
+};
+
+static struct platform_driver npcm_rc_driver = {
+	.probe	= npcm_rc_probe,
+	.driver	= {
+		.name			= "npcm-reset",
+		.of_match_table		= npcm_rc_match,
+		.suppress_bind_attrs	= true,
+	},
+};
+builtin_platform_driver(npcm_rc_driver);
-- 
2.22.0

Re: [PATCH v4 3/3] reset: npcm: add NPCM reset controller driver

[Philipp Zabel]

Hi Tomer,

On Wed, 2019-11-06 at 11:58 +0200, Tomer Maimon wrote:
> Add Nuvoton NPCM BMC reset controller driver.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  drivers/reset/Kconfig      |   7 +
>  drivers/reset/Makefile     |   1 +
>  drivers/reset/reset-npcm.c | 281 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 289 insertions(+)
>  create mode 100644 drivers/reset/reset-npcm.c
> 
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 7b07281aa0ae..9e3eac30e7db 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -89,6 +89,13 @@ config RESET_MESON_AUDIO_ARB
>  	  This enables the reset driver for Audio Memory Arbiter of
>  	  Amlogic's A113 based SoCs
>  
> +config RESET_NPCM
> +	bool "NPCM BMC Reset Driver" if COMPILE_TEST
> +	default ARCH_NPCM
> +	help
> +	  This enables the reset controller driver for Nuvoton NPCM
> +	  BMC SoCs.
> +
>  config RESET_OXNAS
>  	bool
>  
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index cf60ce526064..00767c03f5f2 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
>  obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>  obj-$(CONFIG_RESET_MESON) += reset-meson.o
>  obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
> +obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
>  obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
>  obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
>  obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c
> new file mode 100644
> index 000000000000..ad09d466d7f9
> --- /dev/null
> +++ b/drivers/reset/reset-npcm.c
> @@ -0,0 +1,281 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2019 Nuvoton Technology corporation.
> +
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/init.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reboot.h>
> +#include <linux/reset-controller.h>
> +#include <linux/spinlock.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
> +#include <linux/of_address.h>
> +
> +/* NPCM7xx GCR registers */
> +#define NPCM_MDLR_OFFSET	0x7C
> +#define NPCM_MDLR_USBD0		BIT(9)
> +#define NPCM_MDLR_USBD1		BIT(8)
> +#define NPCM_MDLR_USBD2_4	BIT(21)
> +#define NPCM_MDLR_USBD5_9	BIT(22)
> +
> +#define NPCM_USB1PHYCTL_OFFSET	0x140
> +#define NPCM_USB2PHYCTL_OFFSET	0x144
> +#define NPCM_USBXPHYCTL_RS	BIT(28)
> +
> +/* NPCM7xx Reset registers */
> +#define NPCM_SWRSTR		0x14
> +#define NPCM_SWRST		BIT(2)
> +
> +#define NPCM_IPSRST1		0x20
> +#define NPCM_IPSRST1_USBD1	BIT(5)
> +#define NPCM_IPSRST1_USBD2	BIT(8)
> +#define NPCM_IPSRST1_USBD3	BIT(25)
> +#define NPCM_IPSRST1_USBD4	BIT(22)
> +#define NPCM_IPSRST1_USBD5	BIT(23)
> +#define NPCM_IPSRST1_USBD6	BIT(24)
> +
> +#define NPCM_IPSRST2		0x24
> +#define NPCM_IPSRST2_USB_HOST	BIT(26)
> +
> +#define NPCM_IPSRST3		0x34
> +#define NPCM_IPSRST3_USBD0	BIT(4)
> +#define NPCM_IPSRST3_USBD7	BIT(5)
> +#define NPCM_IPSRST3_USBD8	BIT(6)
> +#define NPCM_IPSRST3_USBD9	BIT(7)
> +#define NPCM_IPSRST3_USBPHY1	BIT(24)
> +#define NPCM_IPSRST3_USBPHY2	BIT(25)
> +
> +#define NPCM_RC_RESETS_PER_REG	32
> +#define NPCM_MASK_RESETS	GENMASK(4, 0)
> +
> +struct npcm_rc_data {
> +	struct reset_controller_dev rcdev;
> +	struct notifier_block restart_nb;
> +	u32 sw_reset_number;
> +	void __iomem *base;
> +	spinlock_t lock;
> +};
> +
> +#define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev)
> +
> +static int npcm_rc_restart(struct notifier_block *nb, unsigned long mode,
> +			   void *cmd)
> +{
> +	struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data,
> +					       restart_nb);
> +
> +	writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);
> +	mdelay(1000);
> +
> +	pr_emerg("%s: unable to restart system\n", __func__);
> +
> +	return NOTIFY_DONE;
> +}
> +
> +static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev,
> +				  unsigned long id, bool set)
> +{
> +	struct npcm_rc_data *rc = to_rc_data(rcdev);
> +	unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
> +	unsigned int ctrl_offset = id >> 8;
> +	unsigned long flags;
> +	u32 stat;
> +
> +	spin_lock_irqsave(&rc->lock, flags);
> +	stat = readl(rc->base + ctrl_offset);
> +	if (set)
> +		writel(stat | rst_bit, rc->base + ctrl_offset);
> +	else
> +		writel(stat & ~rst_bit, rc->base + ctrl_offset);
> +	spin_unlock_irqrestore(&rc->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> +	return npcm_rc_setclear_reset(rcdev, id, true);
> +}
> +
> +static int npcm_rc_deassert(struct reset_controller_dev *rcdev,
> +			    unsigned long id)
> +{
> +	return npcm_rc_setclear_reset(rcdev, id, false);
> +}
> +
> +static int npcm_rc_status(struct reset_controller_dev *rcdev,
> +			  unsigned long id)
> +{
> +	struct npcm_rc_data *rc = to_rc_data(rcdev);
> +	unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
> +	unsigned int ctrl_offset = id >> 8;
> +
> +	return (readl(rc->base + ctrl_offset) & rst_bit);
> +}
> +
> +/*
> + *  The following procedure should be observed in USB PHY, USB device and
> + *  USB host initialization at BMC boot
> + */
> +static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)

Is this npcm750 specific? If so, you could call it npcm750_usb_reset and
only call it if the compatible matches.

> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	u32 mdlr, iprst1, iprst2, iprst3;
> +	struct regmap *gcr_regmap = NULL;
> +	u32 ipsrst1_bits = 0;
> +	u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
> +	u32 ipsrst3_bits = 0;
> +
> +	if (of_device_is_compatible(np, "nuvoton,npcm750-reset")) {

Better use of_match_device(). Also see above, I think this check could
be done in probe() already?

> +		gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
> +		if (IS_ERR(gcr_regmap)) {
> +			dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr\n");
> +			return PTR_ERR(gcr_regmap);
> +		}
> +	}
> +	if (!gcr_regmap)
> +		return -ENXIO;
> +
> +	/* checking which USB device is enabled */
> +	regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
> +	if (!(mdlr & NPCM_MDLR_USBD0))
> +		ipsrst3_bits |= NPCM_IPSRST3_USBD0;
> +	if (!(mdlr & NPCM_MDLR_USBD1))
> +		ipsrst1_bits |= NPCM_IPSRST1_USBD1;
> +	if (!(mdlr & NPCM_MDLR_USBD2_4))
> +		ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
> +				 NPCM_IPSRST1_USBD3 |
> +				 NPCM_IPSRST1_USBD4);
> +	if (!(mdlr & NPCM_MDLR_USBD0)) {
> +		ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
> +				 NPCM_IPSRST1_USBD6);
> +		ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
> +				 NPCM_IPSRST3_USBD8 |
> +				 NPCM_IPSRST3_USBD9);
> +	}
> +
> +	/* assert reset USB PHY and USB devices */
> +	iprst1 = readl(rc->base + NPCM_IPSRST1);
> +	iprst2 = readl(rc->base + NPCM_IPSRST2);
> +	iprst3 = readl(rc->base + NPCM_IPSRST3);
> +
> +	iprst1 |= ipsrst1_bits;
> +	iprst2 |= ipsrst2_bits;
> +	iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
> +		   NPCM_IPSRST3_USBPHY2);
> +
> +	writel(iprst1, rc->base + NPCM_IPSRST1);
> +	writel(iprst2, rc->base + NPCM_IPSRST2);
> +	writel(iprst3, rc->base + NPCM_IPSRST3);
> +
> +	/* clear USB PHY RS bit */
> +	regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
> +			   NPCM_USBXPHYCTL_RS, 0);
> +	regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
> +			   NPCM_USBXPHYCTL_RS, 0);
> +
> +	/* deassert reset USB PHY */
> +	iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
> +	writel(iprst3, rc->base + NPCM_IPSRST3);
> +
> +	udelay(50);
> +
> +	/* set USB PHY RS bit */
> +	regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
> +			   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
> +	regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
> +			   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
> +
> +	/* deassert reset USB devices*/
> +	iprst1 &= ~ipsrst1_bits;
> +	iprst2 &= ~ipsrst2_bits;
> +	iprst3 &= ~ipsrst3_bits;
> +
> +	writel(iprst1, rc->base + NPCM_IPSRST1);
> +	writel(iprst2, rc->base + NPCM_IPSRST2);
> +	writel(iprst3, rc->base + NPCM_IPSRST3);
> +
> +	return 0;
> +}
> +
> +static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
> +			    const struct of_phandle_args *reset_spec)
> +{
> +	unsigned int offset, bit;
> +
> +	offset = reset_spec->args[0];

Return -EINVAL if offset is not one of 0x20, 0x24, or 0x34?

> +	bit = reset_spec->args[1];

Return -EINVAL if bit >= NPCM_RC_RESETS_PER_REG?

> +
> +	return (offset << 8) | bit;
> +}
> +
> +static const struct reset_control_ops npcm_rc_ops = {
> +	.assert		= npcm_rc_assert,
> +	.deassert	= npcm_rc_deassert,
> +	.status		= npcm_rc_status,
> +};
> +
> +static int npcm_rc_probe(struct platform_device *pdev)
> +{
> +	struct npcm_rc_data *rc;
> +	int ret;
> +
> +	rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
> +	if (!rc)
> +		return -ENOMEM;
> +
> +	rc->base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(rc->base))
> +		return PTR_ERR(rc->base);
> +
> +	spin_lock_init(&rc->lock);
> +
> +	rc->rcdev.owner = THIS_MODULE;
> +	rc->rcdev.nr_resets = NPCM_RC_RESETS_PER_REG;

This is not necessary since of_xlate is replaced with a custom version.

> +	rc->rcdev.ops = &npcm_rc_ops;
> +	rc->rcdev.of_node = pdev->dev.of_node;
> +	rc->rcdev.of_reset_n_cells = 2;
> +	rc->rcdev.of_xlate = npcm_reset_xlate;
> +
> +	platform_set_drvdata(pdev, rc);
> +
> +	ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
> +	if (ret) {
> +		dev_err(&pdev->dev, "unable to register device\n");
> +		return ret;
> +	}
> +
> +	if (npcm_usb_reset(pdev, rc))
> +		dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n");
> +
> +	if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number",
> +				  &rc->sw_reset_number)) {
> +		if (rc->sw_reset_number && rc->sw_reset_number < 5) {
> +			rc->restart_nb.priority = 192,
> +			rc->restart_nb.notifier_call = npcm_rc_restart,
> +			ret = register_restart_handler(&rc->restart_nb);
> +			if (ret)
> +				dev_warn(&pdev->dev, "failed to register restart handler\n");
> +		}
> +	}
> +
> +	return ret;
> +}
> +
> +static const struct of_device_id npcm_rc_match[] = {
> +	{ .compatible = "nuvoton,npcm750-reset" },
> +	{ }
> +};
> +
> +static struct platform_driver npcm_rc_driver = {
> +	.probe	= npcm_rc_probe,
> +	.driver	= {
> +		.name			= "npcm-reset",
> +		.of_match_table		= npcm_rc_match,
> +		.suppress_bind_attrs	= true,
> +	},
> +};
> +builtin_platform_driver(npcm_rc_driver);

regards
Philipp

Re: [PATCH v4 3/3] reset: npcm: add NPCM reset controller driver

[Philipp Zabel]

Hi Tomer,

On Wed, 2019-11-06 at 11:58 +0200, Tomer Maimon wrote:
> Add Nuvoton NPCM BMC reset controller driver.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  drivers/reset/Kconfig      |   7 +
>  drivers/reset/Makefile     |   1 +
>  drivers/reset/reset-npcm.c | 281 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 289 insertions(+)
>  create mode 100644 drivers/reset/reset-npcm.c
> 
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 7b07281aa0ae..9e3eac30e7db 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -89,6 +89,13 @@ config RESET_MESON_AUDIO_ARB
>  	  This enables the reset driver for Audio Memory Arbiter of
>  	  Amlogic's A113 based SoCs
>  
> +config RESET_NPCM
> +	bool "NPCM BMC Reset Driver" if COMPILE_TEST
> +	default ARCH_NPCM
> +	help
> +	  This enables the reset controller driver for Nuvoton NPCM
> +	  BMC SoCs.
> +
>  config RESET_OXNAS
>  	bool
>  
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index cf60ce526064..00767c03f5f2 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
>  obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>  obj-$(CONFIG_RESET_MESON) += reset-meson.o
>  obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
> +obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
>  obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
>  obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
>  obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c
> new file mode 100644
> index 000000000000..ad09d466d7f9
> --- /dev/null
> +++ b/drivers/reset/reset-npcm.c
> @@ -0,0 +1,281 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2019 Nuvoton Technology corporation.
> +
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/init.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reboot.h>
> +#include <linux/reset-controller.h>
> +#include <linux/spinlock.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
> +#include <linux/of_address.h>
> +
> +/* NPCM7xx GCR registers */
> +#define NPCM_MDLR_OFFSET	0x7C
> +#define NPCM_MDLR_USBD0		BIT(9)
> +#define NPCM_MDLR_USBD1		BIT(8)
> +#define NPCM_MDLR_USBD2_4	BIT(21)
> +#define NPCM_MDLR_USBD5_9	BIT(22)
> +
> +#define NPCM_USB1PHYCTL_OFFSET	0x140
> +#define NPCM_USB2PHYCTL_OFFSET	0x144
> +#define NPCM_USBXPHYCTL_RS	BIT(28)
> +
> +/* NPCM7xx Reset registers */
> +#define NPCM_SWRSTR		0x14
> +#define NPCM_SWRST		BIT(2)
> +
> +#define NPCM_IPSRST1		0x20
> +#define NPCM_IPSRST1_USBD1	BIT(5)
> +#define NPCM_IPSRST1_USBD2	BIT(8)
> +#define NPCM_IPSRST1_USBD3	BIT(25)
> +#define NPCM_IPSRST1_USBD4	BIT(22)
> +#define NPCM_IPSRST1_USBD5	BIT(23)
> +#define NPCM_IPSRST1_USBD6	BIT(24)
> +
> +#define NPCM_IPSRST2		0x24
> +#define NPCM_IPSRST2_USB_HOST	BIT(26)
> +
> +#define NPCM_IPSRST3		0x34
> +#define NPCM_IPSRST3_USBD0	BIT(4)
> +#define NPCM_IPSRST3_USBD7	BIT(5)
> +#define NPCM_IPSRST3_USBD8	BIT(6)
> +#define NPCM_IPSRST3_USBD9	BIT(7)
> +#define NPCM_IPSRST3_USBPHY1	BIT(24)
> +#define NPCM_IPSRST3_USBPHY2	BIT(25)
> +
> +#define NPCM_RC_RESETS_PER_REG	32
> +#define NPCM_MASK_RESETS	GENMASK(4, 0)
> +
> +struct npcm_rc_data {
> +	struct reset_controller_dev rcdev;
> +	struct notifier_block restart_nb;
> +	u32 sw_reset_number;
> +	void __iomem *base;
> +	spinlock_t lock;
> +};
> +
> +#define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev)
> +
> +static int npcm_rc_restart(struct notifier_block *nb, unsigned long mode,
> +			   void *cmd)
> +{
> +	struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data,
> +					       restart_nb);
> +
> +	writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);
> +	mdelay(1000);
> +
> +	pr_emerg("%s: unable to restart system\n", __func__);
> +
> +	return NOTIFY_DONE;
> +}
> +
> +static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev,
> +				  unsigned long id, bool set)
> +{
> +	struct npcm_rc_data *rc = to_rc_data(rcdev);
> +	unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
> +	unsigned int ctrl_offset = id >> 8;
> +	unsigned long flags;
> +	u32 stat;
> +
> +	spin_lock_irqsave(&rc->lock, flags);
> +	stat = readl(rc->base + ctrl_offset);
> +	if (set)
> +		writel(stat | rst_bit, rc->base + ctrl_offset);
> +	else
> +		writel(stat & ~rst_bit, rc->base + ctrl_offset);
> +	spin_unlock_irqrestore(&rc->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> +	return npcm_rc_setclear_reset(rcdev, id, true);
> +}
> +
> +static int npcm_rc_deassert(struct reset_controller_dev *rcdev,
> +			    unsigned long id)
> +{
> +	return npcm_rc_setclear_reset(rcdev, id, false);
> +}
> +
> +static int npcm_rc_status(struct reset_controller_dev *rcdev,
> +			  unsigned long id)
> +{
> +	struct npcm_rc_data *rc = to_rc_data(rcdev);
> +	unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
> +	unsigned int ctrl_offset = id >> 8;
> +
> +	return (readl(rc->base + ctrl_offset) & rst_bit);
> +}
> +
> +/*
> + *  The following procedure should be observed in USB PHY, USB device and
> + *  USB host initialization at BMC boot
> + */
> +static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)

Is this npcm750 specific? If so, you could call it npcm750_usb_reset and
only call it if the compatible matches.

> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	u32 mdlr, iprst1, iprst2, iprst3;
> +	struct regmap *gcr_regmap = NULL;
> +	u32 ipsrst1_bits = 0;
> +	u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
> +	u32 ipsrst3_bits = 0;
> +
> +	if (of_device_is_compatible(np, "nuvoton,npcm750-reset")) {

Better use of_match_device(). Also see above, I think this check could
be done in probe() already?

> +		gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
> +		if (IS_ERR(gcr_regmap)) {
> +			dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr\n");
> +			return PTR_ERR(gcr_regmap);
> +		}
> +	}
> +	if (!gcr_regmap)
> +		return -ENXIO;
> +
> +	/* checking which USB device is enabled */
> +	regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
> +	if (!(mdlr & NPCM_MDLR_USBD0))
> +		ipsrst3_bits |= NPCM_IPSRST3_USBD0;
> +	if (!(mdlr & NPCM_MDLR_USBD1))
> +		ipsrst1_bits |= NPCM_IPSRST1_USBD1;
> +	if (!(mdlr & NPCM_MDLR_USBD2_4))
> +		ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
> +				 NPCM_IPSRST1_USBD3 |
> +				 NPCM_IPSRST1_USBD4);
> +	if (!(mdlr & NPCM_MDLR_USBD0)) {
> +		ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
> +				 NPCM_IPSRST1_USBD6);
> +		ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
> +				 NPCM_IPSRST3_USBD8 |
> +				 NPCM_IPSRST3_USBD9);
> +	}
> +
> +	/* assert reset USB PHY and USB devices */
> +	iprst1 = readl(rc->base + NPCM_IPSRST1);
> +	iprst2 = readl(rc->base + NPCM_IPSRST2);
> +	iprst3 = readl(rc->base + NPCM_IPSRST3);
> +
> +	iprst1 |= ipsrst1_bits;
> +	iprst2 |= ipsrst2_bits;
> +	iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
> +		   NPCM_IPSRST3_USBPHY2);
> +
> +	writel(iprst1, rc->base + NPCM_IPSRST1);
> +	writel(iprst2, rc->base + NPCM_IPSRST2);
> +	writel(iprst3, rc->base + NPCM_IPSRST3);
> +
> +	/* clear USB PHY RS bit */
> +	regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
> +			   NPCM_USBXPHYCTL_RS, 0);
> +	regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
> +			   NPCM_USBXPHYCTL_RS, 0);
> +
> +	/* deassert reset USB PHY */
> +	iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
> +	writel(iprst3, rc->base + NPCM_IPSRST3);
> +
> +	udelay(50);
> +
> +	/* set USB PHY RS bit */
> +	regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
> +			   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
> +	regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
> +			   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
> +
> +	/* deassert reset USB devices*/
> +	iprst1 &= ~ipsrst1_bits;
> +	iprst2 &= ~ipsrst2_bits;
> +	iprst3 &= ~ipsrst3_bits;
> +
> +	writel(iprst1, rc->base + NPCM_IPSRST1);
> +	writel(iprst2, rc->base + NPCM_IPSRST2);
> +	writel(iprst3, rc->base + NPCM_IPSRST3);
> +
> +	return 0;
> +}
> +
> +static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
> +			    const struct of_phandle_args *reset_spec)
> +{
> +	unsigned int offset, bit;
> +
> +	offset = reset_spec->args[0];

Return -EINVAL if offset is not one of 0x20, 0x24, or 0x34?

> +	bit = reset_spec->args[1];

Return -EINVAL if bit >= NPCM_RC_RESETS_PER_REG?

> +
> +	return (offset << 8) | bit;
> +}
> +
> +static const struct reset_control_ops npcm_rc_ops = {
> +	.assert		= npcm_rc_assert,
> +	.deassert	= npcm_rc_deassert,
> +	.status		= npcm_rc_status,
> +};
> +
> +static int npcm_rc_probe(struct platform_device *pdev)
> +{
> +	struct npcm_rc_data *rc;
> +	int ret;
> +
> +	rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
> +	if (!rc)
> +		return -ENOMEM;
> +
> +	rc->base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(rc->base))
> +		return PTR_ERR(rc->base);
> +
> +	spin_lock_init(&rc->lock);
> +
> +	rc->rcdev.owner = THIS_MODULE;
> +	rc->rcdev.nr_resets = NPCM_RC_RESETS_PER_REG;

This is not necessary since of_xlate is replaced with a custom version.

> +	rc->rcdev.ops = &npcm_rc_ops;
> +	rc->rcdev.of_node = pdev->dev.of_node;
> +	rc->rcdev.of_reset_n_cells = 2;
> +	rc->rcdev.of_xlate = npcm_reset_xlate;
> +
> +	platform_set_drvdata(pdev, rc);
> +
> +	ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
> +	if (ret) {
> +		dev_err(&pdev->dev, "unable to register device\n");
> +		return ret;
> +	}
> +
> +	if (npcm_usb_reset(pdev, rc))
> +		dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n");
> +
> +	if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number",
> +				  &rc->sw_reset_number)) {
> +		if (rc->sw_reset_number && rc->sw_reset_number < 5) {
> +			rc->restart_nb.priority = 192,
> +			rc->restart_nb.notifier_call = npcm_rc_restart,
> +			ret = register_restart_handler(&rc->restart_nb);
> +			if (ret)
> +				dev_warn(&pdev->dev, "failed to register restart handler\n");
> +		}
> +	}
> +
> +	return ret;
> +}
> +
> +static const struct of_device_id npcm_rc_match[] = {
> +	{ .compatible = "nuvoton,npcm750-reset" },
> +	{ }
> +};
> +
> +static struct platform_driver npcm_rc_driver = {
> +	.probe	= npcm_rc_probe,
> +	.driver	= {
> +		.name			= "npcm-reset",
> +		.of_match_table		= npcm_rc_match,
> +		.suppress_bind_attrs	= true,
> +	},
> +};
> +builtin_platform_driver(npcm_rc_driver);

regards
Philipp

Re: [PATCH v4 3/3] reset: npcm: add NPCM reset controller driver

[Tomer Maimon]

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Hi Philipp,

Thanks a lot for your comments

On Wed, 6 Nov 2019 at 12:39, Philipp Zabel <p.zabel@pengutronix.de> wrote:

> Hi Tomer,
>
> On Wed, 2019-11-06 at 11:58 +0200, Tomer Maimon wrote:
> > Add Nuvoton NPCM BMC reset controller driver.
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > ---
> >  drivers/reset/Kconfig      |   7 +
> >  drivers/reset/Makefile     |   1 +
> >  drivers/reset/reset-npcm.c | 281 +++++++++++++++++++++++++++++++++++++
> >  3 files changed, 289 insertions(+)
> >  create mode 100644 drivers/reset/reset-npcm.c
> >
> > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> > index 7b07281aa0ae..9e3eac30e7db 100644
> > --- a/drivers/reset/Kconfig
> > +++ b/drivers/reset/Kconfig
> > @@ -89,6 +89,13 @@ config RESET_MESON_AUDIO_ARB
> >         This enables the reset driver for Audio Memory Arbiter of
> >         Amlogic's A113 based SoCs
> >
> > +config RESET_NPCM
> > +     bool "NPCM BMC Reset Driver" if COMPILE_TEST
> > +     default ARCH_NPCM
> > +     help
> > +       This enables the reset controller driver for Nuvoton NPCM
> > +       BMC SoCs.
> > +
> >  config RESET_OXNAS
> >       bool
> >
> > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> > index cf60ce526064..00767c03f5f2 100644
> > --- a/drivers/reset/Makefile
> > +++ b/drivers/reset/Makefile
> > @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
> >  obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
> >  obj-$(CONFIG_RESET_MESON) += reset-meson.o
> >  obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
> > +obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
> >  obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> >  obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
> >  obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> > diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c
> > new file mode 100644
> > index 000000000000..ad09d466d7f9
> > --- /dev/null
> > +++ b/drivers/reset/reset-npcm.c
> > @@ -0,0 +1,281 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (c) 2019 Nuvoton Technology corporation.
> > +
> > +#include <linux/delay.h>
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/init.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reboot.h>
> > +#include <linux/reset-controller.h>
> > +#include <linux/spinlock.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/regmap.h>
> > +#include <linux/of_address.h>
> > +
> > +/* NPCM7xx GCR registers */
> > +#define NPCM_MDLR_OFFSET     0x7C
> > +#define NPCM_MDLR_USBD0              BIT(9)
> > +#define NPCM_MDLR_USBD1              BIT(8)
> > +#define NPCM_MDLR_USBD2_4    BIT(21)
> > +#define NPCM_MDLR_USBD5_9    BIT(22)
> > +
> > +#define NPCM_USB1PHYCTL_OFFSET       0x140
> > +#define NPCM_USB2PHYCTL_OFFSET       0x144
> > +#define NPCM_USBXPHYCTL_RS   BIT(28)
> > +
> > +/* NPCM7xx Reset registers */
> > +#define NPCM_SWRSTR          0x14
> > +#define NPCM_SWRST           BIT(2)
> > +
> > +#define NPCM_IPSRST1         0x20
> > +#define NPCM_IPSRST1_USBD1   BIT(5)
> > +#define NPCM_IPSRST1_USBD2   BIT(8)
> > +#define NPCM_IPSRST1_USBD3   BIT(25)
> > +#define NPCM_IPSRST1_USBD4   BIT(22)
> > +#define NPCM_IPSRST1_USBD5   BIT(23)
> > +#define NPCM_IPSRST1_USBD6   BIT(24)
> > +
> > +#define NPCM_IPSRST2         0x24
> > +#define NPCM_IPSRST2_USB_HOST        BIT(26)
> > +
> > +#define NPCM_IPSRST3         0x34
> > +#define NPCM_IPSRST3_USBD0   BIT(4)
> > +#define NPCM_IPSRST3_USBD7   BIT(5)
> > +#define NPCM_IPSRST3_USBD8   BIT(6)
> > +#define NPCM_IPSRST3_USBD9   BIT(7)
> > +#define NPCM_IPSRST3_USBPHY1 BIT(24)
> > +#define NPCM_IPSRST3_USBPHY2 BIT(25)
> > +
> > +#define NPCM_RC_RESETS_PER_REG       32
> > +#define NPCM_MASK_RESETS     GENMASK(4, 0)
> > +
> > +struct npcm_rc_data {
> > +     struct reset_controller_dev rcdev;
> > +     struct notifier_block restart_nb;
> > +     u32 sw_reset_number;
> > +     void __iomem *base;
> > +     spinlock_t lock;
> > +};
> > +
> > +#define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev)
> > +
> > +static int npcm_rc_restart(struct notifier_block *nb, unsigned long
> mode,
> > +                        void *cmd)
> > +{
> > +     struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data,
> > +                                            restart_nb);
> > +
> > +     writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);
> > +     mdelay(1000);
> > +
> > +     pr_emerg("%s: unable to restart system\n", __func__);
> > +
> > +     return NOTIFY_DONE;
> > +}
> > +
> > +static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev,
> > +                               unsigned long id, bool set)
> > +{
> > +     struct npcm_rc_data *rc = to_rc_data(rcdev);
> > +     unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
> > +     unsigned int ctrl_offset = id >> 8;
> > +     unsigned long flags;
> > +     u32 stat;
> > +
> > +     spin_lock_irqsave(&rc->lock, flags);
> > +     stat = readl(rc->base + ctrl_offset);
> > +     if (set)
> > +             writel(stat | rst_bit, rc->base + ctrl_offset);
> > +     else
> > +             writel(stat & ~rst_bit, rc->base + ctrl_offset);
> > +     spin_unlock_irqrestore(&rc->lock, flags);
> > +
> > +     return 0;
> > +}
> > +
> > +static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned
> long id)
> > +{
> > +     return npcm_rc_setclear_reset(rcdev, id, true);
> > +}
> > +
> > +static int npcm_rc_deassert(struct reset_controller_dev *rcdev,
> > +                         unsigned long id)
> > +{
> > +     return npcm_rc_setclear_reset(rcdev, id, false);
> > +}
> > +
> > +static int npcm_rc_status(struct reset_controller_dev *rcdev,
> > +                       unsigned long id)
> > +{
> > +     struct npcm_rc_data *rc = to_rc_data(rcdev);
> > +     unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
> > +     unsigned int ctrl_offset = id >> 8;
> > +
> > +     return (readl(rc->base + ctrl_offset) & rst_bit);
> > +}
> > +
> > +/*
> > + *  The following procedure should be observed in USB PHY, USB device
> and
> > + *  USB host initialization at BMC boot
> > + */
> > +static int npcm_usb_reset(struct platform_device *pdev, struct
> npcm_rc_data *rc)
>
> Is this npcm750 specific? If so, you could call it npcm750_usb_reset and
> only call it if the compatible matches.

No, we will need it also in future BMC's

>
>
> +{
> > +     struct device_node *np = pdev->dev.of_node;
> > +     u32 mdlr, iprst1, iprst2, iprst3;
> > +     struct regmap *gcr_regmap = NULL;
> > +     u32 ipsrst1_bits = 0;
> > +     u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
> > +     u32 ipsrst3_bits = 0;
> > +
> > +     if (of_device_is_compatible(np, "nuvoton,npcm750-reset")) {
>
> Better use of_match_device(). Also see above, I think this check could
> be done in probe() already?
>
I will use  of_match_device. because the nuvoton,npcm750-reset used only at
npcm_usb_reset and in the next BMC version we will need to get other
reset device I prefer to leave it the  npcm_usb_reset function, is it O.K?

>
> > +             gcr_regmap =
> syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
> > +             if (IS_ERR(gcr_regmap)) {
> > +                     dev_err(&pdev->dev, "Failed to find
> nuvoton,npcm750-gcr\n");
> > +                     return PTR_ERR(gcr_regmap);
> > +             }
> > +     }
> > +     if (!gcr_regmap)
> > +             return -ENXIO;
> > +
> > +     /* checking which USB device is enabled */
> > +     regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
> > +     if (!(mdlr & NPCM_MDLR_USBD0))
> > +             ipsrst3_bits |= NPCM_IPSRST3_USBD0;
> > +     if (!(mdlr & NPCM_MDLR_USBD1))
> > +             ipsrst1_bits |= NPCM_IPSRST1_USBD1;
> > +     if (!(mdlr & NPCM_MDLR_USBD2_4))
> > +             ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
> > +                              NPCM_IPSRST1_USBD3 |
> > +                              NPCM_IPSRST1_USBD4);
> > +     if (!(mdlr & NPCM_MDLR_USBD0)) {
> > +             ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
> > +                              NPCM_IPSRST1_USBD6);
> > +             ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
> > +                              NPCM_IPSRST3_USBD8 |
> > +                              NPCM_IPSRST3_USBD9);
> > +     }
> > +
> > +     /* assert reset USB PHY and USB devices */
> > +     iprst1 = readl(rc->base + NPCM_IPSRST1);
> > +     iprst2 = readl(rc->base + NPCM_IPSRST2);
> > +     iprst3 = readl(rc->base + NPCM_IPSRST3);
> > +
> > +     iprst1 |= ipsrst1_bits;
> > +     iprst2 |= ipsrst2_bits;
> > +     iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
> > +                NPCM_IPSRST3_USBPHY2);
> > +
> > +     writel(iprst1, rc->base + NPCM_IPSRST1);
> > +     writel(iprst2, rc->base + NPCM_IPSRST2);
> > +     writel(iprst3, rc->base + NPCM_IPSRST3);
> > +
> > +     /* clear USB PHY RS bit */
> > +     regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
> > +                        NPCM_USBXPHYCTL_RS, 0);
> > +     regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
> > +                        NPCM_USBXPHYCTL_RS, 0);
> > +
> > +     /* deassert reset USB PHY */
> > +     iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
> > +     writel(iprst3, rc->base + NPCM_IPSRST3);
> > +
> > +     udelay(50);
> > +
> > +     /* set USB PHY RS bit */
> > +     regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
> > +                        NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
> > +     regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
> > +                        NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
> > +
> > +     /* deassert reset USB devices*/
> > +     iprst1 &= ~ipsrst1_bits;
> > +     iprst2 &= ~ipsrst2_bits;
> > +     iprst3 &= ~ipsrst3_bits;
> > +
> > +     writel(iprst1, rc->base + NPCM_IPSRST1);
> > +     writel(iprst2, rc->base + NPCM_IPSRST2);
> > +     writel(iprst3, rc->base + NPCM_IPSRST3);
> > +
> > +     return 0;
> > +}
> > +
> > +static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
> > +                         const struct of_phandle_args *reset_spec)
> > +{
> > +     unsigned int offset, bit;
> > +
> > +     offset = reset_spec->args[0];
>
> Return -EINVAL if offset is not one of 0x20, 0x24, or 0x34?

> +     bit = reset_spec->args[1];
>
> Return -EINVAL if bit >= NPCM_RC_RESETS_PER_REG?
>
> > +
> > +     return (offset << 8) | bit;
> > +}
> > +
> > +static const struct reset_control_ops npcm_rc_ops = {
> > +     .assert         = npcm_rc_assert,
> > +     .deassert       = npcm_rc_deassert,
> > +     .status         = npcm_rc_status,
> > +};
> > +
> > +static int npcm_rc_probe(struct platform_device *pdev)
> > +{
> > +     struct npcm_rc_data *rc;
> > +     int ret;
> > +
> > +     rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
> > +     if (!rc)
> > +             return -ENOMEM;
> > +
> > +     rc->base = devm_platform_ioremap_resource(pdev, 0);
> > +     if (IS_ERR(rc->base))
> > +             return PTR_ERR(rc->base);
> > +
> > +     spin_lock_init(&rc->lock);
> > +
> > +     rc->rcdev.owner = THIS_MODULE;
> > +     rc->rcdev.nr_resets = NPCM_RC_RESETS_PER_REG;
>
> This is not necessary since of_xlate is replaced with a custom version.
>
> > +     rc->rcdev.ops = &npcm_rc_ops;
> > +     rc->rcdev.of_node = pdev->dev.of_node;
> > +     rc->rcdev.of_reset_n_cells = 2;
> > +     rc->rcdev.of_xlate = npcm_reset_xlate;
> > +
> > +     platform_set_drvdata(pdev, rc);
> > +
> > +     ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
> > +     if (ret) {
> > +             dev_err(&pdev->dev, "unable to register device\n");
> > +             return ret;
> > +     }
> > +
> > +     if (npcm_usb_reset(pdev, rc))
> > +             dev_warn(&pdev->dev, "NPCM USB reset failed, can cause
> issues with UDC and USB host\n");
> > +
> > +     if (!of_property_read_u32(pdev->dev.of_node,
> "nuvoton,sw-reset-number",
> > +                               &rc->sw_reset_number)) {
> > +             if (rc->sw_reset_number && rc->sw_reset_number < 5) {
> > +                     rc->restart_nb.priority = 192,
> > +                     rc->restart_nb.notifier_call = npcm_rc_restart,
> > +                     ret = register_restart_handler(&rc->restart_nb);
> > +                     if (ret)
> > +                             dev_warn(&pdev->dev, "failed to register
> restart handler\n");
> > +             }
> > +     }
> > +
> > +     return ret;
> > +}
> > +
> > +static const struct of_device_id npcm_rc_match[] = {
> > +     { .compatible = "nuvoton,npcm750-reset" },
> > +     { }
> > +};
> > +
> > +static struct platform_driver npcm_rc_driver = {
> > +     .probe  = npcm_rc_probe,
> > +     .driver = {
> > +             .name                   = "npcm-reset",
> > +             .of_match_table         = npcm_rc_match,
> > +             .suppress_bind_attrs    = true,
> > +     },
> > +};
> > +builtin_platform_driver(npcm_rc_driver);
>
> regards
> Philipp
>
>
Thanks a lot

Tomer

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Re: [PATCH v4 3/3] reset: npcm: add NPCM reset controller driver

[Philipp Zabel]

Hi Tomer,

On Wed, 2019-11-06 at 13:14 +0200, Tomer Maimon wrote:
[...]
> On Wed, 6 Nov 2019 at 12:39, Philipp Zabel <p.zabel@pengutronix.de> wrote:
[...]
> > Is this npcm750 specific? If so, you could call it npcm750_usb_reset and
> > only call it if the compatible matches.
> 
> No, we will need it also in future BMC's

Ok, thank you for clarifying.

> > 
> > +{
> > > +     struct device_node *np = pdev->dev.of_node;
> > > +     u32 mdlr, iprst1, iprst2, iprst3;
> > > +     struct regmap *gcr_regmap = NULL;
> > > +     u32 ipsrst1_bits = 0;
> > > +     u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
> > > +     u32 ipsrst3_bits = 0;
> > > +
> > > +     if (of_device_is_compatible(np, "nuvoton,npcm750-reset")) {
> > 
> > Better use of_match_device(). Also see above, I think this check could
> > be done in probe() already?
> > 
> I will use  of_match_device. because the nuvoton,npcm750-reset used only at
> npcm_usb_reset and in the next BMC version we will need to get other
> reset device I prefer to leave it the  npcm_usb_reset function, is it O.K?

Yes, that is fine. I would store the GCR lookup compatible string in a
per-device const struct that is accessible through of_device_id->data.

> > > +             gcr_regmap =
> > syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
> > > +             if (IS_ERR(gcr_regmap)) {
> > > +                     dev_err(&pdev->dev, "Failed to find
> > nuvoton,npcm750-gcr\n");
> > > +                     return PTR_ERR(gcr_regmap);
> > > +             }
> > > +     }
> > > +     if (!gcr_regmap)
> > > +             return -ENXIO;

^ This code could then be the same for all platforms.

regards
Philipp

Re: [PATCH v4 3/3] reset: npcm: add NPCM reset controller driver

[Philipp Zabel]

Hi Tomer,

On Wed, 2019-11-06 at 13:14 +0200, Tomer Maimon wrote:
[...]
> On Wed, 6 Nov 2019 at 12:39, Philipp Zabel <p.zabel@pengutronix.de> wrote:
[...]
> > Is this npcm750 specific? If so, you could call it npcm750_usb_reset and
> > only call it if the compatible matches.
> 
> No, we will need it also in future BMC's

Ok, thank you for clarifying.

> > 
> > +{
> > > +     struct device_node *np = pdev->dev.of_node;
> > > +     u32 mdlr, iprst1, iprst2, iprst3;
> > > +     struct regmap *gcr_regmap = NULL;
> > > +     u32 ipsrst1_bits = 0;
> > > +     u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
> > > +     u32 ipsrst3_bits = 0;
> > > +
> > > +     if (of_device_is_compatible(np, "nuvoton,npcm750-reset")) {
> > 
> > Better use of_match_device(). Also see above, I think this check could
> > be done in probe() already?
> > 
> I will use  of_match_device. because the nuvoton,npcm750-reset used only at
> npcm_usb_reset and in the next BMC version we will need to get other
> reset device I prefer to leave it the  npcm_usb_reset function, is it O.K?

Yes, that is fine. I would store the GCR lookup compatible string in a
per-device const struct that is accessible through of_device_id->data.

> > > +             gcr_regmap =
> > syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
> > > +             if (IS_ERR(gcr_regmap)) {
> > > +                     dev_err(&pdev->dev, "Failed to find
> > nuvoton,npcm750-gcr\n");
> > > +                     return PTR_ERR(gcr_regmap);
> > > +             }
> > > +     }
> > > +     if (!gcr_regmap)
> > > +             return -ENXIO;

^ This code could then be the same for all platforms.

regards
Philipp