From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35BD0C5DF62 for ; Wed, 6 Nov 2019 13:56:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0BD682178F for ; Wed, 6 Nov 2019 13:56:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731839AbfKFN4x (ORCPT ); Wed, 6 Nov 2019 08:56:53 -0500 Received: from mga06.intel.com ([134.134.136.31]:42789 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731836AbfKFN4x (ORCPT ); Wed, 6 Nov 2019 08:56:53 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Nov 2019 05:56:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,274,1569308400"; d="scan'208";a="212777655" Received: from lahna.fi.intel.com (HELO lahna) ([10.237.72.163]) by fmsmga001.fm.intel.com with SMTP; 06 Nov 2019 05:56:49 -0800 Received: by lahna (sSMTP sendmail emulation); Wed, 06 Nov 2019 15:56:48 +0200 Date: Wed, 6 Nov 2019 15:56:48 +0200 From: Mika Westerberg To: Andy Shevchenko Cc: Bartosz Golaszewski , Linus Walleij , linux-gpio@vger.kernel.org, Hans de Goede Subject: Re: [PATCH v2 6/7] pinctrl: baytrail: Add GPIO <-> pin mapping ranges via callback Message-ID: <20191106135648.GT2552@lahna.fi.intel.com> References: <20191105203557.78562-1-andriy.shevchenko@linux.intel.com> <20191105203557.78562-7-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191105203557.78562-7-andriy.shevchenko@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Tue, Nov 05, 2019 at 10:35:56PM +0200, Andy Shevchenko wrote: > When IRQ chip is instantiated via GPIO library flow, the few functions, > in particular the ACPI event registration mechanism, on some of ACPI based > platforms expect that the pin ranges are initialized to that point. > > Add GPIO <-> pin mapping ranges via callback in the GPIO library flow. > > Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg