From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F3A3C5DF61 for ; Thu, 7 Nov 2019 11:16:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 040272187F for ; Thu, 7 Nov 2019 11:16:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388482AbfKGLQR (ORCPT ); Thu, 7 Nov 2019 06:16:17 -0500 Received: from rtits2.realtek.com ([211.75.126.72]:43299 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388178AbfKGLQP (ORCPT ); Thu, 7 Nov 2019 06:16:15 -0500 Authenticated-By: X-SpamFilter-By: BOX Solutions SpamTrap 5.62 with qID xA7BG7TT012861, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (RTITCASV01.realtek.com.tw[172.21.6.18]) by rtits2.realtek.com.tw (8.15.2/2.57/5.78) with ESMTPS id xA7BG7TT012861 (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 7 Nov 2019 19:16:07 +0800 Received: from localhost.localdomain (172.21.68.126) by RTITCASV01.realtek.com.tw (172.21.6.18) with Microsoft SMTP Server id 14.3.468.0; Thu, 7 Nov 2019 19:16:06 +0800 From: To: CC: , Subject: [PATCH 0/4] rtw88: enable PCI CLKREQ and ASPM Date: Thu, 7 Nov 2019 19:15:59 +0800 Message-ID: <20191107111603.12317-1-yhchuang@realtek.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.21.68.126] Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Yan-Hsuan Chuang This set enables PCI CLKREQ and ASPM for power save. Basically they should be enabled through PCI configuration space, but for some reasons (see comments in pci.c), they are disabled by default. So driver requires to check the configuration space and then enable them properly. Yan-Hsuan Chuang (4): rtw88: pci: use macros to access PCI DBI/MDIO registers rtw88: pci: use for loop instead of while loop for DBI/MDIO rtw88: pci: enable CLKREQ function if host supports it rtw88: allows to enable/disable HCI link PS mechanism drivers/net/wireless/realtek/rtw88/hci.h | 6 + drivers/net/wireless/realtek/rtw88/pci.c | 158 ++++++++++++++++++++--- drivers/net/wireless/realtek/rtw88/pci.h | 16 +++ drivers/net/wireless/realtek/rtw88/ps.c | 6 + 4 files changed, 168 insertions(+), 18 deletions(-) -- 2.17.1