* [PATCH 1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
@ 2019-11-07 21:45 ` José Roberto de Souza
0 siblings, 0 replies; 26+ messages in thread
From: José Roberto de Souza @ 2019-11-07 21:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
TRANS_DDI_MST_TRANSPORT_SELECT is 2 bits wide not 3, it was taking
one bit from EDP/DSI Input Select.
Fixes: b3545e086877 ("drm/i915/tgl: add support to one DP-MST stream")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a607ea520829..70459a3d93e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9665,7 +9665,7 @@ enum skl_power_gate {
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
-#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(12, 10)
+#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
--
2.24.0
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^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
@ 2019-11-07 21:45 ` José Roberto de Souza
0 siblings, 0 replies; 26+ messages in thread
From: José Roberto de Souza @ 2019-11-07 21:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
TRANS_DDI_MST_TRANSPORT_SELECT is 2 bits wide not 3, it was taking
one bit from EDP/DSI Input Select.
Fixes: b3545e086877 ("drm/i915/tgl: add support to one DP-MST stream")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a607ea520829..70459a3d93e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9665,7 +9665,7 @@ enum skl_power_gate {
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
-#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(12, 10)
+#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
--
2.24.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 2/3] drm/i915/display/dsi: Add support to pipe D
@ 2019-11-07 21:45 ` José Roberto de Souza
0 siblings, 0 replies; 26+ messages in thread
From: José Roberto de Souza @ 2019-11-07 21:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Adding pipe D support to DSI transcoder.
Not adding it for EDP transcoder code paths as only TGL has 4 pipes
and it do not have a EDP transcoder.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 8eb2d7f29c82..f688207932e0 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -745,6 +745,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
case PIPE_C:
tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
break;
+ case PIPE_D:
+ tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
+ break;
}
/* enable DDI buffer */
@@ -1325,6 +1328,9 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
case TRANS_DDI_EDP_INPUT_C_ONOFF:
*pipe = PIPE_C;
break;
+ case TRANS_DDI_EDP_INPUT_D_ONOFF:
+ *pipe = PIPE_D;
+ break;
default:
DRM_ERROR("Invalid PIPE input\n");
goto out;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 70459a3d93e3..88d1430a6800 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9665,6 +9665,7 @@ enum skl_power_gate {
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
+#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
--
2.24.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/display/dsi: Add support to pipe D
@ 2019-11-07 21:45 ` José Roberto de Souza
0 siblings, 0 replies; 26+ messages in thread
From: José Roberto de Souza @ 2019-11-07 21:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Adding pipe D support to DSI transcoder.
Not adding it for EDP transcoder code paths as only TGL has 4 pipes
and it do not have a EDP transcoder.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 8eb2d7f29c82..f688207932e0 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -745,6 +745,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
case PIPE_C:
tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
break;
+ case PIPE_D:
+ tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
+ break;
}
/* enable DDI buffer */
@@ -1325,6 +1328,9 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
case TRANS_DDI_EDP_INPUT_C_ONOFF:
*pipe = PIPE_C;
break;
+ case TRANS_DDI_EDP_INPUT_D_ONOFF:
+ *pipe = PIPE_D;
+ break;
default:
DRM_ERROR("Invalid PIPE input\n");
goto out;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 70459a3d93e3..88d1430a6800 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9665,6 +9665,7 @@ enum skl_power_gate {
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
+#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
--
2.24.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-07 21:45 ` José Roberto de Souza
0 siblings, 0 replies; 26+ messages in thread
From: José Roberto de Souza @ 2019-11-07 21:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
This register was being enabled after enable TRANS_DDI_FUNC_CTL and
PIPECONF/TRANS_CONF while BSpec states that it should be set when
enabling TRANS_DDI_FUNC_CTL.
BSpec: 49190
BSpec: 22243
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++----------------
drivers/gpu/drm/i915/display/intel_display.c | 6 ------
2 files changed, 2 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 398c6f054a6e..3d5fce878600 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}
-void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
- bool state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- u32 temp;
-
- temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
- if (state == true)
- temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
- else
- temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
- I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
-}
-
/*
* Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
*
@@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
u32 temp;
temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
+ temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 551de2baa569..3b4aea253f8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (pipe_config->has_pch_encoder)
lpt_pch_enable(state, pipe_config);
- if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
- intel_ddi_set_vc_payload_alloc(pipe_config, true);
-
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
@@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_disable_pipe(old_crtc_state);
- if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
- intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
-
if (INTEL_GEN(dev_priv) >= 11)
icl_disable_transcoder_port_sync(old_crtc_state);
--
2.24.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-07 21:45 ` José Roberto de Souza
0 siblings, 0 replies; 26+ messages in thread
From: José Roberto de Souza @ 2019-11-07 21:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
This register was being enabled after enable TRANS_DDI_FUNC_CTL and
PIPECONF/TRANS_CONF while BSpec states that it should be set when
enabling TRANS_DDI_FUNC_CTL.
BSpec: 49190
BSpec: 22243
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++----------------
drivers/gpu/drm/i915/display/intel_display.c | 6 ------
2 files changed, 2 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 398c6f054a6e..3d5fce878600 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}
-void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
- bool state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- u32 temp;
-
- temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
- if (state == true)
- temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
- else
- temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
- I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
-}
-
/*
* Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
*
@@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
u32 temp;
temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
+ temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 551de2baa569..3b4aea253f8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (pipe_config->has_pch_encoder)
lpt_pch_enable(state, pipe_config);
- if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
- intel_ddi_set_vc_payload_alloc(pipe_config, true);
-
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
@@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_disable_pipe(old_crtc_state);
- if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
- intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
-
if (INTEL_GEN(dev_priv) >= 11)
icl_disable_transcoder_port_sync(old_crtc_state);
--
2.24.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
@ 2019-11-07 22:29 ` Lucas De Marchi
0 siblings, 0 replies; 26+ messages in thread
From: Lucas De Marchi @ 2019-11-07 22:29 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 01:45:57PM -0800, Jose Souza wrote:
>TRANS_DDI_MST_TRANSPORT_SELECT is 2 bits wide not 3, it was taking
>one bit from EDP/DSI Input Select.
>
>Fixes: b3545e086877 ("drm/i915/tgl: add support to one DP-MST stream")
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
ugh, facepalm
Double checked that it matches the spec.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
thanks
Lucas De Marchi
>---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index a607ea520829..70459a3d93e3 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -9665,7 +9665,7 @@ enum skl_power_gate {
> #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
> #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
> #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
>-#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(12, 10)
>+#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
> #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
> REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
> #define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
>--
>2.24.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
@ 2019-11-07 22:29 ` Lucas De Marchi
0 siblings, 0 replies; 26+ messages in thread
From: Lucas De Marchi @ 2019-11-07 22:29 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 01:45:57PM -0800, Jose Souza wrote:
>TRANS_DDI_MST_TRANSPORT_SELECT is 2 bits wide not 3, it was taking
>one bit from EDP/DSI Input Select.
>
>Fixes: b3545e086877 ("drm/i915/tgl: add support to one DP-MST stream")
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
ugh, facepalm
Double checked that it matches the spec.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
thanks
Lucas De Marchi
>---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index a607ea520829..70459a3d93e3 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -9665,7 +9665,7 @@ enum skl_power_gate {
> #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
> #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
> #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
>-#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(12, 10)
>+#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
> #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
> REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
> #define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
>--
>2.24.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-07 22:44 ` Lucas De Marchi
0 siblings, 0 replies; 26+ messages in thread
From: Lucas De Marchi @ 2019-11-07 22:44 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
>This register was being enabled after enable TRANS_DDI_FUNC_CTL and
>PIPECONF/TRANS_CONF while BSpec states that it should be set when
>enabling TRANS_DDI_FUNC_CTL.
>
>BSpec: 49190
not what I read here.
8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be configured.
Then configure and enable TRANS_DDI_FUNC_CTL.
8l. If DisplayPort multistream - Enable pipe VC payload allocation in TRANS_DDI_FUNC_CTL
But yes, this needs to be done before TRANS_CONF.
>BSpec: 22243
same here. But as long as we don't do step 8k, I think they can in fact
be combined.
These cover TGL and ICL only, while the code goes until haswell. Are you
sure it's safe for the others?
thanks
Lucas De Marchi
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++----------------
> drivers/gpu/drm/i915/display/intel_display.c | 6 ------
> 2 files changed, 2 insertions(+), 22 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 398c6f054a6e..3d5fce878600 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
> I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> }
>
>-void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
>- bool state)
>-{
>- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>- u32 temp;
>-
>- temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>- if (state == true)
>- temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>- else
>- temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>- I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
>-}
>-
> /*
> * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
> *
>@@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
> u32 temp;
>
> temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
>+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
>+ temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> }
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 551de2baa569..3b4aea253f8c 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (pipe_config->has_pch_encoder)
> lpt_pch_enable(state, pipe_config);
>
>- if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
>- intel_ddi_set_vc_payload_alloc(pipe_config, true);
>-
> assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
>@@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_disable_pipe(old_crtc_state);
>
>- if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
>- intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
>-
> if (INTEL_GEN(dev_priv) >= 11)
> icl_disable_transcoder_port_sync(old_crtc_state);
>
>--
>2.24.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-07 22:44 ` Lucas De Marchi
0 siblings, 0 replies; 26+ messages in thread
From: Lucas De Marchi @ 2019-11-07 22:44 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
>This register was being enabled after enable TRANS_DDI_FUNC_CTL and
>PIPECONF/TRANS_CONF while BSpec states that it should be set when
>enabling TRANS_DDI_FUNC_CTL.
>
>BSpec: 49190
not what I read here.
8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be configured.
Then configure and enable TRANS_DDI_FUNC_CTL.
8l. If DisplayPort multistream - Enable pipe VC payload allocation in TRANS_DDI_FUNC_CTL
But yes, this needs to be done before TRANS_CONF.
>BSpec: 22243
same here. But as long as we don't do step 8k, I think they can in fact
be combined.
These cover TGL and ICL only, while the code goes until haswell. Are you
sure it's safe for the others?
thanks
Lucas De Marchi
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++----------------
> drivers/gpu/drm/i915/display/intel_display.c | 6 ------
> 2 files changed, 2 insertions(+), 22 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 398c6f054a6e..3d5fce878600 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
> I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> }
>
>-void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
>- bool state)
>-{
>- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>- u32 temp;
>-
>- temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>- if (state == true)
>- temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>- else
>- temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>- I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
>-}
>-
> /*
> * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
> *
>@@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
> u32 temp;
>
> temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
>+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
>+ temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> }
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 551de2baa569..3b4aea253f8c 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (pipe_config->has_pch_encoder)
> lpt_pch_enable(state, pipe_config);
>
>- if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
>- intel_ddi_set_vc_payload_alloc(pipe_config, true);
>-
> assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
>@@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_disable_pipe(old_crtc_state);
>
>- if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
>- intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
>-
> if (INTEL_GEN(dev_priv) >= 11)
> icl_disable_transcoder_port_sync(old_crtc_state);
>
>--
>2.24.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-07 22:56 ` Souza, Jose
0 siblings, 0 replies; 26+ messages in thread
From: Souza, Jose @ 2019-11-07 22:56 UTC (permalink / raw)
To: De Marchi, Lucas; +Cc: intel-gfx
On Thu, 2019-11-07 at 14:44 -0800, Lucas De Marchi wrote:
> On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
> > This register was being enabled after enable TRANS_DDI_FUNC_CTL and
> > PIPECONF/TRANS_CONF while BSpec states that it should be set when
> > enabling TRANS_DDI_FUNC_CTL.
> >
> > BSpec: 49190
>
> not what I read here.
>
> 8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be
> configured.
> Then configure and enable TRANS_DDI_FUNC_CTL.
We call icl_enable_trans_port_sync() in haswell_crtc_enable() and then
a few lines later intel_ddi_enable_transcoder_func(), if not do that
right away was a problem people working in port sync would get this
issue.
>
> 8l. If DisplayPort multistream - Enable pipe VC payload allocation in
> TRANS_DDI_FUNC_CTL
>
> But yes, this needs to be done before TRANS_CONF.
>
> > BSpec: 22243
>
> same here. But as long as we don't do step 8k, I think they can in
> fact
> be combined.
>
> These cover TGL and ICL only, while the code goes until haswell. Are
> you
> sure it's safe for the others?
>
I had only checked if the register exist since HSW but now I checked
HSW, BDW and SKL sequence all of then requires this.
BSpec: 4223
BSpec: 4163
BSpec: 4231
> thanks
> Lucas De Marchi
>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++---------------
> > -
> > drivers/gpu/drm/i915/display/intel_display.c | 6 ------
> > 2 files changed, 2 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 398c6f054a6e..3d5fce878600 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct
> > intel_crtc_state *crtc_state,
> > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> > }
> >
> > -void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
> > *crtc_state,
> > - bool state)
> > -{
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > - u32 temp;
> > -
> > - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > - if (state == true)
> > - temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > - else
> > - temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > -}
> > -
> > /*
> > * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
> > *
> > @@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const
> > struct intel_crtc_state *crtc_state)
> > u32 temp;
> >
> > temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
> > + temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 551de2baa569..3b4aea253f8c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct
> > intel_crtc_state *pipe_config,
> > if (pipe_config->has_pch_encoder)
> > lpt_pch_enable(state, pipe_config);
> >
> > - if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
> > - intel_ddi_set_vc_payload_alloc(pipe_config, true);
> > -
> > assert_vblank_disabled(crtc);
> > intel_crtc_vblank_on(pipe_config);
> >
> > @@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct
> > intel_crtc_state *old_crtc_state,
> > if (!transcoder_is_dsi(cpu_transcoder))
> > intel_disable_pipe(old_crtc_state);
> >
> > - if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
> > - intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
> > -
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_disable_transcoder_port_sync(old_crtc_state);
> >
> > --
> > 2.24.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-07 22:56 ` Souza, Jose
0 siblings, 0 replies; 26+ messages in thread
From: Souza, Jose @ 2019-11-07 22:56 UTC (permalink / raw)
To: De Marchi, Lucas; +Cc: intel-gfx
On Thu, 2019-11-07 at 14:44 -0800, Lucas De Marchi wrote:
> On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
> > This register was being enabled after enable TRANS_DDI_FUNC_CTL and
> > PIPECONF/TRANS_CONF while BSpec states that it should be set when
> > enabling TRANS_DDI_FUNC_CTL.
> >
> > BSpec: 49190
>
> not what I read here.
>
> 8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be
> configured.
> Then configure and enable TRANS_DDI_FUNC_CTL.
We call icl_enable_trans_port_sync() in haswell_crtc_enable() and then
a few lines later intel_ddi_enable_transcoder_func(), if not do that
right away was a problem people working in port sync would get this
issue.
>
> 8l. If DisplayPort multistream - Enable pipe VC payload allocation in
> TRANS_DDI_FUNC_CTL
>
> But yes, this needs to be done before TRANS_CONF.
>
> > BSpec: 22243
>
> same here. But as long as we don't do step 8k, I think they can in
> fact
> be combined.
>
> These cover TGL and ICL only, while the code goes until haswell. Are
> you
> sure it's safe for the others?
>
I had only checked if the register exist since HSW but now I checked
HSW, BDW and SKL sequence all of then requires this.
BSpec: 4223
BSpec: 4163
BSpec: 4231
> thanks
> Lucas De Marchi
>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++---------------
> > -
> > drivers/gpu/drm/i915/display/intel_display.c | 6 ------
> > 2 files changed, 2 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 398c6f054a6e..3d5fce878600 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct
> > intel_crtc_state *crtc_state,
> > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> > }
> >
> > -void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
> > *crtc_state,
> > - bool state)
> > -{
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > - u32 temp;
> > -
> > - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > - if (state == true)
> > - temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > - else
> > - temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > -}
> > -
> > /*
> > * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
> > *
> > @@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const
> > struct intel_crtc_state *crtc_state)
> > u32 temp;
> >
> > temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
> > + temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 551de2baa569..3b4aea253f8c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct
> > intel_crtc_state *pipe_config,
> > if (pipe_config->has_pch_encoder)
> > lpt_pch_enable(state, pipe_config);
> >
> > - if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
> > - intel_ddi_set_vc_payload_alloc(pipe_config, true);
> > -
> > assert_vblank_disabled(crtc);
> > intel_crtc_vblank_on(pipe_config);
> >
> > @@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct
> > intel_crtc_state *old_crtc_state,
> > if (!transcoder_is_dsi(cpu_transcoder))
> > intel_disable_pipe(old_crtc_state);
> >
> > - if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
> > - intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
> > -
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_disable_transcoder_port_sync(old_crtc_state);
> >
> > --
> > 2.24.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-07 23:10 ` Lucas De Marchi
0 siblings, 0 replies; 26+ messages in thread
From: Lucas De Marchi @ 2019-11-07 23:10 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 10:56:09PM +0000, Jose Souza wrote:
>On Thu, 2019-11-07 at 14:44 -0800, Lucas De Marchi wrote:
>> On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
>> > This register was being enabled after enable TRANS_DDI_FUNC_CTL and
>> > PIPECONF/TRANS_CONF while BSpec states that it should be set when
>> > enabling TRANS_DDI_FUNC_CTL.
>> >
>> > BSpec: 49190
>>
>> not what I read here.
>>
>> 8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be
>> configured.
>> Then configure and enable TRANS_DDI_FUNC_CTL.
>
>We call icl_enable_trans_port_sync() in haswell_crtc_enable() and then
>a few lines later intel_ddi_enable_transcoder_func(), if not do that
>right away was a problem people working in port sync would get this
>issue.
not what I meant. I meant the spec says to enable TRANS_DDI_FUNC_CTL,
do step 8k, and then enable pipe VC payload allocation.
We aren't doing step 8k anywhere though, as I noted below.
Lucas De Marchi
>
>>
>> 8l. If DisplayPort multistream - Enable pipe VC payload allocation in
>> TRANS_DDI_FUNC_CTL
>>
>> But yes, this needs to be done before TRANS_CONF.
>>
>> > BSpec: 22243
>>
>> same here. But as long as we don't do step 8k, I think they can in
>> fact
>> be combined.
>>
>> These cover TGL and ICL only, while the code goes until haswell. Are
>> you
>> sure it's safe for the others?
>>
>
>I had only checked if the register exist since HSW but now I checked
>HSW, BDW and SKL sequence all of then requires this.
>
>BSpec: 4223
>BSpec: 4163
>BSpec: 4231
>
>
>> thanks
>> Lucas De Marchi
>>
>> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++---------------
>> > -
>> > drivers/gpu/drm/i915/display/intel_display.c | 6 ------
>> > 2 files changed, 2 insertions(+), 22 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > index 398c6f054a6e..3d5fce878600 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > @@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct
>> > intel_crtc_state *crtc_state,
>> > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
>> > }
>> >
>> > -void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
>> > *crtc_state,
>> > - bool state)
>> > -{
>> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> > - u32 temp;
>> > -
>> > - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>> > - if (state == true)
>> > - temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > - else
>> > - temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
>> > -}
>> > -
>> > /*
>> > * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
>> > *
>> > @@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const
>> > struct intel_crtc_state *crtc_state)
>> > u32 temp;
>> >
>> > temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
>> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
>> > + temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
>> > }
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > b/drivers/gpu/drm/i915/display/intel_display.c
>> > index 551de2baa569..3b4aea253f8c 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > @@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct
>> > intel_crtc_state *pipe_config,
>> > if (pipe_config->has_pch_encoder)
>> > lpt_pch_enable(state, pipe_config);
>> >
>> > - if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
>> > - intel_ddi_set_vc_payload_alloc(pipe_config, true);
>> > -
>> > assert_vblank_disabled(crtc);
>> > intel_crtc_vblank_on(pipe_config);
>> >
>> > @@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct
>> > intel_crtc_state *old_crtc_state,
>> > if (!transcoder_is_dsi(cpu_transcoder))
>> > intel_disable_pipe(old_crtc_state);
>> >
>> > - if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
>> > - intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
>> > -
>> > if (INTEL_GEN(dev_priv) >= 11)
>> > icl_disable_transcoder_port_sync(old_crtc_state);
>> >
>> > --
>> > 2.24.0
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-07 23:10 ` Lucas De Marchi
0 siblings, 0 replies; 26+ messages in thread
From: Lucas De Marchi @ 2019-11-07 23:10 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 10:56:09PM +0000, Jose Souza wrote:
>On Thu, 2019-11-07 at 14:44 -0800, Lucas De Marchi wrote:
>> On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
>> > This register was being enabled after enable TRANS_DDI_FUNC_CTL and
>> > PIPECONF/TRANS_CONF while BSpec states that it should be set when
>> > enabling TRANS_DDI_FUNC_CTL.
>> >
>> > BSpec: 49190
>>
>> not what I read here.
>>
>> 8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be
>> configured.
>> Then configure and enable TRANS_DDI_FUNC_CTL.
>
>We call icl_enable_trans_port_sync() in haswell_crtc_enable() and then
>a few lines later intel_ddi_enable_transcoder_func(), if not do that
>right away was a problem people working in port sync would get this
>issue.
not what I meant. I meant the spec says to enable TRANS_DDI_FUNC_CTL,
do step 8k, and then enable pipe VC payload allocation.
We aren't doing step 8k anywhere though, as I noted below.
Lucas De Marchi
>
>>
>> 8l. If DisplayPort multistream - Enable pipe VC payload allocation in
>> TRANS_DDI_FUNC_CTL
>>
>> But yes, this needs to be done before TRANS_CONF.
>>
>> > BSpec: 22243
>>
>> same here. But as long as we don't do step 8k, I think they can in
>> fact
>> be combined.
>>
>> These cover TGL and ICL only, while the code goes until haswell. Are
>> you
>> sure it's safe for the others?
>>
>
>I had only checked if the register exist since HSW but now I checked
>HSW, BDW and SKL sequence all of then requires this.
>
>BSpec: 4223
>BSpec: 4163
>BSpec: 4231
>
>
>> thanks
>> Lucas De Marchi
>>
>> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++---------------
>> > -
>> > drivers/gpu/drm/i915/display/intel_display.c | 6 ------
>> > 2 files changed, 2 insertions(+), 22 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > index 398c6f054a6e..3d5fce878600 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > @@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct
>> > intel_crtc_state *crtc_state,
>> > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
>> > }
>> >
>> > -void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
>> > *crtc_state,
>> > - bool state)
>> > -{
>> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> > - u32 temp;
>> > -
>> > - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>> > - if (state == true)
>> > - temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > - else
>> > - temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
>> > -}
>> > -
>> > /*
>> > * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
>> > *
>> > @@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const
>> > struct intel_crtc_state *crtc_state)
>> > u32 temp;
>> >
>> > temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
>> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
>> > + temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
>> > }
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > b/drivers/gpu/drm/i915/display/intel_display.c
>> > index 551de2baa569..3b4aea253f8c 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > @@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct
>> > intel_crtc_state *pipe_config,
>> > if (pipe_config->has_pch_encoder)
>> > lpt_pch_enable(state, pipe_config);
>> >
>> > - if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
>> > - intel_ddi_set_vc_payload_alloc(pipe_config, true);
>> > -
>> > assert_vblank_disabled(crtc);
>> > intel_crtc_vblank_on(pipe_config);
>> >
>> > @@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct
>> > intel_crtc_state *old_crtc_state,
>> > if (!transcoder_is_dsi(cpu_transcoder))
>> > intel_disable_pipe(old_crtc_state);
>> >
>> > - if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
>> > - intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
>> > -
>> > if (INTEL_GEN(dev_priv) >= 11)
>> > icl_disable_transcoder_port_sync(old_crtc_state);
>> >
>> > --
>> > 2.24.0
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-07 23:18 ` Souza, Jose
0 siblings, 0 replies; 26+ messages in thread
From: Souza, Jose @ 2019-11-07 23:18 UTC (permalink / raw)
To: De Marchi, Lucas; +Cc: intel-gfx
On Thu, 2019-11-07 at 15:10 -0800, Lucas De Marchi wrote:
> On Thu, Nov 07, 2019 at 10:56:09PM +0000, Jose Souza wrote:
> > On Thu, 2019-11-07 at 14:44 -0800, Lucas De Marchi wrote:
> > > On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
> > > > This register was being enabled after enable TRANS_DDI_FUNC_CTL
> > > > and
> > > > PIPECONF/TRANS_CONF while BSpec states that it should be set
> > > > when
> > > > enabling TRANS_DDI_FUNC_CTL.
> > > >
> > > > BSpec: 49190
> > >
> > > not what I read here.
> > >
> > > 8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be
> > > configured.
> > > Then configure and enable TRANS_DDI_FUNC_CTL.
> >
> > We call icl_enable_trans_port_sync() in haswell_crtc_enable() and
> > then
> > a few lines later intel_ddi_enable_transcoder_func(), if not do
> > that
> > right away was a problem people working in port sync would get this
> > issue.
>
> not what I meant. I meant the spec says to enable TRANS_DDI_FUNC_CTL,
> do step 8k, and then enable pipe VC payload allocation.
>
> We aren't doing step 8k anywhere though, as I noted below.
8k is a VRR step that we don't support yet.
>
> Lucas De Marchi
>
> > > 8l. If DisplayPort multistream - Enable pipe VC payload
> > > allocation in
> > > TRANS_DDI_FUNC_CTL
> > >
> > > But yes, this needs to be done before TRANS_CONF.
> > >
> > > > BSpec: 22243
> > >
> > > same here. But as long as we don't do step 8k, I think they can
> > > in
> > > fact
> > > be combined.
> > >
> > > These cover TGL and ICL only, while the code goes until haswell.
> > > Are
> > > you
> > > sure it's safe for the others?
> > >
> >
> > I had only checked if the register exist since HSW but now I
> > checked
> > HSW, BDW and SKL sequence all of then requires this.
> >
> > BSpec: 4223
> > BSpec: 4163
> > BSpec: 4231
> >
> >
> > > thanks
> > > Lucas De Marchi
> > >
> > > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++-----------
> > > > ----
> > > > -
> > > > drivers/gpu/drm/i915/display/intel_display.c | 6 ------
> > > > 2 files changed, 2 insertions(+), 22 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > index 398c6f054a6e..3d5fce878600 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > @@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct
> > > > intel_crtc_state *crtc_state,
> > > > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> > > > }
> > > >
> > > > -void intel_ddi_set_vc_payload_alloc(const struct
> > > > intel_crtc_state
> > > > *crtc_state,
> > > > - bool state)
> > > > -{
> > > > - struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> > > > >uapi.crtc);
> > > > - struct drm_i915_private *dev_priv = to_i915(crtc-
> > > > >base.dev);
> > > > - enum transcoder cpu_transcoder = crtc_state-
> > > > >cpu_transcoder;
> > > > - u32 temp;
> > > > -
> > > > - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > > > - if (state == true)
> > > > - temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > > > - else
> > > > - temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > > > - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > > > -}
> > > > -
> > > > /*
> > > > * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
> > > > *
> > > > @@ -1924,6 +1908,8 @@ void
> > > > intel_ddi_enable_transcoder_func(const
> > > > struct intel_crtc_state *crtc_state)
> > > > u32 temp;
> > > >
> > > > temp =
> > > > intel_ddi_transcoder_func_reg_val_get(crtc_state);
> > > > + if (intel_crtc_has_type(crtc_state,
> > > > INTEL_OUTPUT_DP_MST))
> > > > + temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > > > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > > > }
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 551de2baa569..3b4aea253f8c 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct
> > > > intel_crtc_state *pipe_config,
> > > > if (pipe_config->has_pch_encoder)
> > > > lpt_pch_enable(state, pipe_config);
> > > >
> > > > - if (intel_crtc_has_type(pipe_config,
> > > > INTEL_OUTPUT_DP_MST))
> > > > - intel_ddi_set_vc_payload_alloc(pipe_config,
> > > > true);
> > > > -
> > > > assert_vblank_disabled(crtc);
> > > > intel_crtc_vblank_on(pipe_config);
> > > >
> > > > @@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct
> > > > intel_crtc_state *old_crtc_state,
> > > > if (!transcoder_is_dsi(cpu_transcoder))
> > > > intel_disable_pipe(old_crtc_state);
> > > >
> > > > - if (intel_crtc_has_type(old_crtc_state,
> > > > INTEL_OUTPUT_DP_MST))
> > > > - intel_ddi_set_vc_payload_alloc(old_crtc_state,
> > > > false);
> > > > -
> > > > if (INTEL_GEN(dev_priv) >= 11)
> > > > icl_disable_transcoder_port_sync(old_crtc_state
> > > > );
> > > >
> > > > --
> > > > 2.24.0
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-07 23:18 ` Souza, Jose
0 siblings, 0 replies; 26+ messages in thread
From: Souza, Jose @ 2019-11-07 23:18 UTC (permalink / raw)
To: De Marchi, Lucas; +Cc: intel-gfx
On Thu, 2019-11-07 at 15:10 -0800, Lucas De Marchi wrote:
> On Thu, Nov 07, 2019 at 10:56:09PM +0000, Jose Souza wrote:
> > On Thu, 2019-11-07 at 14:44 -0800, Lucas De Marchi wrote:
> > > On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
> > > > This register was being enabled after enable TRANS_DDI_FUNC_CTL
> > > > and
> > > > PIPECONF/TRANS_CONF while BSpec states that it should be set
> > > > when
> > > > enabling TRANS_DDI_FUNC_CTL.
> > > >
> > > > BSpec: 49190
> > >
> > > not what I read here.
> > >
> > > 8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be
> > > configured.
> > > Then configure and enable TRANS_DDI_FUNC_CTL.
> >
> > We call icl_enable_trans_port_sync() in haswell_crtc_enable() and
> > then
> > a few lines later intel_ddi_enable_transcoder_func(), if not do
> > that
> > right away was a problem people working in port sync would get this
> > issue.
>
> not what I meant. I meant the spec says to enable TRANS_DDI_FUNC_CTL,
> do step 8k, and then enable pipe VC payload allocation.
>
> We aren't doing step 8k anywhere though, as I noted below.
8k is a VRR step that we don't support yet.
>
> Lucas De Marchi
>
> > > 8l. If DisplayPort multistream - Enable pipe VC payload
> > > allocation in
> > > TRANS_DDI_FUNC_CTL
> > >
> > > But yes, this needs to be done before TRANS_CONF.
> > >
> > > > BSpec: 22243
> > >
> > > same here. But as long as we don't do step 8k, I think they can
> > > in
> > > fact
> > > be combined.
> > >
> > > These cover TGL and ICL only, while the code goes until haswell.
> > > Are
> > > you
> > > sure it's safe for the others?
> > >
> >
> > I had only checked if the register exist since HSW but now I
> > checked
> > HSW, BDW and SKL sequence all of then requires this.
> >
> > BSpec: 4223
> > BSpec: 4163
> > BSpec: 4231
> >
> >
> > > thanks
> > > Lucas De Marchi
> > >
> > > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++-----------
> > > > ----
> > > > -
> > > > drivers/gpu/drm/i915/display/intel_display.c | 6 ------
> > > > 2 files changed, 2 insertions(+), 22 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > index 398c6f054a6e..3d5fce878600 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > @@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct
> > > > intel_crtc_state *crtc_state,
> > > > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> > > > }
> > > >
> > > > -void intel_ddi_set_vc_payload_alloc(const struct
> > > > intel_crtc_state
> > > > *crtc_state,
> > > > - bool state)
> > > > -{
> > > > - struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> > > > >uapi.crtc);
> > > > - struct drm_i915_private *dev_priv = to_i915(crtc-
> > > > >base.dev);
> > > > - enum transcoder cpu_transcoder = crtc_state-
> > > > >cpu_transcoder;
> > > > - u32 temp;
> > > > -
> > > > - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > > > - if (state == true)
> > > > - temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > > > - else
> > > > - temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > > > - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > > > -}
> > > > -
> > > > /*
> > > > * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
> > > > *
> > > > @@ -1924,6 +1908,8 @@ void
> > > > intel_ddi_enable_transcoder_func(const
> > > > struct intel_crtc_state *crtc_state)
> > > > u32 temp;
> > > >
> > > > temp =
> > > > intel_ddi_transcoder_func_reg_val_get(crtc_state);
> > > > + if (intel_crtc_has_type(crtc_state,
> > > > INTEL_OUTPUT_DP_MST))
> > > > + temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > > > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > > > }
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 551de2baa569..3b4aea253f8c 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct
> > > > intel_crtc_state *pipe_config,
> > > > if (pipe_config->has_pch_encoder)
> > > > lpt_pch_enable(state, pipe_config);
> > > >
> > > > - if (intel_crtc_has_type(pipe_config,
> > > > INTEL_OUTPUT_DP_MST))
> > > > - intel_ddi_set_vc_payload_alloc(pipe_config,
> > > > true);
> > > > -
> > > > assert_vblank_disabled(crtc);
> > > > intel_crtc_vblank_on(pipe_config);
> > > >
> > > > @@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct
> > > > intel_crtc_state *old_crtc_state,
> > > > if (!transcoder_is_dsi(cpu_transcoder))
> > > > intel_disable_pipe(old_crtc_state);
> > > >
> > > > - if (intel_crtc_has_type(old_crtc_state,
> > > > INTEL_OUTPUT_DP_MST))
> > > > - intel_ddi_set_vc_payload_alloc(old_crtc_state,
> > > > false);
> > > > -
> > > > if (INTEL_GEN(dev_priv) >= 11)
> > > > icl_disable_transcoder_port_sync(old_crtc_state
> > > > );
> > > >
> > > > --
> > > > 2.24.0
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
@ 2019-11-08 1:14 ` Patchwork
0 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-11-08 1:14 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
URL : https://patchwork.freedesktop.org/series/69160/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7290 -> Patchwork_15187
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/index.html
Known issues
------------
Here are the changes found in Patchwork_15187 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_blt:
- fi-bsw-nick: [PASS][1] -> [DMESG-FAIL][2] ([fdo#112176])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-bsw-nick/igt@i915_selftest@live_blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-bsw-nick/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111407])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111736]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-tgl-u/igt@gem_exec_create@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-tgl-u/igt@gem_exec_create@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][7] ([fdo#108511]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
[fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176
Participating hosts (50 -> 46)
------------------------------
Additional (1): fi-hsw-4770r
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7290 -> Patchwork_15187
CI-20190529: 20190529
CI_DRM_7290: 869abae66a356231cfa6645cf491adde3590cba8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15187: d3bc4af38ceb942887aac7fe9b4cf145882dd59e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d3bc4af38ceb drm/i915/display/mst: Enable virtual channel payload allocation earlier
23526380578b drm/i915/display/dsi: Add support to pipe D
a7de06e7e7d4 drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
@ 2019-11-08 1:14 ` Patchwork
0 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-11-08 1:14 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
URL : https://patchwork.freedesktop.org/series/69160/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7290 -> Patchwork_15187
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/index.html
Known issues
------------
Here are the changes found in Patchwork_15187 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_blt:
- fi-bsw-nick: [PASS][1] -> [DMESG-FAIL][2] ([fdo#112176])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-bsw-nick/igt@i915_selftest@live_blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-bsw-nick/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111407])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111736]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-tgl-u/igt@gem_exec_create@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-tgl-u/igt@gem_exec_create@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][7] ([fdo#108511]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
[fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176
Participating hosts (50 -> 46)
------------------------------
Additional (1): fi-hsw-4770r
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7290 -> Patchwork_15187
CI-20190529: 20190529
CI_DRM_7290: 869abae66a356231cfa6645cf491adde3590cba8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15187: d3bc4af38ceb942887aac7fe9b4cf145882dd59e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d3bc4af38ceb drm/i915/display/mst: Enable virtual channel payload allocation earlier
23526380578b drm/i915/display/dsi: Add support to pipe D
a7de06e7e7d4 drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
@ 2019-11-09 10:47 ` Patchwork
0 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-11-09 10:47 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
URL : https://patchwork.freedesktop.org/series/69160/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7290_full -> Patchwork_15187_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_15187_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-apl2/igt@gem_ctx_isolation@bcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_ctx_isolation@vcs1-s3:
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([fdo#111832])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@gem_ctx_isolation@vcs1-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@gem_ctx_isolation@vcs1-s3.html
* igt@gem_ctx_switch@vcs1-heavy:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@gem_ctx_switch@vcs1-heavy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_ctx_switch@vcs1-heavy.html
* igt@gem_eio@suspend:
- shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([fdo#111850])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb3/igt@gem_eio@suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb3/igt@gem_eio@suspend.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [PASS][11] -> [FAIL][12] ([fdo#109661])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb6/igt@gem_eio@unwedge-stress.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#110854])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_balancer@smoke.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_nop@basic-parallel:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111747])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@gem_exec_nop@basic-parallel.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb7/igt@gem_exec_nop@basic-parallel.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109276]) +9 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#112146]) +4 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb7/igt@gem_exec_schedule@preemptive-hang-bsd.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_sync@basic-all:
- shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([fdo#103558] / [fdo#105602]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl7/igt@gem_sync@basic-all.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl2/igt@gem_sync@basic-all.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][23] -> [DMESG-WARN][24] ([fdo#111870])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb5/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-hsw: [PASS][25] -> [DMESG-WARN][26] ([fdo#111870])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-snb: [PASS][27] -> [DMESG-WARN][28] ([fdo#110789] / [fdo#111870])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_workarounds@suspend-resume-context:
- shard-tglb: [PASS][29] -> [INCOMPLETE][30] ([fdo#111832] / [fdo#111850]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@gem_workarounds@suspend-resume-context.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb1/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_selftest@live_hangcheck:
- shard-hsw: [PASS][31] -> [DMESG-FAIL][32] ([fdo#111991])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw2/igt@i915_selftest@live_hangcheck.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw1/igt@i915_selftest@live_hangcheck.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [PASS][33] -> [INCOMPLETE][34] ([fdo#111747] / [fdo#111832] / [fdo#111850])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb9/igt@kms_fbcon_fbt@fbc-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-tglb: [PASS][35] -> [FAIL][36] ([fdo#103167]) +6 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: [PASS][37] -> [FAIL][38] ([fdo#103167]) +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [PASS][39] -> [FAIL][40] ([fdo#103166])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][41] -> [FAIL][42] ([fdo#103166])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109441]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][45] -> [FAIL][46] ([fdo#99912])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl2/igt@kms_setmode@basic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][47] -> [DMESG-WARN][48] ([fdo#108566]) +4 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][49] ([fdo#112080]) -> [PASS][50] +9 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb6/igt@gem_busy@busy-vcs1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_isolation@vecs0-s3:
- shard-tglb: [INCOMPLETE][51] ([fdo#111832]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@gem_ctx_isolation@vecs0-s3.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb9/igt@gem_ctx_isolation@vecs0-s3.html
* igt@gem_ctx_persistence@vcs1-persistence:
- shard-iclb: [SKIP][53] ([fdo#109276] / [fdo#112080]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb7/igt@gem_ctx_persistence@vcs1-persistence.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@gem_ctx_persistence@vcs1-persistence.html
* igt@gem_eio@in-flight-suspend:
- shard-tglb: [INCOMPLETE][55] ([fdo#111832] / [fdo#111850] / [fdo#112081]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb7/igt@gem_eio@in-flight-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb6/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_nop@basic-series:
- shard-tglb: [INCOMPLETE][57] ([fdo#111747]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb6/igt@gem_exec_nop@basic-series.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb4/igt@gem_exec_nop@basic-series.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][59] ([fdo#112146]) -> [PASS][60] +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [SKIP][61] ([fdo#109276]) -> [PASS][62] +14 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb3/igt@gem_exec_schedule@promotion-bsd1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_exec_schedule@smoketest-blt:
- shard-tglb: [INCOMPLETE][63] ([fdo#111867]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb6/igt@gem_exec_schedule@smoketest-blt.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@gem_exec_schedule@smoketest-blt.html
* igt@gem_mmap_gtt@hang:
- shard-snb: [INCOMPLETE][65] ([fdo#105411]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb2/igt@gem_mmap_gtt@hang.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb5/igt@gem_mmap_gtt@hang.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [DMESG-WARN][67] ([fdo#110789] / [fdo#111870]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [DMESG-WARN][69] ([fdo#111870]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@gem_userptr_blits@sync-unmap-after-close.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw5/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][71] ([fdo#110548]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-tglb: [INCOMPLETE][73] ([fdo#111832] / [fdo#111850]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb8/igt@i915_pm_rpm@system-suspend-execbuf.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb4/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][75] ([fdo#108566]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_color@pipe-a-gamma:
- shard-skl: [FAIL][77] ([fdo#104782]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_color@pipe-a-gamma.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_color@pipe-a-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen:
- shard-skl: [FAIL][79] ([fdo#103232]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][81] ([fdo#108566]) -> [PASS][82] +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
- shard-skl: [INCOMPLETE][83] ([fdo#110741]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- shard-skl: [FAIL][85] ([fdo#103184] / [fdo#103232]) -> [PASS][86] +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][87] ([fdo#105363]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [INCOMPLETE][89] ([fdo#103540]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@kms_flip@flip-vs-suspend.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw5/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-tglb: [INCOMPLETE][91] ([fdo#111832] / [fdo#111850] / [fdo#112031]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@kms_flip@flip-vs-suspend-interruptible.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb6/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [FAIL][93] ([fdo#103167]) -> [PASS][94] +4 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-iclb: [FAIL][95] ([fdo#103167] / [fdo#110378]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [FAIL][97] ([fdo#103167]) -> [PASS][98] +4 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-skl: [FAIL][99] ([fdo#103167]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- shard-skl: [FAIL][101] ([fdo#103191]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][103] ([fdo#108145] / [fdo#110403]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][105] ([fdo#109642] / [fdo#111068]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb5/igt@kms_psr2_su@page_flip.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-tglb: [INCOMPLETE][107] ([fdo#111850]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb3/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[10
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
@ 2019-11-09 10:47 ` Patchwork
0 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-11-09 10:47 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
URL : https://patchwork.freedesktop.org/series/69160/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7290_full -> Patchwork_15187_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_15187_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-apl2/igt@gem_ctx_isolation@bcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_ctx_isolation@vcs1-s3:
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([fdo#111832])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@gem_ctx_isolation@vcs1-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@gem_ctx_isolation@vcs1-s3.html
* igt@gem_ctx_switch@vcs1-heavy:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@gem_ctx_switch@vcs1-heavy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_ctx_switch@vcs1-heavy.html
* igt@gem_eio@suspend:
- shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([fdo#111850])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb3/igt@gem_eio@suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb3/igt@gem_eio@suspend.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [PASS][11] -> [FAIL][12] ([fdo#109661])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb6/igt@gem_eio@unwedge-stress.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#110854])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_balancer@smoke.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_nop@basic-parallel:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111747])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@gem_exec_nop@basic-parallel.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb7/igt@gem_exec_nop@basic-parallel.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109276]) +9 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#112146]) +4 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb7/igt@gem_exec_schedule@preemptive-hang-bsd.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_sync@basic-all:
- shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([fdo#103558] / [fdo#105602]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl7/igt@gem_sync@basic-all.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl2/igt@gem_sync@basic-all.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][23] -> [DMESG-WARN][24] ([fdo#111870])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb5/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-hsw: [PASS][25] -> [DMESG-WARN][26] ([fdo#111870])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-snb: [PASS][27] -> [DMESG-WARN][28] ([fdo#110789] / [fdo#111870])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_workarounds@suspend-resume-context:
- shard-tglb: [PASS][29] -> [INCOMPLETE][30] ([fdo#111832] / [fdo#111850]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@gem_workarounds@suspend-resume-context.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb1/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_selftest@live_hangcheck:
- shard-hsw: [PASS][31] -> [DMESG-FAIL][32] ([fdo#111991])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw2/igt@i915_selftest@live_hangcheck.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw1/igt@i915_selftest@live_hangcheck.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [PASS][33] -> [INCOMPLETE][34] ([fdo#111747] / [fdo#111832] / [fdo#111850])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb9/igt@kms_fbcon_fbt@fbc-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-tglb: [PASS][35] -> [FAIL][36] ([fdo#103167]) +6 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: [PASS][37] -> [FAIL][38] ([fdo#103167]) +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [PASS][39] -> [FAIL][40] ([fdo#103166])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][41] -> [FAIL][42] ([fdo#103166])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109441]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][45] -> [FAIL][46] ([fdo#99912])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl2/igt@kms_setmode@basic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][47] -> [DMESG-WARN][48] ([fdo#108566]) +4 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][49] ([fdo#112080]) -> [PASS][50] +9 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb6/igt@gem_busy@busy-vcs1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_isolation@vecs0-s3:
- shard-tglb: [INCOMPLETE][51] ([fdo#111832]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@gem_ctx_isolation@vecs0-s3.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb9/igt@gem_ctx_isolation@vecs0-s3.html
* igt@gem_ctx_persistence@vcs1-persistence:
- shard-iclb: [SKIP][53] ([fdo#109276] / [fdo#112080]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb7/igt@gem_ctx_persistence@vcs1-persistence.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@gem_ctx_persistence@vcs1-persistence.html
* igt@gem_eio@in-flight-suspend:
- shard-tglb: [INCOMPLETE][55] ([fdo#111832] / [fdo#111850] / [fdo#112081]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb7/igt@gem_eio@in-flight-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb6/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_nop@basic-series:
- shard-tglb: [INCOMPLETE][57] ([fdo#111747]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb6/igt@gem_exec_nop@basic-series.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb4/igt@gem_exec_nop@basic-series.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][59] ([fdo#112146]) -> [PASS][60] +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [SKIP][61] ([fdo#109276]) -> [PASS][62] +14 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb3/igt@gem_exec_schedule@promotion-bsd1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_exec_schedule@smoketest-blt:
- shard-tglb: [INCOMPLETE][63] ([fdo#111867]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb6/igt@gem_exec_schedule@smoketest-blt.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@gem_exec_schedule@smoketest-blt.html
* igt@gem_mmap_gtt@hang:
- shard-snb: [INCOMPLETE][65] ([fdo#105411]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb2/igt@gem_mmap_gtt@hang.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb5/igt@gem_mmap_gtt@hang.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [DMESG-WARN][67] ([fdo#110789] / [fdo#111870]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [DMESG-WARN][69] ([fdo#111870]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@gem_userptr_blits@sync-unmap-after-close.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw5/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][71] ([fdo#110548]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-tglb: [INCOMPLETE][73] ([fdo#111832] / [fdo#111850]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb8/igt@i915_pm_rpm@system-suspend-execbuf.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb4/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][75] ([fdo#108566]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_color@pipe-a-gamma:
- shard-skl: [FAIL][77] ([fdo#104782]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_color@pipe-a-gamma.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_color@pipe-a-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen:
- shard-skl: [FAIL][79] ([fdo#103232]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][81] ([fdo#108566]) -> [PASS][82] +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
- shard-skl: [INCOMPLETE][83] ([fdo#110741]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- shard-skl: [FAIL][85] ([fdo#103184] / [fdo#103232]) -> [PASS][86] +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][87] ([fdo#105363]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [INCOMPLETE][89] ([fdo#103540]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@kms_flip@flip-vs-suspend.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw5/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-tglb: [INCOMPLETE][91] ([fdo#111832] / [fdo#111850] / [fdo#112031]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@kms_flip@flip-vs-suspend-interruptible.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb6/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [FAIL][93] ([fdo#103167]) -> [PASS][94] +4 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-iclb: [FAIL][95] ([fdo#103167] / [fdo#110378]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [FAIL][97] ([fdo#103167]) -> [PASS][98] +4 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-skl: [FAIL][99] ([fdo#103167]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- shard-skl: [FAIL][101] ([fdo#103191]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][103] ([fdo#108145] / [fdo#110403]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][105] ([fdo#109642] / [fdo#111068]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb5/igt@kms_psr2_su@page_flip.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-tglb: [INCOMPLETE][107] ([fdo#111850]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb3/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[10
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 2/3] drm/i915/display/dsi: Add support to pipe D
@ 2019-11-13 18:58 ` Lucas De Marchi
0 siblings, 0 replies; 26+ messages in thread
From: Lucas De Marchi @ 2019-11-13 18:58 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 01:45:58PM -0800, Jose Souza wrote:
>Adding pipe D support to DSI transcoder.
>Not adding it for EDP transcoder code paths as only TGL has 4 pipes
>and it do not have a EDP transcoder.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/icl_dsi.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 7 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>index 8eb2d7f29c82..f688207932e0 100644
>--- a/drivers/gpu/drm/i915/display/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>@@ -745,6 +745,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> case PIPE_C:
> tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
> break;
>+ case PIPE_D:
>+ tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
>+ break;
> }
>
> /* enable DDI buffer */
>@@ -1325,6 +1328,9 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> case TRANS_DDI_EDP_INPUT_C_ONOFF:
> *pipe = PIPE_C;
> break;
>+ case TRANS_DDI_EDP_INPUT_D_ONOFF:
>+ *pipe = PIPE_D;
>+ break;
> default:
> DRM_ERROR("Invalid PIPE input\n");
> goto out;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 70459a3d93e3..88d1430a6800 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -9665,6 +9665,7 @@ enum skl_power_gate {
> #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
> #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
> #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
>+#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
> #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
> #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
> REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
>--
>2.24.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/display/dsi: Add support to pipe D
@ 2019-11-13 18:58 ` Lucas De Marchi
0 siblings, 0 replies; 26+ messages in thread
From: Lucas De Marchi @ 2019-11-13 18:58 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 01:45:58PM -0800, Jose Souza wrote:
>Adding pipe D support to DSI transcoder.
>Not adding it for EDP transcoder code paths as only TGL has 4 pipes
>and it do not have a EDP transcoder.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/icl_dsi.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 7 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>index 8eb2d7f29c82..f688207932e0 100644
>--- a/drivers/gpu/drm/i915/display/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>@@ -745,6 +745,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> case PIPE_C:
> tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
> break;
>+ case PIPE_D:
>+ tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
>+ break;
> }
>
> /* enable DDI buffer */
>@@ -1325,6 +1328,9 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> case TRANS_DDI_EDP_INPUT_C_ONOFF:
> *pipe = PIPE_C;
> break;
>+ case TRANS_DDI_EDP_INPUT_D_ONOFF:
>+ *pipe = PIPE_D;
>+ break;
> default:
> DRM_ERROR("Invalid PIPE input\n");
> goto out;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 70459a3d93e3..88d1430a6800 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -9665,6 +9665,7 @@ enum skl_power_gate {
> #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
> #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
> #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
>+#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
> #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
> #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
> REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
>--
>2.24.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-13 18:59 ` Lucas De Marchi
0 siblings, 0 replies; 26+ messages in thread
From: Lucas De Marchi @ 2019-11-13 18:59 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 11:18:37PM +0000, Jose Souza wrote:
>On Thu, 2019-11-07 at 15:10 -0800, Lucas De Marchi wrote:
>> On Thu, Nov 07, 2019 at 10:56:09PM +0000, Jose Souza wrote:
>> > On Thu, 2019-11-07 at 14:44 -0800, Lucas De Marchi wrote:
>> > > On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
>> > > > This register was being enabled after enable TRANS_DDI_FUNC_CTL
>> > > > and
>> > > > PIPECONF/TRANS_CONF while BSpec states that it should be set
>> > > > when
>> > > > enabling TRANS_DDI_FUNC_CTL.
>> > > >
>> > > > BSpec: 49190
>> > >
>> > > not what I read here.
>> > >
>> > > 8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be
>> > > configured.
>> > > Then configure and enable TRANS_DDI_FUNC_CTL.
>> >
>> > We call icl_enable_trans_port_sync() in haswell_crtc_enable() and
>> > then
>> > a few lines later intel_ddi_enable_transcoder_func(), if not do
>> > that
>> > right away was a problem people working in port sync would get this
>> > issue.
>>
>> not what I meant. I meant the spec says to enable TRANS_DDI_FUNC_CTL,
>> do step 8k, and then enable pipe VC payload allocation.
>>
>> We aren't doing step 8k anywhere though, as I noted below.
>
>8k is a VRR step that we don't support yet.
if we ever add it, then this would need to be split again. Anyway, I
think it's ok for now.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>
>>
>> Lucas De Marchi
>>
>> > > 8l. If DisplayPort multistream - Enable pipe VC payload
>> > > allocation in
>> > > TRANS_DDI_FUNC_CTL
>> > >
>> > > But yes, this needs to be done before TRANS_CONF.
>> > >
>> > > > BSpec: 22243
>> > >
>> > > same here. But as long as we don't do step 8k, I think they can
>> > > in
>> > > fact
>> > > be combined.
>> > >
>> > > These cover TGL and ICL only, while the code goes until haswell.
>> > > Are
>> > > you
>> > > sure it's safe for the others?
>> > >
>> >
>> > I had only checked if the register exist since HSW but now I
>> > checked
>> > HSW, BDW and SKL sequence all of then requires this.
>> >
>> > BSpec: 4223
>> > BSpec: 4163
>> > BSpec: 4231
>> >
>> >
>> > > thanks
>> > > Lucas De Marchi
>> > >
>> > > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> > > > ---
>> > > > drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++-----------
>> > > > ----
>> > > > -
>> > > > drivers/gpu/drm/i915/display/intel_display.c | 6 ------
>> > > > 2 files changed, 2 insertions(+), 22 deletions(-)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > > > b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > > > index 398c6f054a6e..3d5fce878600 100644
>> > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > > > @@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct
>> > > > intel_crtc_state *crtc_state,
>> > > > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
>> > > > }
>> > > >
>> > > > -void intel_ddi_set_vc_payload_alloc(const struct
>> > > > intel_crtc_state
>> > > > *crtc_state,
>> > > > - bool state)
>> > > > -{
>> > > > - struct intel_crtc *crtc = to_intel_crtc(crtc_state-
>> > > > >uapi.crtc);
>> > > > - struct drm_i915_private *dev_priv = to_i915(crtc-
>> > > > >base.dev);
>> > > > - enum transcoder cpu_transcoder = crtc_state-
>> > > > >cpu_transcoder;
>> > > > - u32 temp;
>> > > > -
>> > > > - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>> > > > - if (state == true)
>> > > > - temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > > > - else
>> > > > - temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > > > - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
>> > > > -}
>> > > > -
>> > > > /*
>> > > > * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
>> > > > *
>> > > > @@ -1924,6 +1908,8 @@ void
>> > > > intel_ddi_enable_transcoder_func(const
>> > > > struct intel_crtc_state *crtc_state)
>> > > > u32 temp;
>> > > >
>> > > > temp =
>> > > > intel_ddi_transcoder_func_reg_val_get(crtc_state);
>> > > > + if (intel_crtc_has_type(crtc_state,
>> > > > INTEL_OUTPUT_DP_MST))
>> > > > + temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > > > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
>> > > > }
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > > > b/drivers/gpu/drm/i915/display/intel_display.c
>> > > > index 551de2baa569..3b4aea253f8c 100644
>> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > > > @@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct
>> > > > intel_crtc_state *pipe_config,
>> > > > if (pipe_config->has_pch_encoder)
>> > > > lpt_pch_enable(state, pipe_config);
>> > > >
>> > > > - if (intel_crtc_has_type(pipe_config,
>> > > > INTEL_OUTPUT_DP_MST))
>> > > > - intel_ddi_set_vc_payload_alloc(pipe_config,
>> > > > true);
>> > > > -
>> > > > assert_vblank_disabled(crtc);
>> > > > intel_crtc_vblank_on(pipe_config);
>> > > >
>> > > > @@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct
>> > > > intel_crtc_state *old_crtc_state,
>> > > > if (!transcoder_is_dsi(cpu_transcoder))
>> > > > intel_disable_pipe(old_crtc_state);
>> > > >
>> > > > - if (intel_crtc_has_type(old_crtc_state,
>> > > > INTEL_OUTPUT_DP_MST))
>> > > > - intel_ddi_set_vc_payload_alloc(old_crtc_state,
>> > > > false);
>> > > > -
>> > > > if (INTEL_GEN(dev_priv) >= 11)
>> > > > icl_disable_transcoder_port_sync(old_crtc_state
>> > > > );
>> > > >
>> > > > --
>> > > > 2.24.0
>> > > >
>> > > > _______________________________________________
>> > > > Intel-gfx mailing list
>> > > > Intel-gfx@lists.freedesktop.org
>> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier
@ 2019-11-13 18:59 ` Lucas De Marchi
0 siblings, 0 replies; 26+ messages in thread
From: Lucas De Marchi @ 2019-11-13 18:59 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 11:18:37PM +0000, Jose Souza wrote:
>On Thu, 2019-11-07 at 15:10 -0800, Lucas De Marchi wrote:
>> On Thu, Nov 07, 2019 at 10:56:09PM +0000, Jose Souza wrote:
>> > On Thu, 2019-11-07 at 14:44 -0800, Lucas De Marchi wrote:
>> > > On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
>> > > > This register was being enabled after enable TRANS_DDI_FUNC_CTL
>> > > > and
>> > > > PIPECONF/TRANS_CONF while BSpec states that it should be set
>> > > > when
>> > > > enabling TRANS_DDI_FUNC_CTL.
>> > > >
>> > > > BSpec: 49190
>> > >
>> > > not what I read here.
>> > >
>> > > 8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be
>> > > configured.
>> > > Then configure and enable TRANS_DDI_FUNC_CTL.
>> >
>> > We call icl_enable_trans_port_sync() in haswell_crtc_enable() and
>> > then
>> > a few lines later intel_ddi_enable_transcoder_func(), if not do
>> > that
>> > right away was a problem people working in port sync would get this
>> > issue.
>>
>> not what I meant. I meant the spec says to enable TRANS_DDI_FUNC_CTL,
>> do step 8k, and then enable pipe VC payload allocation.
>>
>> We aren't doing step 8k anywhere though, as I noted below.
>
>8k is a VRR step that we don't support yet.
if we ever add it, then this would need to be split again. Anyway, I
think it's ok for now.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>
>>
>> Lucas De Marchi
>>
>> > > 8l. If DisplayPort multistream - Enable pipe VC payload
>> > > allocation in
>> > > TRANS_DDI_FUNC_CTL
>> > >
>> > > But yes, this needs to be done before TRANS_CONF.
>> > >
>> > > > BSpec: 22243
>> > >
>> > > same here. But as long as we don't do step 8k, I think they can
>> > > in
>> > > fact
>> > > be combined.
>> > >
>> > > These cover TGL and ICL only, while the code goes until haswell.
>> > > Are
>> > > you
>> > > sure it's safe for the others?
>> > >
>> >
>> > I had only checked if the register exist since HSW but now I
>> > checked
>> > HSW, BDW and SKL sequence all of then requires this.
>> >
>> > BSpec: 4223
>> > BSpec: 4163
>> > BSpec: 4231
>> >
>> >
>> > > thanks
>> > > Lucas De Marchi
>> > >
>> > > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> > > > ---
>> > > > drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++-----------
>> > > > ----
>> > > > -
>> > > > drivers/gpu/drm/i915/display/intel_display.c | 6 ------
>> > > > 2 files changed, 2 insertions(+), 22 deletions(-)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > > > b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > > > index 398c6f054a6e..3d5fce878600 100644
>> > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > > > @@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct
>> > > > intel_crtc_state *crtc_state,
>> > > > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
>> > > > }
>> > > >
>> > > > -void intel_ddi_set_vc_payload_alloc(const struct
>> > > > intel_crtc_state
>> > > > *crtc_state,
>> > > > - bool state)
>> > > > -{
>> > > > - struct intel_crtc *crtc = to_intel_crtc(crtc_state-
>> > > > >uapi.crtc);
>> > > > - struct drm_i915_private *dev_priv = to_i915(crtc-
>> > > > >base.dev);
>> > > > - enum transcoder cpu_transcoder = crtc_state-
>> > > > >cpu_transcoder;
>> > > > - u32 temp;
>> > > > -
>> > > > - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>> > > > - if (state == true)
>> > > > - temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > > > - else
>> > > > - temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > > > - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
>> > > > -}
>> > > > -
>> > > > /*
>> > > > * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
>> > > > *
>> > > > @@ -1924,6 +1908,8 @@ void
>> > > > intel_ddi_enable_transcoder_func(const
>> > > > struct intel_crtc_state *crtc_state)
>> > > > u32 temp;
>> > > >
>> > > > temp =
>> > > > intel_ddi_transcoder_func_reg_val_get(crtc_state);
>> > > > + if (intel_crtc_has_type(crtc_state,
>> > > > INTEL_OUTPUT_DP_MST))
>> > > > + temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>> > > > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
>> > > > }
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > > > b/drivers/gpu/drm/i915/display/intel_display.c
>> > > > index 551de2baa569..3b4aea253f8c 100644
>> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > > > @@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct
>> > > > intel_crtc_state *pipe_config,
>> > > > if (pipe_config->has_pch_encoder)
>> > > > lpt_pch_enable(state, pipe_config);
>> > > >
>> > > > - if (intel_crtc_has_type(pipe_config,
>> > > > INTEL_OUTPUT_DP_MST))
>> > > > - intel_ddi_set_vc_payload_alloc(pipe_config,
>> > > > true);
>> > > > -
>> > > > assert_vblank_disabled(crtc);
>> > > > intel_crtc_vblank_on(pipe_config);
>> > > >
>> > > > @@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct
>> > > > intel_crtc_state *old_crtc_state,
>> > > > if (!transcoder_is_dsi(cpu_transcoder))
>> > > > intel_disable_pipe(old_crtc_state);
>> > > >
>> > > > - if (intel_crtc_has_type(old_crtc_state,
>> > > > INTEL_OUTPUT_DP_MST))
>> > > > - intel_ddi_set_vc_payload_alloc(old_crtc_state,
>> > > > false);
>> > > > -
>> > > > if (INTEL_GEN(dev_priv) >= 11)
>> > > > icl_disable_transcoder_port_sync(old_crtc_state
>> > > > );
>> > > >
>> > > > --
>> > > > 2.24.0
>> > > >
>> > > > _______________________________________________
>> > > > Intel-gfx mailing list
>> > > > Intel-gfx@lists.freedesktop.org
>> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
@ 2019-11-13 21:13 ` Souza, Jose
0 siblings, 0 replies; 26+ messages in thread
From: Souza, Jose @ 2019-11-13 21:13 UTC (permalink / raw)
To: intel-gfx
On Sat, 2019-11-09 at 10:47 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/3] drm/i915/display: Fix
> TRANS_DDI_MST_TRANSPORT_SELECT definition
> URL : https://patchwork.freedesktop.org/series/69160/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7290_full -> Patchwork_15187_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
Pushed to dinq, thanks for the reviews Lucas.
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_15187_full that come from
> known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_ctx_isolation@bcs0-s3:
> - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566])
> +3 similar issues
> [1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-apl2/igt@gem_ctx_isolation@bcs0-s3.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html
>
> * igt@gem_ctx_isolation@vcs1-dirty-create:
> - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] /
> [fdo#112080]) +1 similar issue
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html
>
> * igt@gem_ctx_isolation@vcs1-s3:
> - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([fdo#111832])
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@gem_ctx_isolation@vcs1-s3.html
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@gem_ctx_isolation@vcs1-s3.html
>
> * igt@gem_ctx_switch@vcs1-heavy:
> - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +3
> similar issues
> [7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@gem_ctx_switch@vcs1-heavy.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_ctx_switch@vcs1-heavy.html
>
> * igt@gem_eio@suspend:
> - shard-tglb: [PASS][9] -> [INCOMPLETE][10]
> ([fdo#111850])
> [9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb3/igt@gem_eio@suspend.html
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb3/igt@gem_eio@suspend.html
>
> * igt@gem_eio@unwedge-stress:
> - shard-snb: [PASS][11] -> [FAIL][12] ([fdo#109661])
> [11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb6/igt@gem_eio@unwedge-stress.html
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb1/igt@gem_eio@unwedge-stress.html
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#110854])
> [13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_balancer@smoke.html
> [14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_exec_balancer@smoke.html
>
> * igt@gem_exec_nop@basic-parallel:
> - shard-tglb: [PASS][15] -> [INCOMPLETE][16]
> ([fdo#111747])
> [15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@gem_exec_nop@basic-parallel.html
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb7/igt@gem_exec_nop@basic-parallel.html
>
> * igt@gem_exec_schedule@preempt-queue-bsd1:
> - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109276]) +9
> similar issues
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
> [18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd1.html
>
> * igt@gem_exec_schedule@preemptive-hang-bsd:
> - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#112146]) +4
> similar issues
> [19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb7/igt@gem_exec_schedule@preemptive-hang-bsd.html
> [20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
>
> * igt@gem_sync@basic-all:
> - shard-kbl: [PASS][21] -> [DMESG-WARN][22]
> ([fdo#103558] / [fdo#105602]) +2 similar issues
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl7/igt@gem_sync@basic-all.html
> [22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl2/igt@gem_sync@basic-all.html
>
> * igt@gem_userptr_blits@dmabuf-unsync:
> - shard-snb: [PASS][23] -> [DMESG-WARN][24]
> ([fdo#111870])
> [23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
> [24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb5/igt@gem_userptr_blits@dmabuf-unsync.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-busy:
> - shard-hsw: [PASS][25] -> [DMESG-WARN][26]
> ([fdo#111870])
> [25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
> [26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
> - shard-snb: [PASS][27] -> [DMESG-WARN][28]
> ([fdo#110789] / [fdo#111870])
> [27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
> [28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
>
> * igt@gem_workarounds@suspend-resume-context:
> - shard-tglb: [PASS][29] -> [INCOMPLETE][30]
> ([fdo#111832] / [fdo#111850]) +1 similar issue
> [29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@gem_workarounds@suspend-resume-context.html
> [30]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb1/igt@gem_workarounds@suspend-resume-context.html
>
> * igt@i915_selftest@live_hangcheck:
> - shard-hsw: [PASS][31] -> [DMESG-FAIL][32]
> ([fdo#111991])
> [31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw2/igt@i915_selftest@live_hangcheck.html
> [32]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw1/igt@i915_selftest@live_hangcheck.html
>
> * igt@kms_fbcon_fbt@fbc-suspend:
> - shard-tglb: [PASS][33] -> [INCOMPLETE][34]
> ([fdo#111747] / [fdo#111832] / [fdo#111850])
> [33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb9/igt@kms_fbcon_fbt@fbc-suspend.html
> [34]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html
>
> * igt@kms
> _frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
> - shard-tglb: [PASS][35] -> [FAIL][36] ([fdo#103167]) +6
> similar issues
> [35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
> [36]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
>
> * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
> - shard-iclb: [PASS][37] -> [FAIL][38] ([fdo#103167]) +4
> similar issues
> [37]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
> [38]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> - shard-skl: [PASS][39] -> [FAIL][40] ([fdo#103166])
> [39]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> [40]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-iclb: [PASS][41] -> [FAIL][42] ([fdo#103166])
> [41]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
> [42]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_psr@psr2_cursor_mmap_cpu:
> - shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109441]) +3
> similar issues
> [43]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
> [44]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html
>
> * igt@kms_setmode@basic:
> - shard-kbl: [PASS][45] -> [FAIL][46] ([fdo#99912])
> [45]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl2/igt@kms_setmode@basic.html
> [46]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl2/igt@kms_setmode@basic.html
>
> * igt@kms_vblank@pipe-a-ts-continuation-suspend:
> - shard-kbl: [PASS][47] -> [DMESG-WARN][48]
> ([fdo#108566]) +4 similar issues
> [47]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
> [48]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
>
>
> #### Possible fixes ####
>
> * igt@gem_busy@busy-vcs1:
> - shard-iclb: [SKIP][49] ([fdo#112080]) -> [PASS][50] +9
> similar issues
> [49]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb6/igt@gem_busy@busy-vcs1.html
> [50]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@gem_busy@busy-vcs1.html
>
> * igt@gem_ctx_isolation@vecs0-s3:
> - shard-tglb: [INCOMPLETE][51] ([fdo#111832]) ->
> [PASS][52] +1 similar issue
> [51]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@gem_ctx_isolation@vecs0-s3.html
> [52]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb9/igt@gem_ctx_isolation@vecs0-s3.html
>
> * igt@gem_ctx_persistence@vcs1-persistence:
> - shard-iclb: [SKIP][53] ([fdo#109276] / [fdo#112080]) ->
> [PASS][54] +1 similar issue
> [53]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb7/igt@gem_ctx_persistence@vcs1-persistence.html
> [54]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@gem_ctx_persistence@vcs1-persistence.html
>
> * igt@gem_eio@in-flight-suspend:
> - shard-tglb: [INCOMPLETE][55] ([fdo#111832] /
> [fdo#111850] / [fdo#112081]) -> [PASS][56]
> [55]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb7/igt@gem_eio@in-flight-suspend.html
> [56]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb6/igt@gem_eio@in-flight-suspend.html
>
> * igt@gem_exec_nop@basic-series:
> - shard-tglb: [INCOMPLETE][57] ([fdo#111747]) ->
> [PASS][58]
> [57]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb6/igt@gem_exec_nop@basic-series.html
> [58]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb4/igt@gem_exec_nop@basic-series.html
>
> * igt@gem_exec_schedule@preempt-other-chain-bsd:
> - shard-iclb: [SKIP][59] ([fdo#112146]) -> [PASS][60] +3
> similar issues
> [59]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
> [60]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
>
> * igt@gem_exec_schedule@promotion-bsd1:
> - shard-iclb: [SKIP][61] ([fdo#109276]) -> [PASS][62] +14
> similar issues
> [61]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb3/igt@gem_exec_schedule@promotion-bsd1.html
> [62]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html
>
> * igt@gem_exec_schedule@smoketest-blt:
> - shard-tglb: [INCOMPLETE][63] ([fdo#111867]) ->
> [PASS][64]
> [63]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb6/igt@gem_exec_schedule@smoketest-blt.html
> [64]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@gem_exec_schedule@smoketest-blt.html
>
> * igt@gem_mmap_gtt@hang:
> - shard-snb: [INCOMPLETE][65] ([fdo#105411]) ->
> [PASS][66]
> [65]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb2/igt@gem_mmap_gtt@hang.html
> [66]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb5/igt@gem_mmap_gtt@hang.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-busy:
> - shard-snb: [DMESG-WARN][67] ([fdo#110789] /
> [fdo#111870]) -> [PASS][68]
> [67]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
> [68]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
>
> * igt@gem_userptr_blits@sync-unmap-after-close:
> - shard-hsw: [DMESG-WARN][69] ([fdo#111870]) ->
> [PASS][70]
> [69]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@gem_userptr_blits@sync-unmap-after-close.html
> [70]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw5/igt@gem_userptr_blits@sync-unmap-after-close.html
>
> * igt@i915_pm_dc@dc6-psr:
> - shard-iclb: [FAIL][71] ([fdo#110548]) -> [PASS][72]
> [71]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
> [72]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
>
> * igt@i915_pm_rpm@system-suspend-execbuf:
> - shard-tglb: [INCOMPLETE][73] ([fdo#111832] /
> [fdo#111850]) -> [PASS][74]
> [73]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb8/igt@i915_pm_rpm@system-suspend-execbuf.html
> [74]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb4/igt@i915_pm_rpm@system-suspend-execbuf.html
>
> * igt@i915_suspend@fence-restore-tiled2untiled:
> - shard-apl: [DMESG-WARN][75] ([fdo#108566]) ->
> [PASS][76]
> [75]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
> [76]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
>
> * igt@kms_color@pipe-a-gamma:
> - shard-skl: [FAIL][77] ([fdo#104782]) -> [PASS][78]
> [77]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_color@pipe-a-gamma.html
> [78]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_color@pipe-a-gamma.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen:
> - shard-skl: [FAIL][79] ([fdo#103232]) -> [PASS][80]
> [79]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
> [80]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-suspend:
> - shard-kbl: [DMESG-WARN][81] ([fdo#108566]) ->
> [PASS][82] +3 similar issues
> [81]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> [82]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> - shard-skl: [INCOMPLETE][83] ([fdo#110741]) ->
> [PASS][84]
> [83]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> [84]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
>
> * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
> - shard-skl: [FAIL][85] ([fdo#103184] / [fdo#103232]) ->
> [PASS][86] +1 similar issue
> [85]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
> [86]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-skl: [FAIL][87] ([fdo#105363]) -> [PASS][88]
> [87]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
> [88]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
>
> * igt@kms_flip@flip-vs-suspend:
> - shard-hsw: [INCOMPLETE][89] ([fdo#103540]) ->
> [PASS][90]
> [89]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@kms_flip@flip-vs-suspend.html
> [90]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw5/igt@kms_flip@flip-vs-suspend.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-tglb: [INCOMPLETE][91] ([fdo#111832] /
> [fdo#111850] / [fdo#112031]) -> [PASS][92]
> [91]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@kms_flip@flip-vs-suspend-interruptible.html
> [92]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb6/igt@kms_flip@flip-vs-suspend-interruptible.html
>
> * igt@kms
> _frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
> - shard-iclb: [FAIL][93] ([fdo#103167]) -> [PASS][94] +4
> similar issues
> [93]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
> [94]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-rte:
> - shard-iclb: [FAIL][95] ([fdo#103167] / [fdo#110378]) ->
> [PASS][96]
> [95]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
> [96]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
> - shard-tglb: [FAIL][97] ([fdo#103167]) -> [PASS][98] +4
> similar issues
> [97]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
> [98]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
> - shard-skl: [FAIL][99] ([fdo#103167]) -> [PASS][100]
> [99]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
> [100]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
>
> * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
> - shard-skl: [FAIL][101] ([fdo#103191]) -> [PASS][102]
> [101]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
> [102]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [FAIL][103] ([fdo#108145] / [fdo#110403])
> -> [PASS][104]
> [103]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [104]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_psr2_su@page_flip:
> - shard-iclb: [SKIP][105] ([fdo#109642] / [fdo#111068])
> -> [PASS][106]
> [105]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb5/igt@kms_psr2_su@page_flip.html
> [106]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@kms_psr2_su@page_flip.html
>
> * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
> - shard-tglb: [INCOMPLETE][107] ([fdo#111850]) ->
> [PASS][108]
> [107]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb3/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
> [10
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition
@ 2019-11-13 21:13 ` Souza, Jose
0 siblings, 0 replies; 26+ messages in thread
From: Souza, Jose @ 2019-11-13 21:13 UTC (permalink / raw)
To: intel-gfx
On Sat, 2019-11-09 at 10:47 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/3] drm/i915/display: Fix
> TRANS_DDI_MST_TRANSPORT_SELECT definition
> URL : https://patchwork.freedesktop.org/series/69160/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7290_full -> Patchwork_15187_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
Pushed to dinq, thanks for the reviews Lucas.
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_15187_full that come from
> known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_ctx_isolation@bcs0-s3:
> - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566])
> +3 similar issues
> [1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-apl2/igt@gem_ctx_isolation@bcs0-s3.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html
>
> * igt@gem_ctx_isolation@vcs1-dirty-create:
> - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] /
> [fdo#112080]) +1 similar issue
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html
>
> * igt@gem_ctx_isolation@vcs1-s3:
> - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([fdo#111832])
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@gem_ctx_isolation@vcs1-s3.html
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@gem_ctx_isolation@vcs1-s3.html
>
> * igt@gem_ctx_switch@vcs1-heavy:
> - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +3
> similar issues
> [7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@gem_ctx_switch@vcs1-heavy.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_ctx_switch@vcs1-heavy.html
>
> * igt@gem_eio@suspend:
> - shard-tglb: [PASS][9] -> [INCOMPLETE][10]
> ([fdo#111850])
> [9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb3/igt@gem_eio@suspend.html
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb3/igt@gem_eio@suspend.html
>
> * igt@gem_eio@unwedge-stress:
> - shard-snb: [PASS][11] -> [FAIL][12] ([fdo#109661])
> [11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb6/igt@gem_eio@unwedge-stress.html
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb1/igt@gem_eio@unwedge-stress.html
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#110854])
> [13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_balancer@smoke.html
> [14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_exec_balancer@smoke.html
>
> * igt@gem_exec_nop@basic-parallel:
> - shard-tglb: [PASS][15] -> [INCOMPLETE][16]
> ([fdo#111747])
> [15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@gem_exec_nop@basic-parallel.html
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb7/igt@gem_exec_nop@basic-parallel.html
>
> * igt@gem_exec_schedule@preempt-queue-bsd1:
> - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109276]) +9
> similar issues
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
> [18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd1.html
>
> * igt@gem_exec_schedule@preemptive-hang-bsd:
> - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#112146]) +4
> similar issues
> [19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb7/igt@gem_exec_schedule@preemptive-hang-bsd.html
> [20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
>
> * igt@gem_sync@basic-all:
> - shard-kbl: [PASS][21] -> [DMESG-WARN][22]
> ([fdo#103558] / [fdo#105602]) +2 similar issues
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl7/igt@gem_sync@basic-all.html
> [22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl2/igt@gem_sync@basic-all.html
>
> * igt@gem_userptr_blits@dmabuf-unsync:
> - shard-snb: [PASS][23] -> [DMESG-WARN][24]
> ([fdo#111870])
> [23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
> [24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb5/igt@gem_userptr_blits@dmabuf-unsync.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-busy:
> - shard-hsw: [PASS][25] -> [DMESG-WARN][26]
> ([fdo#111870])
> [25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
> [26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
> - shard-snb: [PASS][27] -> [DMESG-WARN][28]
> ([fdo#110789] / [fdo#111870])
> [27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
> [28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
>
> * igt@gem_workarounds@suspend-resume-context:
> - shard-tglb: [PASS][29] -> [INCOMPLETE][30]
> ([fdo#111832] / [fdo#111850]) +1 similar issue
> [29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@gem_workarounds@suspend-resume-context.html
> [30]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb1/igt@gem_workarounds@suspend-resume-context.html
>
> * igt@i915_selftest@live_hangcheck:
> - shard-hsw: [PASS][31] -> [DMESG-FAIL][32]
> ([fdo#111991])
> [31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw2/igt@i915_selftest@live_hangcheck.html
> [32]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw1/igt@i915_selftest@live_hangcheck.html
>
> * igt@kms_fbcon_fbt@fbc-suspend:
> - shard-tglb: [PASS][33] -> [INCOMPLETE][34]
> ([fdo#111747] / [fdo#111832] / [fdo#111850])
> [33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb9/igt@kms_fbcon_fbt@fbc-suspend.html
> [34]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html
>
> * igt@kms
> _frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
> - shard-tglb: [PASS][35] -> [FAIL][36] ([fdo#103167]) +6
> similar issues
> [35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
> [36]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
>
> * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
> - shard-iclb: [PASS][37] -> [FAIL][38] ([fdo#103167]) +4
> similar issues
> [37]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
> [38]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> - shard-skl: [PASS][39] -> [FAIL][40] ([fdo#103166])
> [39]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> [40]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-iclb: [PASS][41] -> [FAIL][42] ([fdo#103166])
> [41]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
> [42]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_psr@psr2_cursor_mmap_cpu:
> - shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109441]) +3
> similar issues
> [43]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
> [44]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html
>
> * igt@kms_setmode@basic:
> - shard-kbl: [PASS][45] -> [FAIL][46] ([fdo#99912])
> [45]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl2/igt@kms_setmode@basic.html
> [46]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl2/igt@kms_setmode@basic.html
>
> * igt@kms_vblank@pipe-a-ts-continuation-suspend:
> - shard-kbl: [PASS][47] -> [DMESG-WARN][48]
> ([fdo#108566]) +4 similar issues
> [47]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
> [48]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
>
>
> #### Possible fixes ####
>
> * igt@gem_busy@busy-vcs1:
> - shard-iclb: [SKIP][49] ([fdo#112080]) -> [PASS][50] +9
> similar issues
> [49]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb6/igt@gem_busy@busy-vcs1.html
> [50]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@gem_busy@busy-vcs1.html
>
> * igt@gem_ctx_isolation@vecs0-s3:
> - shard-tglb: [INCOMPLETE][51] ([fdo#111832]) ->
> [PASS][52] +1 similar issue
> [51]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@gem_ctx_isolation@vecs0-s3.html
> [52]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb9/igt@gem_ctx_isolation@vecs0-s3.html
>
> * igt@gem_ctx_persistence@vcs1-persistence:
> - shard-iclb: [SKIP][53] ([fdo#109276] / [fdo#112080]) ->
> [PASS][54] +1 similar issue
> [53]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb7/igt@gem_ctx_persistence@vcs1-persistence.html
> [54]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@gem_ctx_persistence@vcs1-persistence.html
>
> * igt@gem_eio@in-flight-suspend:
> - shard-tglb: [INCOMPLETE][55] ([fdo#111832] /
> [fdo#111850] / [fdo#112081]) -> [PASS][56]
> [55]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb7/igt@gem_eio@in-flight-suspend.html
> [56]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb6/igt@gem_eio@in-flight-suspend.html
>
> * igt@gem_exec_nop@basic-series:
> - shard-tglb: [INCOMPLETE][57] ([fdo#111747]) ->
> [PASS][58]
> [57]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb6/igt@gem_exec_nop@basic-series.html
> [58]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb4/igt@gem_exec_nop@basic-series.html
>
> * igt@gem_exec_schedule@preempt-other-chain-bsd:
> - shard-iclb: [SKIP][59] ([fdo#112146]) -> [PASS][60] +3
> similar issues
> [59]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
> [60]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
>
> * igt@gem_exec_schedule@promotion-bsd1:
> - shard-iclb: [SKIP][61] ([fdo#109276]) -> [PASS][62] +14
> similar issues
> [61]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb3/igt@gem_exec_schedule@promotion-bsd1.html
> [62]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html
>
> * igt@gem_exec_schedule@smoketest-blt:
> - shard-tglb: [INCOMPLETE][63] ([fdo#111867]) ->
> [PASS][64]
> [63]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb6/igt@gem_exec_schedule@smoketest-blt.html
> [64]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@gem_exec_schedule@smoketest-blt.html
>
> * igt@gem_mmap_gtt@hang:
> - shard-snb: [INCOMPLETE][65] ([fdo#105411]) ->
> [PASS][66]
> [65]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb2/igt@gem_mmap_gtt@hang.html
> [66]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb5/igt@gem_mmap_gtt@hang.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-busy:
> - shard-snb: [DMESG-WARN][67] ([fdo#110789] /
> [fdo#111870]) -> [PASS][68]
> [67]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
> [68]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
>
> * igt@gem_userptr_blits@sync-unmap-after-close:
> - shard-hsw: [DMESG-WARN][69] ([fdo#111870]) ->
> [PASS][70]
> [69]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@gem_userptr_blits@sync-unmap-after-close.html
> [70]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw5/igt@gem_userptr_blits@sync-unmap-after-close.html
>
> * igt@i915_pm_dc@dc6-psr:
> - shard-iclb: [FAIL][71] ([fdo#110548]) -> [PASS][72]
> [71]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
> [72]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
>
> * igt@i915_pm_rpm@system-suspend-execbuf:
> - shard-tglb: [INCOMPLETE][73] ([fdo#111832] /
> [fdo#111850]) -> [PASS][74]
> [73]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb8/igt@i915_pm_rpm@system-suspend-execbuf.html
> [74]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb4/igt@i915_pm_rpm@system-suspend-execbuf.html
>
> * igt@i915_suspend@fence-restore-tiled2untiled:
> - shard-apl: [DMESG-WARN][75] ([fdo#108566]) ->
> [PASS][76]
> [75]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
> [76]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
>
> * igt@kms_color@pipe-a-gamma:
> - shard-skl: [FAIL][77] ([fdo#104782]) -> [PASS][78]
> [77]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_color@pipe-a-gamma.html
> [78]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_color@pipe-a-gamma.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen:
> - shard-skl: [FAIL][79] ([fdo#103232]) -> [PASS][80]
> [79]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
> [80]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-suspend:
> - shard-kbl: [DMESG-WARN][81] ([fdo#108566]) ->
> [PASS][82] +3 similar issues
> [81]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> [82]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> - shard-skl: [INCOMPLETE][83] ([fdo#110741]) ->
> [PASS][84]
> [83]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> [84]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
>
> * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
> - shard-skl: [FAIL][85] ([fdo#103184] / [fdo#103232]) ->
> [PASS][86] +1 similar issue
> [85]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
> [86]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-skl: [FAIL][87] ([fdo#105363]) -> [PASS][88]
> [87]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
> [88]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
>
> * igt@kms_flip@flip-vs-suspend:
> - shard-hsw: [INCOMPLETE][89] ([fdo#103540]) ->
> [PASS][90]
> [89]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-hsw6/igt@kms_flip@flip-vs-suspend.html
> [90]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-hsw5/igt@kms_flip@flip-vs-suspend.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-tglb: [INCOMPLETE][91] ([fdo#111832] /
> [fdo#111850] / [fdo#112031]) -> [PASS][92]
> [91]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@kms_flip@flip-vs-suspend-interruptible.html
> [92]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb6/igt@kms_flip@flip-vs-suspend-interruptible.html
>
> * igt@kms
> _frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
> - shard-iclb: [FAIL][93] ([fdo#103167]) -> [PASS][94] +4
> similar issues
> [93]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
> [94]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-rte:
> - shard-iclb: [FAIL][95] ([fdo#103167] / [fdo#110378]) ->
> [PASS][96]
> [95]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
> [96]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
> - shard-tglb: [FAIL][97] ([fdo#103167]) -> [PASS][98] +4
> similar issues
> [97]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
> [98]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
> - shard-skl: [FAIL][99] ([fdo#103167]) -> [PASS][100]
> [99]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
> [100]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
>
> * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
> - shard-skl: [FAIL][101] ([fdo#103191]) -> [PASS][102]
> [101]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl5/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
> [102]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl8/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [FAIL][103] ([fdo#108145] / [fdo#110403])
> -> [PASS][104]
> [103]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [104]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_psr2_su@page_flip:
> - shard-iclb: [SKIP][105] ([fdo#109642] / [fdo#111068])
> -> [PASS][106]
> [105]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-iclb5/igt@kms_psr2_su@page_flip.html
> [106]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/shard-iclb2/igt@kms_psr2_su@page_flip.html
>
> * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
> - shard-tglb: [INCOMPLETE][107] ([fdo#111850]) ->
> [PASS][108]
> [107]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/shard-tglb3/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
> [10
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2019-11-13 21:13 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-07 21:45 [PATCH 1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition José Roberto de Souza
2019-11-07 21:45 ` [Intel-gfx] " José Roberto de Souza
2019-11-07 21:45 ` [PATCH 2/3] drm/i915/display/dsi: Add support to pipe D José Roberto de Souza
2019-11-07 21:45 ` [Intel-gfx] " José Roberto de Souza
2019-11-13 18:58 ` Lucas De Marchi
2019-11-13 18:58 ` [Intel-gfx] " Lucas De Marchi
2019-11-07 21:45 ` [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier José Roberto de Souza
2019-11-07 21:45 ` [Intel-gfx] " José Roberto de Souza
2019-11-07 22:44 ` Lucas De Marchi
2019-11-07 22:44 ` [Intel-gfx] " Lucas De Marchi
2019-11-07 22:56 ` Souza, Jose
2019-11-07 22:56 ` [Intel-gfx] " Souza, Jose
2019-11-07 23:10 ` Lucas De Marchi
2019-11-07 23:10 ` [Intel-gfx] " Lucas De Marchi
2019-11-07 23:18 ` Souza, Jose
2019-11-07 23:18 ` [Intel-gfx] " Souza, Jose
2019-11-13 18:59 ` Lucas De Marchi
2019-11-13 18:59 ` [Intel-gfx] " Lucas De Marchi
2019-11-07 22:29 ` [PATCH 1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition Lucas De Marchi
2019-11-07 22:29 ` [Intel-gfx] " Lucas De Marchi
2019-11-08 1:14 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
2019-11-08 1:14 ` [Intel-gfx] " Patchwork
2019-11-09 10:47 ` ✓ Fi.CI.IGT: " Patchwork
2019-11-09 10:47 ` [Intel-gfx] " Patchwork
2019-11-13 21:13 ` Souza, Jose
2019-11-13 21:13 ` [Intel-gfx] " Souza, Jose
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