From: "Z.q. Hou" <zhiqiang.hou@nxp.com> To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "bhelgaas@google.com" <bhelgaas@google.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "arnd@arndb.de" <arnd@arndb.de>, "mark.rutland@arm.com" <mark.rutland@arm.com>, "l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>, "shawnguo@kernel.org" <shawnguo@kernel.org>, "m.karthikeyan@mobiveil.co.in" <m.karthikeyan@mobiveil.co.in>, Leo Li <leoyang.li@nxp.com>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "catalin.marinas@arm.com" <catalin.marinas@arm.com>, "will.deacon@arm.com" <will.deacon@arm.com>, "andrew.murray@arm.com" <andrew.murray@arm.com> Cc: Mingkai Hu <mingkai.hu@nxp.com>, "M.h. Lian" <minghuan.lian@nxp.com>, Xiaowei Bao <xiaowei.bao@nxp.com>, "Z.q. Hou" <zhiqiang.hou@nxp.com> Subject: [PATCHv9 03/12] PCI: mobiveil: Collect the interrupt related operations into a routine Date: Wed, 20 Nov 2019 03:45:37 +0000 [thread overview] Message-ID: <20191120034451.30102-4-Zhiqiang.Hou@nxp.com> (raw) In-Reply-To: <20191120034451.30102-1-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Collect the interrupt initialization related operations into a new routine to make it more readable. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> --- V9: - New patch splited from the #1 of V8 patches to make it easy to review. drivers/pci/controller/pcie-mobiveil.c | 65 +++++++++++++++++--------- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 97f682ca7c7a..512b27a0536e 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -454,12 +454,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) return PTR_ERR(pcie->csr_axi_slave_base); pcie->pcie_reg_base = res->start; - /* map MSI config resource */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); - pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pcie->apb_csr_base)) - return PTR_ERR(pcie->apb_csr_base); - /* read the number of windows requested */ if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) pcie->apio_wins = MAX_PIO_WINDOWS; @@ -467,12 +461,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) pcie->ppio_wins = MAX_PIO_WINDOWS; - rp->irq = platform_get_irq(pdev, 0); - if (rp->irq <= 0) { - dev_err(dev, "failed to map IRQ: %d\n", rp->irq); - return -ENODEV; - } - return 0; } @@ -618,9 +606,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT); mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL); - mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), - PAB_INTP_AMBA_MISC_ENB); - /* * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in * PAB_AXI_PIO_CTRL Register @@ -670,9 +655,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) value |= (PCI_CLASS_BRIDGE_PCI << 16); mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); - /* setup MSI hardware registers */ - mobiveil_pcie_enable_msi(pcie); - return 0; } @@ -873,6 +855,46 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) return 0; } +static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie) +{ + struct platform_device *pdev = pcie->pdev; + struct device *dev = &pdev->dev; + struct root_port *rp = &pcie->rp; + struct resource *res; + int ret; + + /* map MSI config resource */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); + pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pcie->apb_csr_base)) + return PTR_ERR(pcie->apb_csr_base); + + /* setup MSI hardware registers */ + mobiveil_pcie_enable_msi(pcie); + + rp->irq = platform_get_irq(pdev, 0); + if (rp->irq <= 0) { + dev_err(dev, "failed to map IRQ: %d\n", rp->irq); + return -ENODEV; + } + + /* initialize the IRQ domains */ + ret = mobiveil_pcie_init_irq_domain(pcie); + if (ret) { + dev_err(dev, "Failed creating IRQ Domain\n"); + return ret; + } + + irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); + + /* Enable interrupts */ + mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), + PAB_INTP_AMBA_MISC_ENB); + + + return 0; +} + int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) { struct root_port *rp = &pcie->rp; @@ -906,15 +928,12 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) return ret; } - /* initialize the IRQ domains */ - ret = mobiveil_pcie_init_irq_domain(pcie); + ret = mobiveil_pcie_interrupt_init(pcie); if (ret) { - dev_err(dev, "Failed creating IRQ Domain\n"); + dev_err(dev, "Interrupt init failed\n"); return ret; } - irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); - /* Initialize bridge */ bridge->dev.parent = dev; bridge->sysdata = pcie; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: "Z.q. Hou" <zhiqiang.hou@nxp.com> To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "bhelgaas@google.com" <bhelgaas@google.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "arnd@arndb.de" <arnd@arndb.de>, "mark.rutland@arm.com" <mark.rutland@arm.com>, "l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>, "shawnguo@kernel.org" <shawnguo@kernel.org>, "m.karthikeyan@mobiveil.co.in" <m.karthikeyan@mobiveil.co.in>, Leo Li <leoyang.li@nxp.com>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "catalin.marinas@arm.com" <catalin.marinas@arm.com>, "will.deacon@arm.com" <will.deacon@arm.com>, "andrew.murray@arm.com" <andrew.murray@arm.com> Cc: "M.h. Lian" <minghuan.lian@nxp.com>, "Z.q. Hou" <zhiqiang.hou@nxp.com>, Xiaowei Bao <xiaowei.bao@nxp.com>, Mingkai Hu <mingkai.hu@nxp.com> Subject: [PATCHv9 03/12] PCI: mobiveil: Collect the interrupt related operations into a routine Date: Wed, 20 Nov 2019 03:45:37 +0000 [thread overview] Message-ID: <20191120034451.30102-4-Zhiqiang.Hou@nxp.com> (raw) In-Reply-To: <20191120034451.30102-1-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Collect the interrupt initialization related operations into a new routine to make it more readable. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> --- V9: - New patch splited from the #1 of V8 patches to make it easy to review. drivers/pci/controller/pcie-mobiveil.c | 65 +++++++++++++++++--------- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 97f682ca7c7a..512b27a0536e 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -454,12 +454,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) return PTR_ERR(pcie->csr_axi_slave_base); pcie->pcie_reg_base = res->start; - /* map MSI config resource */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); - pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pcie->apb_csr_base)) - return PTR_ERR(pcie->apb_csr_base); - /* read the number of windows requested */ if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) pcie->apio_wins = MAX_PIO_WINDOWS; @@ -467,12 +461,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) pcie->ppio_wins = MAX_PIO_WINDOWS; - rp->irq = platform_get_irq(pdev, 0); - if (rp->irq <= 0) { - dev_err(dev, "failed to map IRQ: %d\n", rp->irq); - return -ENODEV; - } - return 0; } @@ -618,9 +606,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT); mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL); - mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), - PAB_INTP_AMBA_MISC_ENB); - /* * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in * PAB_AXI_PIO_CTRL Register @@ -670,9 +655,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) value |= (PCI_CLASS_BRIDGE_PCI << 16); mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); - /* setup MSI hardware registers */ - mobiveil_pcie_enable_msi(pcie); - return 0; } @@ -873,6 +855,46 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) return 0; } +static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie) +{ + struct platform_device *pdev = pcie->pdev; + struct device *dev = &pdev->dev; + struct root_port *rp = &pcie->rp; + struct resource *res; + int ret; + + /* map MSI config resource */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); + pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pcie->apb_csr_base)) + return PTR_ERR(pcie->apb_csr_base); + + /* setup MSI hardware registers */ + mobiveil_pcie_enable_msi(pcie); + + rp->irq = platform_get_irq(pdev, 0); + if (rp->irq <= 0) { + dev_err(dev, "failed to map IRQ: %d\n", rp->irq); + return -ENODEV; + } + + /* initialize the IRQ domains */ + ret = mobiveil_pcie_init_irq_domain(pcie); + if (ret) { + dev_err(dev, "Failed creating IRQ Domain\n"); + return ret; + } + + irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); + + /* Enable interrupts */ + mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), + PAB_INTP_AMBA_MISC_ENB); + + + return 0; +} + int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) { struct root_port *rp = &pcie->rp; @@ -906,15 +928,12 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) return ret; } - /* initialize the IRQ domains */ - ret = mobiveil_pcie_init_irq_domain(pcie); + ret = mobiveil_pcie_interrupt_init(pcie); if (ret) { - dev_err(dev, "Failed creating IRQ Domain\n"); + dev_err(dev, "Interrupt init failed\n"); return ret; } - irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); - /* Initialize bridge */ bridge->dev.parent = dev; bridge->sysdata = pcie; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-20 3:45 UTC|newest] Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-20 3:45 [PATCHv9 00/12] PCI: Recode Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou 2019-11-20 3:45 ` Z.q. Hou 2019-11-20 3:45 ` [PATCHv9 01/12] PCI: mobiveil: Re-abstract the private structure Z.q. Hou 2019-11-20 3:45 ` Z.q. Hou 2020-01-13 10:09 ` Andrew Murray 2020-01-13 10:09 ` Andrew Murray 2020-02-06 11:04 ` Z.q. Hou 2020-02-06 11:04 ` Z.q. Hou 2020-02-06 11:27 ` Andrew Murray 2020-02-06 11:27 ` Andrew Murray 2019-11-20 3:45 ` [PATCHv9 02/12] PCI: mobiveil: Move the host initialization into a routine Z.q. Hou 2019-11-20 3:45 ` Z.q. Hou 2020-01-13 10:19 ` Andrew Murray 2020-01-13 10:19 ` Andrew Murray 2020-02-06 11:14 ` Z.q. Hou 2020-02-06 11:14 ` Z.q. Hou 2019-11-20 3:45 ` Z.q. Hou [this message] 2019-11-20 3:45 ` [PATCHv9 03/12] PCI: mobiveil: Collect the interrupt related operations " Z.q. Hou 2020-01-13 10:34 ` Andrew Murray 2020-01-13 10:34 ` Andrew Murray 2020-02-06 11:30 ` Z.q. Hou 2020-02-06 11:30 ` Z.q. Hou 2019-11-20 3:45 ` [PATCHv9 04/12] PCI: mobiveil: Modularize the Mobiveil PCIe Host Bridge IP driver Z.q. Hou 2019-11-20 3:45 ` Z.q. Hou 2020-01-13 11:05 ` Andrew Murray 2020-01-13 11:05 ` Andrew Murray 2020-02-06 12:25 ` Z.q. Hou 2020-02-06 12:25 ` Z.q. Hou 2019-11-20 3:45 ` [PATCHv9 05/12] PCI: mobiveil: Add callback function for interrupt initialization Z.q. Hou 2019-11-20 3:45 ` Z.q. Hou 2020-01-13 11:19 ` Andrew Murray 2020-01-13 11:19 ` Andrew Murray 2020-02-06 13:25 ` Z.q. Hou 2020-02-06 13:25 ` Z.q. Hou 2019-11-20 3:45 ` [PATCHv9 06/12] PCI: mobiveil: Add callback function for link up check Z.q. Hou 2019-11-20 3:45 ` Z.q. Hou 2020-01-13 11:22 ` Andrew Murray 2020-01-13 11:22 ` Andrew Murray 2020-02-06 13:25 ` Z.q. Hou 2020-02-06 13:25 ` Z.q. Hou 2019-11-20 3:46 ` [PATCHv9 07/12] PCI: mobiveil: Make mobiveil_host_init() can be used to re-init host Z.q. Hou 2019-11-20 3:46 ` Z.q. Hou 2020-01-13 11:26 ` Andrew Murray 2020-01-13 11:26 ` Andrew Murray 2020-02-06 13:27 ` Z.q. Hou 2020-02-06 13:27 ` Z.q. Hou 2019-11-20 3:46 ` [PATCHv9 08/12] PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors Z.q. Hou 2019-11-20 3:46 ` Z.q. Hou 2020-01-13 11:31 ` Andrew Murray 2020-01-13 11:31 ` Andrew Murray 2020-02-06 13:45 ` Z.q. Hou 2020-02-06 13:45 ` Z.q. Hou 2019-11-20 3:46 ` [PATCHv9 09/12] dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou 2019-11-20 3:46 ` Z.q. Hou 2019-11-20 3:46 ` [PATCHv9 10/12] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou 2019-11-20 3:46 ` Z.q. Hou 2020-01-13 12:02 ` Andrew Murray 2020-01-13 12:02 ` Andrew Murray 2020-02-06 13:45 ` Z.q. Hou 2020-02-06 13:45 ` Z.q. Hou 2020-02-06 14:29 ` Andrew Murray 2020-02-06 14:29 ` Andrew Murray 2019-11-20 3:46 ` [PATCHv9 11/12] arm64: dts: lx2160a: Add PCIe controller DT nodes Z.q. Hou 2019-11-20 3:46 ` Z.q. Hou 2019-11-20 3:46 ` [PATCHv9 12/12] arm64: defconfig: Enable CONFIG_PCIE_LAYERSCAPE_GEN4 Z.q. Hou 2019-11-20 3:46 ` Z.q. Hou 2019-11-20 9:57 ` [PATCHv9 00/12] PCI: Recode Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Russell King - ARM Linux admin 2019-11-20 9:57 ` Russell King - ARM Linux admin 2019-11-20 10:30 ` Z.q. Hou 2019-11-20 10:30 ` Z.q. Hou 2019-12-13 18:37 ` Olof Johansson 2019-12-13 18:37 ` Olof Johansson 2019-12-17 2:50 ` Z.q. Hou 2019-12-17 2:50 ` Z.q. Hou 2020-01-10 15:33 ` Lorenzo Pieralisi 2020-01-10 15:33 ` Lorenzo Pieralisi 2020-01-10 17:05 ` Olof Johansson 2020-01-10 17:05 ` Olof Johansson 2020-02-06 10:57 ` Z.q. Hou 2020-02-06 10:57 ` Z.q. Hou 2020-02-10 15:12 ` Olof Johansson 2020-02-10 15:12 ` Olof Johansson 2020-02-10 15:22 ` Russell King - ARM Linux admin 2020-02-10 15:22 ` Russell King - ARM Linux admin 2020-02-10 15:28 ` Olof Johansson 2020-02-10 15:28 ` Olof Johansson 2020-02-10 16:15 ` Russell King - ARM Linux admin 2020-02-10 16:15 ` Russell King - ARM Linux admin 2020-02-10 17:20 ` Russell King - ARM Linux admin 2020-02-10 17:20 ` Russell King - ARM Linux admin 2020-02-10 18:33 ` Olof Johansson 2020-02-10 18:33 ` Olof Johansson 2020-02-10 18:41 ` Li Yang 2020-02-10 18:41 ` Li Yang 2020-02-10 19:48 ` Li Yang 2020-02-10 19:48 ` Li Yang 2020-02-11 12:13 ` Laurentiu Tudor 2020-02-11 12:13 ` Laurentiu Tudor 2020-02-11 13:04 ` Robin Murphy 2020-02-11 13:04 ` Robin Murphy 2020-02-11 13:55 ` Laurentiu Tudor 2020-02-11 13:55 ` Laurentiu Tudor 2020-02-11 14:51 ` Robin Murphy 2020-02-11 14:51 ` Robin Murphy 2020-02-11 14:48 ` Olof Johansson 2020-02-11 14:48 ` Olof Johansson 2020-02-11 15:14 ` Laurentiu Tudor 2020-02-11 15:14 ` Laurentiu Tudor 2020-02-29 9:55 ` Russell King - ARM Linux admin 2020-02-29 9:55 ` Russell King - ARM Linux admin 2020-02-29 11:04 ` Russell King - ARM Linux admin 2020-02-29 11:04 ` Russell King - ARM Linux admin 2020-02-29 12:08 ` Russell King - ARM Linux admin 2020-02-29 12:08 ` Russell King - ARM Linux admin 2020-02-29 13:32 ` Russell King - ARM Linux admin 2020-02-29 13:32 ` Russell King - ARM Linux admin 2020-02-29 15:19 ` Theodore Y. Ts'o 2020-02-29 15:19 ` Theodore Y. Ts'o 2020-02-29 17:03 ` Russell King - ARM Linux admin 2020-02-29 17:03 ` Russell King - ARM Linux admin 2020-02-29 18:03 ` Theodore Y. Ts'o 2020-02-29 18:03 ` Theodore Y. Ts'o 2020-06-05 23:53 ` Russell King - ARM Linux admin 2020-06-05 23:53 ` Russell King - ARM Linux admin 2020-06-06 10:19 ` Russell King - ARM Linux admin 2020-06-06 10:19 ` Russell King - ARM Linux admin 2020-02-10 15:33 ` Lorenzo Pieralisi 2020-02-10 15:33 ` Lorenzo Pieralisi
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