From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 746F1C432C0 for ; Mon, 2 Dec 2019 12:20:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 557F82071F for ; Mon, 2 Dec 2019 12:20:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727418AbfLBMUy (ORCPT ); Mon, 2 Dec 2019 07:20:54 -0500 Received: from foss.arm.com ([217.140.110.172]:53728 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727354AbfLBMUy (ORCPT ); Mon, 2 Dec 2019 07:20:54 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EF3FF30E; Mon, 2 Dec 2019 04:20:52 -0800 (PST) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 68CBB3F68E; Mon, 2 Dec 2019 04:20:52 -0800 (PST) Date: Mon, 2 Dec 2019 12:20:50 +0000 From: Andrew Murray To: Nicolas Saenz Julienne Cc: maz@kernel.org, linux-kernel@vger.kernel.org, Lorenzo Pieralisi , Eric Anholt , Stefan Wahren , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com, mbrugger@suse.com, phil@raspberrypi.org, jeremy.linton@arm.com, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, Bjorn Helgaas , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 5/7] PCI: brcmstb: add MSI capability Message-ID: <20191202122050.GA18399@e119886-lin.cambridge.arm.com> References: <20191126091946.7970-1-nsaenzjulienne@suse.de> <20191126091946.7970-6-nsaenzjulienne@suse.de> <20191129154629.GF43905@e119886-lin.cambridge.arm.com> <2820f3fb9abc69d54df0dee1b6233eaf3cb63834.camel@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <2820f3fb9abc69d54df0dee1b6233eaf3cb63834.camel@suse.de> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Dec 02, 2019 at 10:59:36AM +0100, Nicolas Saenz Julienne wrote: > Hi Andrew, > > On Fri, 2019-11-29 at 15:46 +0000, Andrew Murray wrote: > > On Tue, Nov 26, 2019 at 10:19:43AM +0100, Nicolas Saenz Julienne wrote: > > > From: Jim Quinlan > > > > > > This adds MSI support to the Broadcom STB PCIe host controller. The MSI > > > controller is physically located within the PCIe block, however, there > > > is no reason why the MSI controller could not be moved elsewhere in the > > > future. MSIX is not supported by the HW. > > > > > > Since the internal Brcmstb MSI controller is intertwined with the PCIe > > > controller, it is not its own platform device but rather part of the > > > PCIe platform device. > > > > > > Signed-off-by: Jim Quinlan > > > Co-developed-by: Nicolas Saenz Julienne > > > Signed-off-by: Nicolas Saenz Julienne > > > Reviewed-by: Marc Zyngier > > > > > > --- > > > > > > Changes since v2 (kept Marc's Reviewed-by as changes didn't affect irq > > > subsystem stuff or seem petty enough): > > > - Use standard APIs on register operations > > > - Get rid of revision code > > > > Do any RPI4's have a HW revision of less than 33? > > No, IIRC it's actually revision 34. I had left that bit of code in, following > the same train of thought as with the of_data on the device-tree part of the > driver: "It's harmless and should make accomodating other devices easier." It > turned out not to be such a great approach. Lesson's learned. So I decided to > remove it. OK you can add my: Reviewed-by: Andrew Murray Thanks, Andrew Murray > > > > - Update rules to msi_target_addr selection > > > - Remove unwarranted MSI_FLAG_PCI_MSIX > > > - Small cosmetic changes > > > > > > Changes since v1:cuando tenías tu vacaciones? > > > - Move revision code and some registers to this patch > > > - Use PCIE_MSI_IRQ_DOMAIN in Kconfig > > > - Remove redundant register read from ISR > > > - Fail probe on MSI init error > > > - Get rid of msi_internal > > > - Use bitmap family of functions > > > - Use edge triggered setup > > > - Add comment regarding MultiMSI > > > - Simplify compose_msi_msg to avoid reg read > > > > > > This is based on Jim's original submission[1] with some slight changes > > > regarding how pcie->msi_target_addr is decided. > > > > > > [1] https://patchwork.kernel.org/patch/10605955/ > > > > > > drivers/pci/controller/Kconfig | 1 + > > > drivers/pci/controller/pcie-brcmstb.c | 261 +++++++++++++++++++++++++- > > > 2 files changed, 261 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig > > > index 27504f108ee5..918e283bbff1 100644 > > > + > > > +static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg > > > *msg) > > > +{ > > > + struct brcm_msi *msi = irq_data_get_irq_chip_data(data); > > > + > > > + msg->address_lo = lower_32_bits(msi->target_addr); > > > + msg->address_hi = upper_32_bits(msi->target_addr); > > > + msg->data = 0x6540 | data->hwirq; > > > > NIT: Perhaps this 0x6540 can be a define - just in the same way we have a > > define > > for PCIE_MISC_MSI_DATA_CONFIG_VAL. > > Noted > > Regards, > Nicolas > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22D91C432C0 for ; Mon, 2 Dec 2019 12:21:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E43E52071F for ; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ibkhJ-0006WU-24; Mon, 02 Dec 2019 12:21:01 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ibkhF-0006VV-QZ; Mon, 02 Dec 2019 12:20:59 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EF3FF30E; Mon, 2 Dec 2019 04:20:52 -0800 (PST) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 68CBB3F68E; Mon, 2 Dec 2019 04:20:52 -0800 (PST) Date: Mon, 2 Dec 2019 12:20:50 +0000 From: Andrew Murray To: Nicolas Saenz Julienne Subject: Re: [PATCH v3 5/7] PCI: brcmstb: add MSI capability Message-ID: <20191202122050.GA18399@e119886-lin.cambridge.arm.com> References: <20191126091946.7970-1-nsaenzjulienne@suse.de> <20191126091946.7970-6-nsaenzjulienne@suse.de> <20191129154629.GF43905@e119886-lin.cambridge.arm.com> <2820f3fb9abc69d54df0dee1b6233eaf3cb63834.camel@suse.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <2820f3fb9abc69d54df0dee1b6233eaf3cb63834.camel@suse.de> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191202_042057_948425_5CDD37D4 X-CRM114-Status: GOOD ( 24.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Florian Fainelli , mbrugger@suse.com, maz@kernel.org, phil@raspberrypi.org, linux-kernel@vger.kernel.org, jeremy.linton@arm.com, Eric Anholt , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, Stefan Wahren , james.quinlan@broadcom.com, linux-pci@vger.kernel.org, Bjorn Helgaas , linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Dec 02, 2019 at 10:59:36AM +0100, Nicolas Saenz Julienne wrote: > Hi Andrew, > = > On Fri, 2019-11-29 at 15:46 +0000, Andrew Murray wrote: > > On Tue, Nov 26, 2019 at 10:19:43AM +0100, Nicolas Saenz Julienne wrote: > > > From: Jim Quinlan > > > = > > > This adds MSI support to the Broadcom STB PCIe host controller. The M= SI > > > controller is physically located within the PCIe block, however, there > > > is no reason why the MSI controller could not be moved elsewhere in t= he > > > future. MSIX is not supported by the HW. > > > = > > > Since the internal Brcmstb MSI controller is intertwined with the PCIe > > > controller, it is not its own platform device but rather part of the > > > PCIe platform device. > > > = > > > Signed-off-by: Jim Quinlan > > > Co-developed-by: Nicolas Saenz Julienne > > > Signed-off-by: Nicolas Saenz Julienne > > > Reviewed-by: Marc Zyngier > > > = > > > --- > > > = > > > Changes since v2 (kept Marc's Reviewed-by as changes didn't affect irq > > > subsystem stuff or seem petty enough): > > > - Use standard APIs on register operations > > > - Get rid of revision code > > = > > Do any RPI4's have a HW revision of less than 33? > = > No, IIRC it's actually revision 34. I had left that bit of code in, follo= wing > the same train of thought as with the of_data on the device-tree part of = the > driver: "It's harmless and should make accomodating other devices easier.= " It > turned out not to be such a great approach. Lesson's learned. So I decide= d to > remove it. OK you can add my: Reviewed-by: Andrew Murray Thanks, Andrew Murray > = > > > - Update rules to msi_target_addr selection > > > - Remove unwarranted MSI_FLAG_PCI_MSIX > > > - Small cosmetic changes > > > = > > > Changes since v1:cuando ten=EDas tu vacaciones? > > > - Move revision code and some registers to this patch > > > - Use PCIE_MSI_IRQ_DOMAIN in Kconfig > > > - Remove redundant register read from ISR > > > - Fail probe on MSI init error > > > - Get rid of msi_internal > > > - Use bitmap family of functions > > > - Use edge triggered setup > > > - Add comment regarding MultiMSI > > > - Simplify compose_msi_msg to avoid reg read > > > = > > > This is based on Jim's original submission[1] with some slight changes > > > regarding how pcie->msi_target_addr is decided. > > > = > > > [1] https://patchwork.kernel.org/patch/10605955/ > > > = > > > drivers/pci/controller/Kconfig | 1 + > > > drivers/pci/controller/pcie-brcmstb.c | 261 ++++++++++++++++++++++++= +- > > > 2 files changed, 261 insertions(+), 1 deletion(-) > > > = > > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/= Kconfig > > > index 27504f108ee5..918e283bbff1 100644 > > > + > > > +static void brcm_msi_compose_msi_msg(struct irq_data *data, struct m= si_msg > > > *msg) > > > +{ > > > + struct brcm_msi *msi =3D irq_data_get_irq_chip_data(data); > > > + > > > + msg->address_lo =3D lower_32_bits(msi->target_addr); > > > + msg->address_hi =3D upper_32_bits(msi->target_addr); > > > + msg->data =3D 0x6540 | data->hwirq; > > = > > NIT: Perhaps this 0x6540 can be a define - just in the same way we have= a > > define > > for PCIE_MISC_MSI_DATA_CONFIG_VAL. > = > Noted > = > Regards, > Nicolas > = _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel