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Tue, 3 Dec 2019 14:50:01 +0000 From: To: , , , CC: , , Subject: [PATCH v2] mtd: spi-nor: Fix the writing of the Status Register on micron flashes Thread-Topic: [PATCH v2] mtd: spi-nor: Fix the writing of the Status Register on micron flashes Thread-Index: AQHVqejwCl518Aw3q0SW+i9wp+8yiw== Date: Tue, 3 Dec 2019 14:50:01 +0000 Message-ID: <20191203144948.15137-1-tudor.ambarus@microchip.com> References: <20191203141625.13839-1-tudor.ambarus@microchip.com> In-Reply-To: <20191203141625.13839-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM0PR01CA0123.eurprd01.prod.exchangelabs.com (2603:10a6:208:168::28) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.14.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e33acfd2-2efd-42aa-1a9f-08d778001300 x-ms-traffictypediagnostic: MN2PR11MB4383: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:820; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: e33acfd2-2efd-42aa-1a9f-08d778001300 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Dec 2019 14:50:01.3489 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: nYnzCqCqv/YV+H/m/9g8Beu1/xC7N0fM6FjJ6XQoJrb8LpuXxd7JVHO3fzxssovpvWwRDk4bg0vsdN3yh9z4XRAL+43sSHZtSy78UK7Pqw4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4383 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Micron flashes do not support 16 bit writes on the Status Register. According to micron datasheets, when using the Write Status Register (01h) command, the chip select should be driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. If CS is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. This fixes the lock operations on micron flashes. Reported-by: John Garry Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock= ()") Signed-off-by: Tudor Ambarus --- v2: reword commit subject drivers/mtd/spi-nor/spi-nor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index f1490c7b5cb9..7e41493f69d8 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -4607,6 +4607,7 @@ static void sst_set_default_init(struct spi_nor *nor) static void st_micron_set_default_init(struct spi_nor *nor) { nor->flags |=3D SNOR_F_HAS_LOCK; + nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; nor->params.quad_enable =3D NULL; nor->params.set_4byte =3D st_micron_set_4byte; } --=20 2.14.5 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, PDS_BTC_ID,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3058DC432C0 for ; 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Tue, 3 Dec 2019 14:50:01 +0000 From: To: , , , Subject: [PATCH v2] mtd: spi-nor: Fix the writing of the Status Register on micron flashes Thread-Topic: [PATCH v2] mtd: spi-nor: Fix the writing of the Status Register on micron flashes Thread-Index: AQHVqejwCl518Aw3q0SW+i9wp+8yiw== Date: Tue, 3 Dec 2019 14:50:01 +0000 Message-ID: <20191203144948.15137-1-tudor.ambarus@microchip.com> References: <20191203141625.13839-1-tudor.ambarus@microchip.com> In-Reply-To: <20191203141625.13839-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM0PR01CA0123.eurprd01.prod.exchangelabs.com (2603:10a6:208:168::28) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.14.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e33acfd2-2efd-42aa-1a9f-08d778001300 x-ms-traffictypediagnostic: MN2PR11MB4383: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:820; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org From: Tudor Ambarus Micron flashes do not support 16 bit writes on the Status Register. According to micron datasheets, when using the Write Status Register (01h) command, the chip select should be driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. If CS is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. This fixes the lock operations on micron flashes. Reported-by: John Garry Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()") Signed-off-by: Tudor Ambarus --- v2: reword commit subject drivers/mtd/spi-nor/spi-nor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index f1490c7b5cb9..7e41493f69d8 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -4607,6 +4607,7 @@ static void sst_set_default_init(struct spi_nor *nor) static void st_micron_set_default_init(struct spi_nor *nor) { nor->flags |= SNOR_F_HAS_LOCK; + nor->flags &= ~SNOR_F_HAS_16BIT_SR; nor->params.quad_enable = NULL; nor->params.set_4byte = st_micron_set_4byte; } -- 2.14.5 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/