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From: Matt Roper <matthew.d.roper@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: Define each HBR link rate
Date: Tue, 3 Dec 2019 08:17:50 -0800	[thread overview]
Message-ID: <20191203161750.GL3251369@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20191203023110.488972-1-jose.souza@intel.com>

On Mon, Dec 02, 2019 at 06:31:09PM -0800, José Roberto de Souza wrote:
> This is better than keep those values in the code that you always
> need to check the DP spec to know what level of HBR it is.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

I think there are a bunch of other places where we could use these new
macros too, but that can be done in a followup.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

We might want to add RBR (162000) as well for completeness in the
future.


Matt

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a976606d21c7..914f0cc4d237 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -49,6 +49,10 @@
>  #include "intel_tc.h"
>  #include "intel_vdsc.h"
>  
> +#define HBR_RATE 270000
> +#define HBR2_RATE 540000
> +#define HBR3_RATE 810000
> +
>  struct ddi_buf_trans {
>  	u32 trans1;	/* balance leg enable, de-emph level */
>  	u32 trans2;	/* vref sel, vswing */
> @@ -888,7 +892,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
>  	if (type == INTEL_OUTPUT_HDMI) {
>  		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
>  		return icl_combo_phy_ddi_translations_hdmi;
> -	} else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
> +	} else if (rate > HBR2_RATE && type == INTEL_OUTPUT_EDP) {
>  		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
>  		return icl_combo_phy_ddi_translations_edp_hbr3;
>  	} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> -- 
> 2.24.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

      parent reply	other threads:[~2019-12-03 16:18 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-03  2:31 [PATCH 1/2] drm/i915/dp: Define each HBR link rate José Roberto de Souza
2019-12-03  2:31 ` [Intel-gfx] " José Roberto de Souza
2019-12-03  2:31 ` [PATCH 2/2] drm/i915/dp/tgl+: Update combo phy vswing tables José Roberto de Souza
2019-12-03  2:31   ` [Intel-gfx] " José Roberto de Souza
2019-12-03 13:18   ` Ville Syrjälä
2019-12-03 16:35   ` Matt Roper
2019-12-03  3:09 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: Define each HBR link rate Patchwork
2019-12-03  3:09   ` [Intel-gfx] " Patchwork
2019-12-03  9:08 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
2019-12-03 13:11   ` Ville Syrjälä
2019-12-03 21:48     ` Souza, Jose
2019-12-03 22:01     ` Manasi Navare
2019-12-03  9:21 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
2019-12-03 16:17 ` Matt Roper [this message]

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