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Tue, 3 Dec 2019 17:22:53 +0000 (UTC) Date: Tue, 3 Dec 2019 18:22:51 +0100 From: Cornelia Huck To: Janosch Frank Subject: Re: [PATCH v3 4/4] pc-bios/s390x: Fix reset psw mask Message-ID: <20191203182251.66f3ff6d.cohuck@redhat.com> In-Reply-To: <20191203132813.2734-5-frankja@linux.ibm.com> References: <20191203132813.2734-1-frankja@linux.ibm.com> <20191203132813.2734-5-frankja@linux.ibm.com> Organization: Red Hat GmbH MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: f9n7Q7b0OhCCVvHpJFxwlw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, qemu-s390x@nongnu.org, mihajlov@linux.ibm.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 3 Dec 2019 08:28:13 -0500 Janosch Frank wrote: > We need to set the short psw indication bit in the reset psw, as it is > a short psw. > > fixes: 9629823290 ("pc-bios/s390-ccw: do a subsystem reset before running the guest") s/fixes: 9629823290/Fixes: 962982329029/ > Signed-off-by: Janosch Frank > --- > pc-bios/s390-ccw/jump2ipl.c | 12 +++++++----- > 1 file changed, 7 insertions(+), 5 deletions(-) > > diff --git a/pc-bios/s390-ccw/jump2ipl.c b/pc-bios/s390-ccw/jump2ipl.c > index 266f1502b9..da13c43cc0 100644 > --- a/pc-bios/s390-ccw/jump2ipl.c > +++ b/pc-bios/s390-ccw/jump2ipl.c > @@ -12,11 +12,11 @@ > #define KERN_IMAGE_START 0x010000UL > #define PSW_MASK_64 0x0000000100000000ULL > #define PSW_MASK_32 0x0000000080000000ULL > -#define IPL_PSW_MASK (PSW_MASK_32 | PSW_MASK_64) > +#define PSW_MASK_SHORTPSW 0x0008000000000000ULL > +#define RESET_PSW_MASK (PSW_MASK_SHORTPSW | PSW_MASK_32 | PSW_MASK_64) > > typedef struct ResetInfo { > - uint32_t ipl_mask; > - uint32_t ipl_addr; > + uint64_t ipl_psw; > uint32_t ipl_continue; > } ResetInfo; > > @@ -50,7 +50,9 @@ void jump_to_IPL_code(uint64_t address) > ResetInfo *current = 0; > > save = *current; > - current->ipl_addr = (uint32_t) (uint64_t) &jump_to_IPL_2; > + > + current->ipl_psw = (uint64_t) &jump_to_IPL_2; > + current->ipl_psw |= RESET_PSW_MASK; > current->ipl_continue = address & 0x7fffffff; > > debug_print_int("set IPL addr to", current->ipl_continue); > @@ -82,7 +84,7 @@ void jump_to_low_kernel(void) > } > > /* Trying to get PSW at zero address */ > - if (*((uint64_t *)0) & IPL_PSW_MASK) { > + if (*((uint64_t *)0) & RESET_PSW_MASK) { > jump_to_IPL_code((*((uint64_t *)0)) & 0x7fffffff); > } > Looks sane to me, but would like an ack from bios maintainers. As this is independent of the other patches (which depend on a headers update), I can pick this and do a rebuild of the bios(es). Unless one of the bios maintainers wants to do that and send me a pull req :), but that seems like overkill.