From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 272DFC432C0 for ; Tue, 3 Dec 2019 22:58:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF9212053B for ; Tue, 3 Dec 2019 22:58:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1575413917; bh=KdwJcVLx58wGM4fAureZyuDrPm9Qz7LvQkB3v0xg2TQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=zsgqDHbBlJtPvylg9VDrTdhz3iGIObXEPLqV1aSfzkxb+S65iBm6SgESgjHZcWmRw bcvF2Ir/QXNfmM6wbZbDscbUWig/Iv8Qwse4/hJOkodmQ2HtvEOIINMGZQtz8wq4tX LJhD+8oDHUa3DMxTU6dP8P+TEBciSajhutShYkGs= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730666AbfLCW6f (ORCPT ); Tue, 3 Dec 2019 17:58:35 -0500 Received: from mail.kernel.org ([198.145.29.99]:55000 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730440AbfLCW6d (ORCPT ); Tue, 3 Dec 2019 17:58:33 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0F2DF2053B; Tue, 3 Dec 2019 22:58:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1575413912; bh=KdwJcVLx58wGM4fAureZyuDrPm9Qz7LvQkB3v0xg2TQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Icp0jU5mxPCSJdNFoeV/74iTLoxC3f0OOT+aXJVGUb0S5CEiAqH775rtqTb5EAvlc VVyAMEdaHUkzXoltT+ZeLo8//dRjoCKnTNKa/7ulD2J2jhO/8Pw7zYPqpn7aZLyT+u d8PWLjmcVrv7FJZ3VkRb72AGM4kln2NI+FRi8dFY= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Gabriel Fernandez , Stephen Boyd , Mathieu Poirier Subject: [PATCH 4.19 311/321] clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks Date: Tue, 3 Dec 2019 23:36:17 +0100 Message-Id: <20191203223443.326776604@linuxfoundation.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191203223427.103571230@linuxfoundation.org> References: <20191203223427.103571230@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Gabriel Fernandez commit 72cfd1ad1057f16fc614861b3c271597995e57ba upstream. STM32MP1 clock IP offers lots of Kernel clocks that are shared by multiple IP's at the same time. Then boot loader applies a clock tree that allows to use all IP's at same time and with the maximum of performance. Not change parents on a change rate on kernel clocks ensures the integrity of the system. Signed-off-by: Gabriel Fernandez Signed-off-by: Stephen Boyd Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- drivers/clk/clk-stm32mp1.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -1286,10 +1286,11 @@ _clk_stm32_register_composite(struct dev MGATE_MP1(_id, _name, _parent, _flags, _mgate) #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\ - COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE | _flags,\ - _MGATE_MP1(_mgate),\ - _MMUX(_mmux),\ - _NO_DIV) + COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\ + CLK_SET_RATE_NO_REPARENT | _flags,\ + _MGATE_MP1(_mgate),\ + _MMUX(_mmux),\ + _NO_DIV) enum { G_SAI1, @@ -1952,7 +1953,8 @@ static const struct clock_config stm32mp MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU), MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12), - COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE, + COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE | + CLK_SET_RATE_NO_REPARENT, _NO_GATE, _MMUX(M_ETHCK), _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),