From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:01 -0700 Subject: [PATCH v6 028/102] x86: Reduce mrccache record alignment size In-Reply-To: <20191207044315.51770-1-sjg@chromium.org> References: <20191207044315.51770-1-sjg@chromium.org> Message-ID: <20191206213936.v6.28.I4de8ad84496e107ad6345eab4527090fa5460f92@changeid> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de At present the records are 4KB in size. This is unnecessarily large when the SPI-flash erase size is 256 bytes. Reduce it so it will be more efficient with Apollo Lake's 24-byte variable-data record. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v6: None Changes in v5: None Changes in v4: - apollolake -> Apollo Lake Changes in v3: None Changes in v2: None arch/x86/include/asm/mrccache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index 40fda856ff..abf5818223 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -7,7 +7,7 @@ #ifndef _ASM_MRCCACHE_H #define _ASM_MRCCACHE_H -#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_ALIGN 0x100 #define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \ ('C' << 16) | ('D'<<24)) -- 2.24.0.393.g34dc348eaf-goog