* [PATCH v7 00/17] x86: Add initial support for apollolake
@ 2019-12-09 0:32 Simon Glass
2019-12-09 0:32 ` [PATCH v7 01/17] x86: apl: Add pinctrl driver Simon Glass
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Simon Glass @ 2019-12-09 0:32 UTC (permalink / raw)
To: u-boot
Apollo Lake is an Intel SoC generation aimed at relatively low-end
embedded systems. It was released in 2016 but has become more popular
recently with some embedded boards using it.
This series adds support for Apollo Lake. As an example it adds an
implementation of chromebook_coral (a large range of Chromebooks released
in 2017).
The series provides enough support to boot to a prompt. with LCD display,
storage, USB, EC and keyboard.
Since this is the first time U-Boot has used FSP2 there is quite a bit of
refactoring needed.
This series is available at u-boot-dm/coral-working
Changes in v7:
- Add a comment to enable_bios_reset_cpl()
- Add the new documentation to the index file
- Drop Glacier Lake code
- Fix value of GPIO_28_IRQ
- Update Kconfig to avoid using def_bool
- Update comment in apl_p2sb_early_init()
Changes in v6:
- Add .driver_data in the designware_pci_supported array
- Add a comment about VANILLA
- Add a comment about the need for board_run_command()
- Add new patch with methods to find the position/size of next SPL phase
- Change comment to apl_hostbridge_early_init_pinctrl, not apl_gpio_early_init
- Change commented-out enable_rtc_upper_bank() call to a TODO
- Drop Glacier Lake code
- Drop init of ComB since it is not used
- Drop lpc_configure_pads() and probe() function, add a comment about pads
- Drop mention of devicetree for VTD feature
- Drop mention of ramstage
- Drop platform data and pre-PCI code, since DM PCI is available in SPL
- Drop unnecessary priv struct and probe method
- Fix FSP-M and FSP-S in comments
- Fix comments for struct apl_hostbridge_platdata
- Fix various coding style problems
- Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option
- Move image pos/size access functions and symbols to generic SPL code
- Move lpss_reset_release() to this commit
- Rename init_for_uart() to board_debug_uart_init()
- Use 'No SPI' instead of 'SPI2' as a debug message
- Use SZ_4G instead of open-coded shift
- Use generic gpio compatible string
Changes in v5:
- Add L2 cache flush function
- Add L2 cache flush functoin
- Add gpio-controller to GPIO nodes
- Allocate the FSP-S data instead of using the stack
- Comment out GPIOs in the fsp_s node since we don't use them yet
- Correct CPU ACPI IDs
- Drop SAFETY_MARGIN
- Drop unrelated change metioned by Heiko
- Enable SMP
- Rename APOLLOLAKE_USB2_PORT_MAX
- Use a define for ACPI base address
Changes in v4:
- Add a comment for enable_bios_reset_cpl()
- Add comments for exported functions
- Add u-boot,skip-auto-config-until-reloc property to PCI
- Adjust the comment for struct dw_i2c_speed_config
- Allow pinctrl nodes to have subnodes (i.e. GPIO nodes)
- Avoid needing to know internals of pinctrl in this driver
- Change apollolake to apl
- Detect zero mmio address
- Drop GPIO_NUM_PAD_CFG_REGS
- Drop duplicate commit 'Create a new sandbox_pci_read_bar() function'
- Enable HAVE_X86_FIT
- Enable INTEL_GPIO
- Move code to pinctrl driver
- Name this P-Unit instead of power unit, in the commit message
- New GPIO driver binding
- Rename arch_fsp_s_preinit() to arch_fsps_preinit()
- Set up LPC pads early
- Switch over to use pinctrl for pad init/config
- Tidy up header guards
- Tidy up mixed case in FSP code
- Tidy up the header file a little
- Update SPI flash protection only in SPL
- Update documentation with more detailed memory map
- Use 'Apollo Lake'
- Use BIT() macro a bit more
- Use BIT() macro bit more
- Use existing VBT Kconfig option
- Use hyphen for device-tree properties
- Use tabs instead of spaces
- apollolake -> Apollo Lake
- use GENMASK() for VTBAR_MASK
Changes in v3:
- Ad FSP-S support
- Add CONFIG_TPL_X86_ASSUME_CPUID to reduce code size
- Add Chrome OS EC support
- Add MMC, video, USB configs
- Add VBT signature
- Add a driver for APL SPI for TPL (using of-platdata)
- Add a proper SPI node and make the SPI flash node a child
- Add a weak function to avoid errors on other platforms
- Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot
- Add bootstage support
- Add bootstage timing for reading vbt
- Add fspm_done() hook to handle FSP-S wierdness (it breaks SPI flash)
- Add more documentation
- Add snapshot/restore for IRQs
- Add spi alias in device tree
- Add structures for FSP-S also
- Add two more defines for the CPU driver
- Add various minor tidy-ups
- Adjust fast_spi_cache_bios_region() to avoid using SPI driver
- Disable the bootcommand since it does nothing useful on coral
- Don't allow BOOT_FROM_FAST_SPI_FLASH with FSP-S
- Don't enable SPI flash in TPL by default
- Drop CONFIG_SPL_NET_SUPPORT
- Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f()
- Drop patch '86: timer: Reduce timer code size in TPL on Intel CPUs'
- Drop patch 'dm: core: Don't include ofnode functions with of-platdata'
- Drop patch 'spi: sandbox: Add a test driver for sandbox SPI flash'
- Drop patch 'spl: Allow SPL/TPL to use of-platdata without libfdt'
- Drop patch 'x86: apollolake: Add definitions for the Intel Fast SPI interface'
- Drop patch 'x86: timer: Set up the timer in timer_early_get_count()'
- Drop struct fsp_usp_header as it is now in the API file
- Drop unused code in lpc_configure_pads()
- Enable video and USB3
- Expand comments for BOOT_FROM_FAST_SPI_FLASH
- Fix build error when debug UART is disabled
- Fix mixed case in GPIO defines
- Fix the incorrect value of CPU_ADDR_BITS
- Fix value of LPC_BC_LE
- Init the p2sb before the northbridge since the latter so it can use GPIOs
- Move location of fast_spi.h header file
- Move pad programming into the hostbridge to reduce TPL device-tree size
- Reduce amount of early-pad data in TPL
- Rework how pads configuration is defined in TPL and SPL
- Set boot_loader_tolum_size to 0
- Shorten log_msg_ret() calls since the function name is always printed
- Support TPL without CONFIG_TPL_SPI_SUPPORT
- Support TPL without CONFIG_TPL_SPI_SUPPORT (reduces code size)
- Support bootstage timing
- Tidy up the pad settings in the device tree
- Use a zero-based tsc timer
- Use pci_get_devfn()
- Use the IRQ uclass instead of ITSS
Changes in v2:
- Drop probe() function
- Implement set_spi_protect()
Simon Glass (17):
x86: apl: Add pinctrl driver
i2c: designware: Add Apollo Lake support
x86: apl: Add systemagent driver
x86: apl: Add hostbridge driver
x86: apl: Add ITSS driver
x86: apl: Add LPC driver
x86: apl: Add PCH driver
x86: apl: Add PUNIT driver
spl: Add methods to find the position/size of next phase
x86: apl: Add SPL loaders
x86: apl: Add a CPU driver
x86: apl: Add SPL/TPL init
x86: apl: Add P2SB driver
x86: apl: Add Kconfig and Makefile
x86: apl: Add FSP structures
x86: apl: Add FSP support
x86: Add chromebook_coral
arch/x86/Kconfig | 1 +
arch/x86/cpu/Makefile | 1 +
arch/x86/cpu/apollolake/Kconfig | 96 ++
arch/x86/cpu/apollolake/Makefile | 21 +
arch/x86/cpu/apollolake/cpu.c | 41 +
arch/x86/cpu/apollolake/cpu_common.c | 17 +
arch/x86/cpu/apollolake/cpu_spl.c | 271 ++++++
arch/x86/cpu/apollolake/fsp_m.c | 210 +++++
arch/x86/cpu/apollolake/fsp_s.c | 661 ++++++++++++++
arch/x86/cpu/apollolake/hostbridge.c | 179 ++++
arch/x86/cpu/apollolake/itss.c | 214 +++++
arch/x86/cpu/apollolake/lpc.c | 122 +++
arch/x86/cpu/apollolake/p2sb.c | 166 ++++
arch/x86/cpu/apollolake/pch.c | 36 +
arch/x86/cpu/apollolake/punit.c | 94 ++
arch/x86/cpu/apollolake/spl.c | 178 ++++
arch/x86/cpu/apollolake/systemagent.c | 23 +
arch/x86/dts/Makefile | 1 +
arch/x86/dts/chromebook_coral.dts | 831 ++++++++++++++++++
arch/x86/include/asm/arch-apollolake/cpu.h | 20 +
.../asm/arch-apollolake/fsp/fsp_configs.h | 14 +
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 123 +++
.../asm/arch-apollolake/fsp/fsp_s_upd.h | 292 ++++++
.../include/asm/arch-apollolake/fsp/fsp_vpd.h | 11 +
arch/x86/include/asm/arch-apollolake/gpio.h | 485 ++++++++++
arch/x86/include/asm/arch-apollolake/itss.h | 43 +
arch/x86/include/asm/arch-apollolake/lpc.h | 82 ++
arch/x86/include/asm/arch-apollolake/pch.h | 9 +
.../include/asm/arch-apollolake/systemagent.h | 37 +
arch/x86/include/asm/msr-index.h | 1 +
board/google/Kconfig | 15 +
board/google/chromebook_coral/Kconfig | 43 +
board/google/chromebook_coral/MAINTAINERS | 6 +
board/google/chromebook_coral/Makefile | 5 +
board/google/chromebook_coral/coral.c | 19 +
common/spl/spl.c | 20 +
configs/chromebook_coral_defconfig | 102 +++
doc/board/google/chromebook_coral.rst | 241 +++++
doc/board/google/index.rst | 1 +
drivers/i2c/designware_i2c_pci.c | 25 +
drivers/pinctrl/intel/Kconfig | 16 +-
drivers/pinctrl/intel/Makefile | 1 +
drivers/pinctrl/intel/pinctrl_apl.c | 192 ++++
include/configs/chromebook_coral.h | 32 +
include/spl.h | 21 +-
45 files changed, 5015 insertions(+), 4 deletions(-)
create mode 100644 arch/x86/cpu/apollolake/Kconfig
create mode 100644 arch/x86/cpu/apollolake/cpu.c
create mode 100644 arch/x86/cpu/apollolake/cpu_common.c
create mode 100644 arch/x86/cpu/apollolake/cpu_spl.c
create mode 100644 arch/x86/cpu/apollolake/fsp_m.c
create mode 100644 arch/x86/cpu/apollolake/fsp_s.c
create mode 100644 arch/x86/cpu/apollolake/hostbridge.c
create mode 100644 arch/x86/cpu/apollolake/itss.c
create mode 100644 arch/x86/cpu/apollolake/lpc.c
create mode 100644 arch/x86/cpu/apollolake/p2sb.c
create mode 100644 arch/x86/cpu/apollolake/pch.c
create mode 100644 arch/x86/cpu/apollolake/punit.c
create mode 100644 arch/x86/cpu/apollolake/spl.c
create mode 100644 arch/x86/cpu/apollolake/systemagent.c
create mode 100644 arch/x86/dts/chromebook_coral.dts
create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h
create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h
create mode 100644 arch/x86/include/asm/arch-apollolake/itss.h
create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h
create mode 100644 arch/x86/include/asm/arch-apollolake/pch.h
create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h
create mode 100644 board/google/chromebook_coral/Kconfig
create mode 100644 board/google/chromebook_coral/MAINTAINERS
create mode 100644 board/google/chromebook_coral/Makefile
create mode 100644 board/google/chromebook_coral/coral.c
create mode 100644 configs/chromebook_coral_defconfig
create mode 100644 doc/board/google/chromebook_coral.rst
create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c
create mode 100644 include/configs/chromebook_coral.h
--
2.24.0.393.g34dc348eaf-goog
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v7 01/17] x86: apl: Add pinctrl driver
2019-12-09 0:32 [PATCH v7 00/17] x86: Add initial support for apollolake Simon Glass
@ 2019-12-09 0:32 ` Simon Glass
2019-12-10 14:06 ` Bin Meng
2019-12-09 0:32 ` [PATCH v7 02/17] i2c: designware: Add Apollo Lake support Simon Glass
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Simon Glass @ 2019-12-09 0:32 UTC (permalink / raw)
To: u-boot
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
common Intel pinctrl support.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v7:
- Drop Glacier Lake code
- Fix value of GPIO_28_IRQ
- Update Kconfig to avoid using def_bool
Changes in v6: None
Changes in v5: None
Changes in v4:
- Allow pinctrl nodes to have subnodes (i.e. GPIO nodes)
- Drop GPIO_NUM_PAD_CFG_REGS
- Switch over to use pinctrl for pad init/config
- Tidy up the header file a little
- apollolake -> Apollo Lake
Changes in v3:
- Add various minor tidy-ups
- Fix mixed case in GPIO defines
- Rework how pads configuration is defined in TPL and SPL
- Use the IRQ uclass instead of ITSS
Changes in v2: None
arch/x86/include/asm/arch-apollolake/gpio.h | 485 ++++++++++++++++++++
drivers/pinctrl/intel/Kconfig | 16 +-
drivers/pinctrl/intel/Makefile | 1 +
drivers/pinctrl/intel/pinctrl_apl.c | 192 ++++++++
4 files changed, 691 insertions(+), 3 deletions(-)
create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h
create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c
diff --git a/arch/x86/include/asm/arch-apollolake/gpio.h b/arch/x86/include/asm/arch-apollolake/gpio.h
new file mode 100644
index 0000000000..10879c168e
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/gpio.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Definitions for the GPIO subsystem on Apollolake
+ *
+ * Copyright (C) 2015 - 2017 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ *
+ * Placed in a separate file since some of these definitions can be used from
+ * assembly code
+ *
+ * Taken from gpio_apl.h in coreboot
+ */
+
+#ifndef _ASM_ARCH_GPIO_H_
+#define _ASM_ARCH_GPIO_H_
+
+/* Port ids */
+#define PID_GPIO_SW 0xC0
+#define PID_GPIO_S 0xC2
+#define PID_GPIO_W 0xC7
+#define PID_GPIO_NW 0xC4
+#define PID_GPIO_N 0xC5
+#define PID_ITSS 0xD0
+#define PID_RTC 0xD1
+
+/*
+ * Miscellaneous Configuration register(MISCCFG). These are community-specific
+ * registers and are meant to house miscellaneous configuration fields per
+ * community. There are 8 GPIO groups: GPP_0 -> GPP_8 (Group 3 is absent)
+ */
+#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration offset */
+#define GPIO_GPE_SW_31_0 0 /* SOUTHWEST GPIO# 0 ~ 31 belong to GROUP0 */
+#define GPIO_GPE_SW_63_32 1 /* SOUTHWEST GPIO# 32 ~ 42 belong to GROUP1 */
+#define GPIO_GPE_W_31_0 2 /* WEST GPIO# 0 ~ 25 belong to GROUP2 */
+#define GPIO_GPE_NW_31_0 4 /* NORTHWEST GPIO# 0 ~ 17 belong to GROUP4 */
+#define GPIO_GPE_NW_63_32 5 /* NORTHWEST GPIO# 32 ~ 63 belong to GROUP5 */
+#define GPIO_GPE_NW_95_64 6 /* NORTHWEST GPIO# 64 ~ 76 belong to GROUP6 */
+#define GPIO_GPE_N_31_0 7 /* NORTH GPIO# 0 ~ 31 belong to GROUP7 */
+#define GPIO_GPE_N_63_32 8 /* NORTH GPIO# 32 ~ 61 belong to GROUP8 */
+
+#define GPIO_MAX_NUM_PER_GROUP 32
+
+/*
+ * Host Software Pad Ownership Register.
+ * The pins in the community are divided into 3 groups:
+ * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95
+ */
+#define HOSTSW_OWN_REG_0 0x80
+
+#define PAD_CFG_BASE 0x500
+
+#define GPI_INT_STS_0 0x100
+#define GPI_INT_EN_0 0x110
+
+#define GPI_SMI_STS_0 0x140
+#define GPI_SMI_EN_0 0x150
+
+#define NUM_N_PADS (PAD_N(SVID0_CLK) + 1)
+#define NUM_NW_PADS (PAD_NW(GPIO_123) + 1)
+#define NUM_W_PADS (PAD_W(SUSPWRDNACK) + 1)
+#define NUM_SW_PADS (PAD_SW(LPC_FRAMEB) + 1)
+
+#define NUM_N_GPI_REGS \
+ (ALIGN(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_NW_GPI_REGS \
+ (ALIGN(NUM_NW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_W_GPI_REGS \
+ (ALIGN(NUM_W_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_SW_GPI_REGS \
+ (ALIGN(NUM_SW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+/*
+ * Total number of GPI status registers across all GPIO communities in the SOC
+ */
+#define NUM_GPI_STATUS_REGS (NUM_N_GPI_REGS + NUM_NW_GPI_REGS \
+ + NUM_W_GPI_REGS + NUM_SW_GPI_REGS)
+
+/* North community pads */
+#define GPIO_0 0
+#define GPIO_1 1
+#define GPIO_2 2
+#define GPIO_3 3
+#define GPIO_4 4
+#define GPIO_5 5
+#define GPIO_6 6
+#define GPIO_7 7
+#define GPIO_8 8
+#define GPIO_9 9
+#define GPIO_10 10
+#define GPIO_11 11
+#define GPIO_12 12
+#define GPIO_13 13
+#define GPIO_14 14
+#define GPIO_15 15
+#define GPIO_16 16
+#define GPIO_17 17
+#define GPIO_18 18
+#define GPIO_19 19
+#define GPIO_20 20
+#define GPIO_21 21
+#define GPIO_22 22
+#define GPIO_23 23
+#define GPIO_24 24
+#define GPIO_25 25
+#define GPIO_26 26
+#define GPIO_27 27
+#define GPIO_28 28
+#define GPIO_29 29
+#define GPIO_30 30
+#define GPIO_31 31
+#define GPIO_32 32
+#define GPIO_33 33
+#define GPIO_34 34
+#define GPIO_35 35
+#define GPIO_36 36
+#define GPIO_37 37
+#define GPIO_38 38
+#define GPIO_39 39
+#define GPIO_40 40
+#define GPIO_41 41
+#define GPIO_42 42
+#define GPIO_43 43
+#define GPIO_44 44
+#define GPIO_45 45
+#define GPIO_46 46
+#define GPIO_47 47
+#define GPIO_48 48
+#define GPIO_49 49
+#define GPIO_62 50
+#define GPIO_63 51
+#define GPIO_64 52
+#define GPIO_65 53
+#define GPIO_66 54
+#define GPIO_67 55
+#define GPIO_68 56
+#define GPIO_69 57
+#define GPIO_70 58
+#define GPIO_71 59
+#define GPIO_72 60
+#define GPIO_73 61
+#define JTAG_TCK 62
+#define JTAG_TRST_B 63
+#define JTAG_TMS 64
+#define JTAG_TDI 65
+#define JTAG_CX_PMODE 66
+#define JTAG_CX_PREQ_B 67
+#define JTAGX 68
+#define JTAG_CX_PRDY_B 69
+#define JTAG_TDO 70
+#define CNV_BRI_DT 71
+#define CNV_BRI_RSP 72
+#define CNV_RGI_DT 73
+#define CNV_RGI_RSP 74
+#define SVID0_ALERT_B 75
+#define SVID0_DATA 76
+#define SVID0_CLK 77
+
+/* Northwest community pads */
+#define GPIO_187 78
+#define GPIO_188 79
+#define GPIO_189 80
+#define GPIO_190 81
+#define GPIO_191 82
+#define GPIO_192 83
+#define GPIO_193 84
+#define GPIO_194 85
+#define GPIO_195 86
+#define GPIO_196 87
+#define GPIO_197 88
+#define GPIO_198 89
+#define GPIO_199 90
+#define GPIO_200 91
+#define GPIO_201 92
+#define GPIO_202 93
+#define GPIO_203 94
+#define GPIO_204 95
+#define PMC_SPI_FS0 96
+#define PMC_SPI_FS1 97
+#define PMC_SPI_FS2 98
+#define PMC_SPI_RXD 99
+#define PMC_SPI_TXD 100
+#define PMC_SPI_CLK 101
+#define PMIC_PWRGOOD 102
+#define PMIC_RESET_B 103
+#define GPIO_213 104
+#define GPIO_214 105
+#define GPIO_215 106
+#define PMIC_THERMTRIP_B 107
+#define PMIC_STDBY 108
+#define PROCHOT_B 109
+#define PMIC_I2C_SCL 110
+#define PMIC_I2C_SDA 111
+#define GPIO_74 112
+#define GPIO_75 113
+#define GPIO_76 114
+#define GPIO_77 115
+#define GPIO_78 116
+#define GPIO_79 117
+#define GPIO_80 118
+#define GPIO_81 119
+#define GPIO_82 120
+#define GPIO_83 121
+#define GPIO_84 122
+#define GPIO_85 123
+#define GPIO_86 124
+#define GPIO_87 125
+#define GPIO_88 126
+#define GPIO_89 127
+#define GPIO_90 128
+#define GPIO_91 129
+#define GPIO_92 130
+#define GPIO_97 131
+#define GPIO_98 132
+#define GPIO_99 133
+#define GPIO_100 134
+#define GPIO_101 135
+#define GPIO_102 136
+#define GPIO_103 137
+#define FST_SPI_CLK_FB 138
+#define GPIO_104 139
+#define GPIO_105 140
+#define GPIO_106 141
+#define GPIO_109 142
+#define GPIO_110 143
+#define GPIO_111 144
+#define GPIO_112 145
+#define GPIO_113 146
+#define GPIO_116 147
+#define GPIO_117 148
+#define GPIO_118 149
+#define GPIO_119 150
+#define GPIO_120 151
+#define GPIO_121 152
+#define GPIO_122 153
+#define GPIO_123 154
+
+/* West community pads */
+#define GPIO_124 155
+#define GPIO_125 156
+#define GPIO_126 157
+#define GPIO_127 158
+#define GPIO_128 159
+#define GPIO_129 160
+#define GPIO_130 161
+#define GPIO_131 162
+#define GPIO_132 163
+#define GPIO_133 164
+#define GPIO_134 165
+#define GPIO_135 166
+#define GPIO_136 167
+#define GPIO_137 168
+#define GPIO_138 169
+#define GPIO_139 170
+#define GPIO_146 171
+#define GPIO_147 172
+#define GPIO_148 173
+#define GPIO_149 174
+#define GPIO_150 175
+#define GPIO_151 176
+#define GPIO_152 177
+#define GPIO_153 178
+#define GPIO_154 179
+#define GPIO_155 180
+#define GPIO_209 181
+#define GPIO_210 182
+#define GPIO_211 183
+#define GPIO_212 184
+#define OSC_CLK_OUT_0 185
+#define OSC_CLK_OUT_1 186
+#define OSC_CLK_OUT_2 187
+#define OSC_CLK_OUT_3 188
+#define OSC_CLK_OUT_4 189
+#define PMU_AC_PRESENT 190
+#define PMU_BATLOW_B 191
+#define PMU_PLTRST_B 192
+#define PMU_PWRBTN_B 193
+#define PMU_RESETBUTTON_B 194
+#define PMU_SLP_S0_B 195
+#define PMU_SLP_S3_B 196
+#define PMU_SLP_S4_B 197
+#define PMU_SUSCLK 198
+#define PMU_WAKE_B 199
+#define SUS_STAT_B 200
+#define SUSPWRDNACK 201
+
+/* Southwest community pads */
+#define GPIO_205 202
+#define GPIO_206 203
+#define GPIO_207 204
+#define GPIO_208 205
+#define GPIO_156 206
+#define GPIO_157 207
+#define GPIO_158 208
+#define GPIO_159 209
+#define GPIO_160 210
+#define GPIO_161 211
+#define GPIO_162 212
+#define GPIO_163 213
+#define GPIO_164 214
+#define GPIO_165 215
+#define GPIO_166 216
+#define GPIO_167 217
+#define GPIO_168 218
+#define GPIO_169 219
+#define GPIO_170 220
+#define GPIO_171 221
+#define GPIO_172 222
+#define GPIO_179 223
+#define GPIO_173 224
+#define GPIO_174 225
+#define GPIO_175 226
+#define GPIO_176 227
+#define GPIO_177 228
+#define GPIO_178 229
+#define GPIO_186 230
+#define GPIO_182 231
+#define GPIO_183 232
+#define SMB_ALERTB 233
+#define SMB_CLK 234
+#define SMB_DATA 235
+#define LPC_ILB_SERIRQ 236
+#define LPC_CLKOUT0 237
+#define LPC_CLKOUT1 238
+#define LPC_AD0 239
+#define LPC_AD1 240
+#define LPC_AD2 241
+#define LPC_AD3 242
+#define LPC_CLKRUNB 243
+#define LPC_FRAMEB 244
+
+/* PERST_0 not defined */
+#define GPIO_PRT0_UDEF 0xFF
+
+#define TOTAL_PADS 245
+#define N_OFFSET GPIO_0
+#define NW_OFFSET GPIO_187
+#define W_OFFSET GPIO_124
+#define SW_OFFSET GPIO_205
+
+/* Macros for translating a global pad offset to a local offset */
+#define PAD_N(pad) (pad - N_OFFSET)
+#define PAD_NW(pad) (pad - NW_OFFSET)
+#define PAD_W(pad) (pad - W_OFFSET)
+#define PAD_SW(pad) (pad - SW_OFFSET)
+
+/* Linux names of the GPIO devices */
+#define GPIO_COMM_N_NAME "INT3452:00"
+#define GPIO_COMM_NW_NAME "INT3452:01"
+#define GPIO_COMM_W_NAME "INT3452:02"
+#define GPIO_COMM_SW_NAME "INT3452:03"
+
+/* Following is used in gpio asl */
+#define GPIO_COMM_NAME "INT3452"
+#define GPIO_COMM_0_DESC \
+ "General Purpose Input/Output (GPIO) Controller - North"
+#define GPIO_COMM_1_DESC \
+ "General Purpose Input/Output (GPIO) Controller - Northwest"
+#define GPIO_COMM_2_DESC \
+ "General Purpose Input/Output (GPIO) Controller - West"
+#define GPIO_COMM_3_DESC \
+ "General Purpose Input/Output (GPIO) Controller - Southwest"
+
+#define GPIO_COMM0_PID PID_GPIO_N
+#define GPIO_COMM1_PID PID_GPIO_NW
+#define GPIO_COMM2_PID PID_GPIO_W
+#define GPIO_COMM3_PID PID_GPIO_SW
+
+/*
+ * IOxAPIC IRQs for the GPIOs, overlap is expected as we encourage to use
+ * shared IRQ instead of direct IRQ, in case of overlapping, we can easily
+ * program one of the overlap to shared IRQ to avoid the conflict.
+ */
+
+/* NorthWest community pads */
+#define PMIC_I2C_SDA_IRQ 0x32
+#define GPIO_74_IRQ 0x33
+#define GPIO_75_IRQ 0x34
+#define GPIO_76_IRQ 0x35
+#define GPIO_77_IRQ 0x36
+#define GPIO_78_IRQ 0x37
+#define GPIO_79_IRQ 0x38
+#define GPIO_80_IRQ 0x39
+#define GPIO_81_IRQ 0x3A
+#define GPIO_82_IRQ 0x3B
+#define GPIO_83_IRQ 0x3C
+#define GPIO_84_IRQ 0x3D
+#define GPIO_85_IRQ 0x3E
+#define GPIO_86_IRQ 0x3F
+#define GPIO_87_IRQ 0x40
+#define GPIO_88_IRQ 0x41
+#define GPIO_89_IRQ 0x42
+#define GPIO_90_IRQ 0x43
+#define GPIO_91_IRQ 0x44
+#define GPIO_97_IRQ 0x49
+#define GPIO_98_IRQ 0x4A
+#define GPIO_99_IRQ 0x4B
+#define GPIO_100_IRQ 0x4C
+#define GPIO_101_IRQ 0x4D
+#define GPIO_102_IRQ 0x4E
+#define GPIO_103_IRQ 0x4F
+#define GPIO_104_IRQ 0x50
+#define GPIO_105_IRQ 0x51
+#define GPIO_106_IRQ 0x52
+#define GPIO_109_IRQ 0x54
+#define GPIO_110_IRQ 0x55
+#define GPIO_111_IRQ 0x56
+#define GPIO_112_IRQ 0x57
+#define GPIO_113_IRQ 0x58
+#define GPIO_116_IRQ 0x5B
+#define GPIO_117_IRQ 0x5C
+#define GPIO_118_IRQ 0x5D
+#define GPIO_119_IRQ 0x5E
+#define GPIO_120_IRQ 0x5F
+#define GPIO_121_IRQ 0x60
+#define GPIO_122_IRQ 0x61
+#define GPIO_123_IRQ 0x62
+
+/* North community pads */
+#define GPIO_0_IRQ 0x63
+#define GPIO_1_IRQ 0x64
+#define GPIO_2_IRQ 0x65
+#define GPIO_3_IRQ 0x66
+#define GPIO_4_IRQ 0x67
+#define GPIO_5_IRQ 0x68
+#define GPIO_6_IRQ 0x69
+#define GPIO_7_IRQ 0x6A
+#define GPIO_8_IRQ 0x6B
+#define GPIO_9_IRQ 0x6C
+#define GPIO_10_IRQ 0x6D
+#define GPIO_11_IRQ 0x6E
+#define GPIO_12_IRQ 0x6F
+#define GPIO_13_IRQ 0x70
+#define GPIO_14_IRQ 0x71
+#define GPIO_15_IRQ 0x72
+#define GPIO_16_IRQ 0x73
+#define GPIO_17_IRQ 0x74
+#define GPIO_18_IRQ 0x75
+#define GPIO_19_IRQ 0x76
+#define GPIO_20_IRQ 0x77
+#define GPIO_21_IRQ 0x32
+#define GPIO_22_IRQ 0x33
+#define GPIO_23_IRQ 0x34
+#define GPIO_24_IRQ 0x35
+#define GPIO_25_IRQ 0x36
+#define GPIO_26_IRQ 0x37
+#define GPIO_27_IRQ 0x38
+#define GPIO_28_IRQ 0x39
+#define GPIO_29_IRQ 0x3A
+#define GPIO_30_IRQ 0x3B
+#define GPIO_31_IRQ 0x3C
+#define GPIO_32_IRQ 0x3D
+#define GPIO_33_IRQ 0x3E
+#define GPIO_34_IRQ 0x3F
+#define GPIO_35_IRQ 0x40
+#define GPIO_36_IRQ 0x41
+#define GPIO_37_IRQ 0x42
+#define GPIO_38_IRQ 0x43
+#define GPIO_39_IRQ 0x44
+#define GPIO_40_IRQ 0x45
+#define GPIO_41_IRQ 0x46
+#define GPIO_42_IRQ 0x47
+#define GPIO_43_IRQ 0x48
+#define GPIO_44_IRQ 0x49
+#define GPIO_45_IRQ 0x4A
+#define GPIO_46_IRQ 0x4B
+#define GPIO_47_IRQ 0x4C
+#define GPIO_48_IRQ 0x4D
+#define GPIO_49_IRQ 0x4E
+#define GPIO_62_IRQ 0x5B
+#define GPIO_63_IRQ 0x5C
+#define GPIO_64_IRQ 0x5D
+#define GPIO_65_IRQ 0x5E
+#define GPIO_66_IRQ 0x5F
+#define GPIO_67_IRQ 0x60
+#define GPIO_68_IRQ 0x61
+#define GPIO_69_IRQ 0x62
+#define GPIO_70_IRQ 0x63
+#define GPIO_71_IRQ 0x64
+#define GPIO_72_IRQ 0x65
+#define GPIO_73_IRQ 0x66
+
+#endif /* _ASM_ARCH_GPIO_H_ */
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index c01c6244d9..e62a2e0349 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -5,12 +5,22 @@
if PINCTRL_INTEL
config INTEL_PINCTRL_DUAL_ROUTE_SUPPORT
- def_bool y
+ bool
+ default y
config INTEL_PINCTRL_PADCFG_PADTOL
- def_bool n
+ bool n
config INTEL_PINCTRL_IOSTANDBY
- def_bool y
+ bool
+ default y
+
+config PINCTRL_INTEL_APL
+ bool "Support Intel Apollo Lake (APL)"
+ help
+ Add support for Intel Apollo Lake pin-control and pin-mux settings.
+ These are mostly read from the device tree, with the early-pads
+ property in the host bridge and the pads property in the fsp-s
+ subnode of the host bridge.
endif
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index bc1aad2c06..3aed8e9663 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -3,3 +3,4 @@
# Copyright 2019 Google LLC
obj-y += pinctrl.o
+obj-$(CONFIG_PINCTRL_INTEL_APL) += pinctrl_apl.o
diff --git a/drivers/pinctrl/intel/pinctrl_apl.c b/drivers/pinctrl/intel/pinctrl_apl.c
new file mode 100644
index 0000000000..bd80435ffa
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl_apl.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Intel Corp.
+ * Copyright 2019 Google LLC
+ *
+ * Taken partly from coreboot gpio.c
+ */
+
+#define LOG_CATEGORY UCLASS_GPIO
+
+#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <p2sb.h>
+#include <asm/intel_pinctrl.h>
+#include <asm-generic/gpio.h>
+#include <asm/intel_pinctrl_defs.h>
+
+/**
+ * struct apl_gpio_platdata - platform data for each device
+ *
+ * @dtplat: of-platdata data from C struct
+ */
+struct apl_gpio_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Put this first since driver model will copy the data here */
+ struct dtd_intel_apl_pinctrl dtplat;
+#endif
+};
+
+static const struct reset_mapping rst_map[] = {
+ { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+
+/* Groups for each community */
+static const struct pad_group apl_community_n_groups[] = {
+ INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_31), /* NORTH 0 */
+ INTEL_GPP(N_OFFSET, GPIO_32, JTAG_TRST_B), /* NORTH 1 */
+ INTEL_GPP(N_OFFSET, JTAG_TMS, SVID0_CLK), /* NORTH 2 */
+};
+
+static const struct pad_group apl_community_w_groups[] = {
+ INTEL_GPP(W_OFFSET, W_OFFSET, OSC_CLK_OUT_1), /* WEST 0 */
+ INTEL_GPP(W_OFFSET, OSC_CLK_OUT_2, SUSPWRDNACK),/* WEST 1 */
+};
+
+static const struct pad_group apl_community_sw_groups[] = {
+ INTEL_GPP(SW_OFFSET, SW_OFFSET, SMB_ALERTB), /* SOUTHWEST 0 */
+ INTEL_GPP(SW_OFFSET, SMB_CLK, LPC_FRAMEB), /* SOUTHWEST 1 */
+};
+
+static const struct pad_group apl_community_nw_groups[] = {
+ INTEL_GPP(NW_OFFSET, NW_OFFSET, PROCHOT_B), /* NORTHWEST 0 */
+ INTEL_GPP(NW_OFFSET, PMIC_I2C_SCL, GPIO_106), /* NORTHWEST 1 */
+ INTEL_GPP(NW_OFFSET, GPIO_109, GPIO_123), /* NORTHWEST 2 */
+};
+
+/* TODO(sjg at chromium.org): Consider moving this to device tree */
+static const struct pad_community apl_gpio_communities[] = {
+ {
+ .port = PID_GPIO_N,
+ .first_pad = N_OFFSET,
+ .last_pad = SVID0_CLK,
+ .num_gpi_regs = NUM_N_GPI_REGS,
+ .gpi_status_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
+ + NUM_SW_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPIO_GPE_N",
+ .acpi_path = "\\_SB.GPO0",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = apl_community_n_groups,
+ .num_groups = ARRAY_SIZE(apl_community_n_groups),
+ }, {
+ .port = PID_GPIO_NW,
+ .first_pad = NW_OFFSET,
+ .last_pad = GPIO_123,
+ .num_gpi_regs = NUM_NW_GPI_REGS,
+ .gpi_status_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPIO_GPE_NW",
+ .acpi_path = "\\_SB.GPO1",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = apl_community_nw_groups,
+ .num_groups = ARRAY_SIZE(apl_community_nw_groups),
+ }, {
+ .port = PID_GPIO_W,
+ .first_pad = W_OFFSET,
+ .last_pad = SUSPWRDNACK,
+ .num_gpi_regs = NUM_W_GPI_REGS,
+ .gpi_status_offset = NUM_SW_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPIO_GPE_W",
+ .acpi_path = "\\_SB.GPO2",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = apl_community_w_groups,
+ .num_groups = ARRAY_SIZE(apl_community_w_groups),
+ }, {
+ .port = PID_GPIO_SW,
+ .first_pad = SW_OFFSET,
+ .last_pad = LPC_FRAMEB,
+ .num_gpi_regs = NUM_SW_GPI_REGS,
+ .gpi_status_offset = 0,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPIO_GPE_SW",
+ .acpi_path = "\\_SB.GPO3",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = apl_community_sw_groups,
+ .num_groups = ARRAY_SIZE(apl_community_sw_groups),
+ },
+};
+
+static int apl_pinctrl_ofdata_to_platdata(struct udevice *dev)
+{
+ struct p2sb_child_platdata *pplat;
+ const struct pad_community *comm = NULL;
+ int i;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct apl_gpio_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ /*
+ * It would be nice to do this in the bind() method, but with
+ * of-platdata binding happens in the order that DM finds things in the
+ * linker list (i.e. alphabetical order by driver name). So the GPIO
+ * device may well be bound before its parent (p2sb), and this call
+ * will fail if p2sb is not bound yet.
+ *
+ * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc
+ */
+ ret = p2sb_set_port_id(dev, plat->dtplat.intel_p2sb_port_id);
+ if (ret)
+ return log_msg_ret("Could not set port id", ret);
+#endif
+ /* Attach this device to its community structure */
+ pplat = dev_get_parent_platdata(dev);
+ for (i = 0; i < ARRAY_SIZE(apl_gpio_communities); i++) {
+ if (apl_gpio_communities[i].port == pplat->pid)
+ comm = &apl_gpio_communities[i];
+ }
+
+ return intel_pinctrl_ofdata_to_platdata(dev, comm, 2);
+}
+
+static const struct udevice_id apl_gpio_ids[] = {
+ { .compatible = "intel,apl-pinctrl"},
+ { }
+};
+
+U_BOOT_DRIVER(apl_pinctrl_drv) = {
+ .name = "intel_apl_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = apl_gpio_ids,
+ .probe = intel_pinctrl_probe,
+ .ops = &intel_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .ofdata_to_platdata = apl_pinctrl_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct intel_pinctrl_priv),
+ .platdata_auto_alloc_size = sizeof(struct apl_gpio_platdata),
+};
--
2.24.0.393.g34dc348eaf-goog
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v7 02/17] i2c: designware: Add Apollo Lake support
2019-12-09 0:32 [PATCH v7 00/17] x86: Add initial support for apollolake Simon Glass
2019-12-09 0:32 ` [PATCH v7 01/17] x86: apl: Add pinctrl driver Simon Glass
@ 2019-12-09 0:32 ` Simon Glass
2019-12-10 14:06 ` Bin Meng
2019-12-09 0:32 ` [PATCH v7 03/17] x86: apl: Add systemagent driver Simon Glass
2019-12-09 0:32 ` [PATCH v7 04/17] x86: apl: Add hostbridge driver Simon Glass
3 siblings, 1 reply; 10+ messages in thread
From: Simon Glass @ 2019-12-09 0:32 UTC (permalink / raw)
To: u-boot
For Apollo Lake we need to take the I2C bus controller out of reset before
using this. Add this functionality to the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
---
Changes in v7: None
Changes in v6:
- Add .driver_data in the designware_pci_supported array
- Add a comment about VANILLA
- Move lpss_reset_release() to this commit
Changes in v5:
- Drop unrelated change metioned by Heiko
Changes in v4:
- apollolake -> Apollo Lake
Changes in v3:
- Add a weak function to avoid errors on other platforms
Changes in v2: None
drivers/i2c/designware_i2c_pci.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
index bb1f809af3..a3586371dc 100644
--- a/drivers/i2c/designware_i2c_pci.c
+++ b/drivers/i2c/designware_i2c_pci.c
@@ -8,8 +8,14 @@
#include <common.h>
#include <dm.h>
#include <spl.h>
+#include <asm/lpss.h>
#include "designware_i2c.h"
+enum {
+ VANILLA = 0, /* standard I2C with no tweaks */
+ INTEL_APL, /* Apollo Lake I2C */
+};
+
/* BayTrail HCNT/LCNT/SDA hold time */
static struct dw_scl_sda_cfg byt_config = {
.ss_hcnt = 0x200,
@@ -19,6 +25,9 @@ static struct dw_scl_sda_cfg byt_config = {
.sda_hold = 0x6,
};
+/* Have a weak function for now - possibly should be a new uclass */
+__weak void lpss_reset_release(void *regs);
+
static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
{
struct dw_i2c *priv = dev_get_priv(dev);
@@ -59,6 +68,15 @@ static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
static int designware_i2c_pci_probe(struct udevice *dev)
{
+ struct dw_i2c *priv = dev_get_priv(dev);
+
+ if (dev_get_driver_data(dev) == INTEL_APL) {
+ /* Ensure controller is in D0 state */
+ lpss_set_power_state(dev, STATE_D0);
+
+ lpss_reset_release(priv->regs);
+ }
+
return designware_i2c_probe(dev);
}
@@ -88,6 +106,7 @@ static int designware_i2c_pci_bind(struct udevice *dev)
static const struct udevice_id designware_i2c_pci_ids[] = {
{ .compatible = "snps,designware-i2c-pci" },
+ { .compatible = "intel,apl-i2c", INTEL_APL },
{ }
};
@@ -113,6 +132,12 @@ static struct pci_device_id designware_pci_supported[] = {
{ PCI_VDEVICE(INTEL, 0x0f45) },
{ PCI_VDEVICE(INTEL, 0x0f46) },
{ PCI_VDEVICE(INTEL, 0x0f47) },
+ { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
+ { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
+ { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
+ { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
+ { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
+ { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
{},
};
--
2.24.0.393.g34dc348eaf-goog
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v7 03/17] x86: apl: Add systemagent driver
2019-12-09 0:32 [PATCH v7 00/17] x86: Add initial support for apollolake Simon Glass
2019-12-09 0:32 ` [PATCH v7 01/17] x86: apl: Add pinctrl driver Simon Glass
2019-12-09 0:32 ` [PATCH v7 02/17] i2c: designware: Add Apollo Lake support Simon Glass
@ 2019-12-09 0:32 ` Simon Glass
2019-12-10 14:06 ` Bin Meng
2019-12-09 0:32 ` [PATCH v7 04/17] x86: apl: Add hostbridge driver Simon Glass
3 siblings, 1 reply; 10+ messages in thread
From: Simon Glass @ 2019-12-09 0:32 UTC (permalink / raw)
To: u-boot
This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v7:
- Add a comment to enable_bios_reset_cpl()
Changes in v6: None
Changes in v5: None
Changes in v4:
- Add a comment for enable_bios_reset_cpl()
- Tidy up header guards
- use GENMASK() for VTBAR_MASK
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 2 +
arch/x86/cpu/apollolake/systemagent.c | 23 ++++++++++++
.../include/asm/arch-apollolake/systemagent.h | 37 +++++++++++++++++++
3 files changed, 62 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/systemagent.c
create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index fdda748ea3..3a8c2f66a3 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -2,5 +2,7 @@
#
# Copyright 2019 Google LLC
+obj-$(CONFIG_SPL_BUILD) += systemagent.o
+
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/systemagent.c b/arch/x86/cpu/apollolake/systemagent.c
new file mode 100644
index 0000000000..b6bc2ba14f
--- /dev/null
+++ b/arch/x86/cpu/apollolake/systemagent.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ * Take from coreboot project file of the same name
+ */
+
+#include <common.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/arch/systemagent.h>
+
+void enable_bios_reset_cpl(void)
+{
+ /*
+ * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
+ * that BIOS has initialised memory and power management
+ *
+ * The FSP-S does not do this. If we leave this as zero then I believe
+ * the power-aware interrupts don't work in Linux, and CPU 0 always gets
+ * the interrupt.
+ */
+ setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3);
+}
diff --git a/arch/x86/include/asm/arch-apollolake/systemagent.h b/arch/x86/include/asm/arch-apollolake/systemagent.h
new file mode 100644
index 0000000000..206d8903fa
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/systemagent.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ * Take from coreboot project file of the same name
+ */
+
+#ifndef _ASM_ARCH_SYSTEMAGENT_H
+#define _ASM_ARCH_SYSTEMAGENT_H
+
+/* Device 0:0.0 PCI configuration space */
+#define MCHBAR 0x48
+
+/* RAPL Package Power Limit register under MCHBAR */
+#define PUNIT_THERMAL_DEVICE_IRQ 0x700C
+#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18
+#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000
+#define BIOS_RESET_CPL 0x7078
+#define PCODE_INIT_DONE BIT(8)
+#define MCHBAR_RAPL_PPL 0x70A8
+#define CORE_DISABLE_MASK 0x7168
+#define CAPID0_A 0xE4
+#define VTD_DISABLE BIT(23)
+#define DEFVTBAR 0x6c80
+#define GFXVTBAR 0x6c88
+#define VTBAR_ENABLED 0x01
+#define VTBAR_MASK GENMASK_ULL(39, 12)
+#define VTBAR_SIZE 0x1000
+
+/**
+ * enable_bios_reset_cpl() - Tell the system agent that memory/power are ready
+ *
+ * This should be called when U-Boot has set up the memory and power
+ * management.
+ */
+void enable_bios_reset_cpl(void);
+
+#endif
--
2.24.0.393.g34dc348eaf-goog
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v7 04/17] x86: apl: Add hostbridge driver
2019-12-09 0:32 [PATCH v7 00/17] x86: Add initial support for apollolake Simon Glass
` (2 preceding siblings ...)
2019-12-09 0:32 ` [PATCH v7 03/17] x86: apl: Add systemagent driver Simon Glass
@ 2019-12-09 0:32 ` Simon Glass
3 siblings, 0 replies; 10+ messages in thread
From: Simon Glass @ 2019-12-09 0:32 UTC (permalink / raw)
To: u-boot
This driver models the hostbridge as a northbridge. It simply sets up the
graphics BAR. It supports of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v7: None
Changes in v6:
- Fix comments for struct apl_hostbridge_platdata
Changes in v5: None
Changes in v4:
- Avoid needing to know internals of pinctrl in this driver
- Move code to pinctrl driver
- Switch over to use pinctrl for pad init/config
Changes in v3:
- Move pad programming into the hostbridge to reduce TPL device-tree size
- Use pci_get_devfn()
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/hostbridge.c | 179 +++++++++++++++++++++++++++
2 files changed, 180 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/hostbridge.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 3a8c2f66a3..4d3c08f84e 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -4,5 +4,6 @@
obj-$(CONFIG_SPL_BUILD) += systemagent.o
+obj-y += hostbridge.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c
new file mode 100644
index 0000000000..793853d5b5
--- /dev/null
+++ b/arch/x86/cpu/apollolake/hostbridge.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <spl.h>
+#include <asm/intel_pinctrl.h>
+#include <asm/intel_regs.h>
+#include <asm/pci.h>
+#include <asm/arch/systemagent.h>
+
+/**
+ * struct apl_hostbridge_platdata - platform data for hostbridge
+ *
+ * @dtplat: Platform data for of-platdata
+ * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
+ * @early_pads_count: Number of pads to process
+ * @pciex_region_size: BAR length in bytes
+ * @bdf: Bus/device/function of hostbridge
+ */
+struct apl_hostbridge_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_hostbridge dtplat;
+#endif
+ u32 *early_pads;
+ int early_pads_count;
+ uint pciex_region_size;
+ pci_dev_t bdf;
+};
+
+enum {
+ PCIEXBAR = 0x60,
+ PCIEXBAR_LENGTH_256MB = 0,
+ PCIEXBAR_LENGTH_128MB,
+ PCIEXBAR_LENGTH_64MB,
+
+ PCIEXBAR_PCIEXBAREN = 1 << 0,
+
+ TSEG = 0xb8, /* TSEG base */
+};
+
+static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
+{
+ struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ struct udevice *pinctrl;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
+ if (ret)
+ return log_msg_ret("no hostbridge pinctrl", ret);
+
+ return pinctrl_config_pads(pinctrl, plat->early_pads,
+ plat->early_pads_count);
+}
+
+static int apl_hostbridge_early_init(struct udevice *dev)
+{
+ struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ u32 region_size;
+ ulong base;
+ u32 reg;
+ int ret;
+
+ /* Set up the MCHBAR */
+ pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32);
+ base = MCH_BASE_ADDRESS;
+ pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32);
+
+ /*
+ * The PCIEXBAR is assumed to live in the memory mapped IO space under
+ * 4GiB
+ */
+ pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32);
+
+ switch (plat->pciex_region_size >> 20) {
+ default:
+ case 256:
+ region_size = PCIEXBAR_LENGTH_256MB;
+ break;
+ case 128:
+ region_size = PCIEXBAR_LENGTH_128MB;
+ break;
+ case 64:
+ region_size = PCIEXBAR_LENGTH_64MB;
+ break;
+ }
+
+ reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1)
+ | PCIEXBAR_PCIEXBAREN;
+ pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32);
+
+ /*
+ * TSEG defines the base of SMM range. BIOS determines the base
+ * of TSEG memory which must be at or below Graphics base of GTT
+ * Stolen memory, hence its better to clear TSEG register early
+ * to avoid power on default non-zero value (if any).
+ */
+ pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32);
+
+ ret = apl_hostbridge_early_init_pinctrl(dev);
+ if (ret)
+ return log_msg_ret("pinctrl", ret);
+
+ return 0;
+}
+
+static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev)
+{
+ struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ struct udevice *pinctrl;
+ int ret;
+
+ /*
+ * The host bridge holds the early pad data needed to get through TPL.
+ * This is a small amount of data, enough to fit in TPL, so we keep it
+ * separate from the full pad data, stored in the fsp-s subnode. That
+ * subnode is not present in TPL, to save space.
+ */
+ ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
+ if (ret)
+ return log_msg_ret("no hostbridge PINCTRL", ret);
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ int root;
+
+ /* Get length of PCI Express Region */
+ plat->pciex_region_size = dev_read_u32_default(dev, "pciex-region-size",
+ 256 << 20);
+
+ root = pci_get_devfn(dev);
+ if (root < 0)
+ return log_msg_ret("Cannot get host-bridge PCI address", root);
+ plat->bdf = root;
+
+ ret = pinctrl_read_pads(pinctrl, dev_ofnode(dev), "early-pads",
+ &plat->early_pads, &plat->early_pads_count);
+ if (ret)
+ return log_msg_ret("early-pads", ret);
+#else
+ struct dtd_intel_apl_hostbridge *dtplat = &plat->dtplat;
+ int size;
+
+ plat->pciex_region_size = dtplat->pciex_region_size;
+ plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
+
+ /* Assume that if everything is 0, it is empty */
+ plat->early_pads = dtplat->early_pads;
+ size = ARRAY_SIZE(dtplat->early_pads);
+ plat->early_pads_count = pinctrl_count_pads(pinctrl, plat->early_pads,
+ size);
+
+#endif
+
+ return 0;
+}
+
+static int apl_hostbridge_probe(struct udevice *dev)
+{
+ if (spl_phase() == PHASE_TPL)
+ return apl_hostbridge_early_init(dev);
+
+ return 0;
+}
+
+static const struct udevice_id apl_hostbridge_ids[] = {
+ { .compatible = "intel,apl-hostbridge" },
+ { }
+};
+
+U_BOOT_DRIVER(apl_hostbridge_drv) = {
+ .name = "intel_apl_hostbridge",
+ .id = UCLASS_NORTHBRIDGE,
+ .of_match = apl_hostbridge_ids,
+ .ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata,
+ .probe = apl_hostbridge_probe,
+ .platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata),
+};
--
2.24.0.393.g34dc348eaf-goog
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v7 01/17] x86: apl: Add pinctrl driver
2019-12-09 0:32 ` [PATCH v7 01/17] x86: apl: Add pinctrl driver Simon Glass
@ 2019-12-10 14:06 ` Bin Meng
2019-12-15 0:29 ` Bin Meng
0 siblings, 1 reply; 10+ messages in thread
From: Bin Meng @ 2019-12-10 14:06 UTC (permalink / raw)
To: u-boot
On Mon, Dec 9, 2019 at 8:32 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
> common Intel pinctrl support.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v7:
> - Drop Glacier Lake code
> - Fix value of GPIO_28_IRQ
> - Update Kconfig to avoid using def_bool
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Allow pinctrl nodes to have subnodes (i.e. GPIO nodes)
> - Drop GPIO_NUM_PAD_CFG_REGS
> - Switch over to use pinctrl for pad init/config
> - Tidy up the header file a little
> - apollolake -> Apollo Lake
>
> Changes in v3:
> - Add various minor tidy-ups
> - Fix mixed case in GPIO defines
> - Rework how pads configuration is defined in TPL and SPL
> - Use the IRQ uclass instead of ITSS
>
> Changes in v2: None
>
> arch/x86/include/asm/arch-apollolake/gpio.h | 485 ++++++++++++++++++++
> drivers/pinctrl/intel/Kconfig | 16 +-
> drivers/pinctrl/intel/Makefile | 1 +
> drivers/pinctrl/intel/pinctrl_apl.c | 192 ++++++++
> 4 files changed, 691 insertions(+), 3 deletions(-)
> create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h
> create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v7 02/17] i2c: designware: Add Apollo Lake support
2019-12-09 0:32 ` [PATCH v7 02/17] i2c: designware: Add Apollo Lake support Simon Glass
@ 2019-12-10 14:06 ` Bin Meng
0 siblings, 0 replies; 10+ messages in thread
From: Bin Meng @ 2019-12-10 14:06 UTC (permalink / raw)
To: u-boot
On Mon, Dec 9, 2019 at 8:32 AM Simon Glass <sjg@chromium.org> wrote:
>
> For Apollo Lake we need to take the I2C bus controller out of reset before
> using this. Add this functionality to the driver.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heiko Schocher <hs@denx.de>
> ---
>
> Changes in v7: None
> Changes in v6:
> - Add .driver_data in the designware_pci_supported array
> - Add a comment about VANILLA
> - Move lpss_reset_release() to this commit
>
> Changes in v5:
> - Drop unrelated change metioned by Heiko
>
> Changes in v4:
> - apollolake -> Apollo Lake
>
> Changes in v3:
> - Add a weak function to avoid errors on other platforms
>
> Changes in v2: None
>
> drivers/i2c/designware_i2c_pci.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
> index bb1f809af3..a3586371dc 100644
> --- a/drivers/i2c/designware_i2c_pci.c
> +++ b/drivers/i2c/designware_i2c_pci.c
> @@ -8,8 +8,14 @@
> #include <common.h>
> #include <dm.h>
> #include <spl.h>
> +#include <asm/lpss.h>
> #include "designware_i2c.h"
>
> +enum {
> + VANILLA = 0, /* standard I2C with no tweaks */
> + INTEL_APL, /* Apollo Lake I2C */
> +};
> +
> /* BayTrail HCNT/LCNT/SDA hold time */
> static struct dw_scl_sda_cfg byt_config = {
> .ss_hcnt = 0x200,
> @@ -19,6 +25,9 @@ static struct dw_scl_sda_cfg byt_config = {
> .sda_hold = 0x6,
> };
>
> +/* Have a weak function for now - possibly should be a new uclass */
> +__weak void lpss_reset_release(void *regs);
> +
> static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
> {
> struct dw_i2c *priv = dev_get_priv(dev);
> @@ -59,6 +68,15 @@ static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
>
> static int designware_i2c_pci_probe(struct udevice *dev)
> {
> + struct dw_i2c *priv = dev_get_priv(dev);
> +
> + if (dev_get_driver_data(dev) == INTEL_APL) {
> + /* Ensure controller is in D0 state */
> + lpss_set_power_state(dev, STATE_D0);
> +
> + lpss_reset_release(priv->regs);
> + }
> +
> return designware_i2c_probe(dev);
> }
>
> @@ -88,6 +106,7 @@ static int designware_i2c_pci_bind(struct udevice *dev)
>
> static const struct udevice_id designware_i2c_pci_ids[] = {
> { .compatible = "snps,designware-i2c-pci" },
> + { .compatible = "intel,apl-i2c", INTEL_APL },
nits: .data = INTEL_APL to make it clear
> { }
> };
>
> @@ -113,6 +132,12 @@ static struct pci_device_id designware_pci_supported[] = {
> { PCI_VDEVICE(INTEL, 0x0f45) },
> { PCI_VDEVICE(INTEL, 0x0f46) },
> { PCI_VDEVICE(INTEL, 0x0f47) },
> + { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
> + { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
> + { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
> + { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
> + { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
> + { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
> {},
> };
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v7 03/17] x86: apl: Add systemagent driver
2019-12-09 0:32 ` [PATCH v7 03/17] x86: apl: Add systemagent driver Simon Glass
@ 2019-12-10 14:06 ` Bin Meng
2019-12-15 0:36 ` Bin Meng
0 siblings, 1 reply; 10+ messages in thread
From: Bin Meng @ 2019-12-10 14:06 UTC (permalink / raw)
To: u-boot
On Mon, Dec 9, 2019 at 8:32 AM Simon Glass <sjg@chromium.org> wrote:
>
> This driver handles communication with the systemagent which needs to be
> told when U-Boot has completed its init.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v7:
> - Add a comment to enable_bios_reset_cpl()
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Add a comment for enable_bios_reset_cpl()
> - Tidy up header guards
> - use GENMASK() for VTBAR_MASK
>
> Changes in v3: None
> Changes in v2: None
>
> arch/x86/cpu/apollolake/Makefile | 2 +
> arch/x86/cpu/apollolake/systemagent.c | 23 ++++++++++++
> .../include/asm/arch-apollolake/systemagent.h | 37 +++++++++++++++++++
> 3 files changed, 62 insertions(+)
> create mode 100644 arch/x86/cpu/apollolake/systemagent.c
> create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v7 01/17] x86: apl: Add pinctrl driver
2019-12-10 14:06 ` Bin Meng
@ 2019-12-15 0:29 ` Bin Meng
0 siblings, 0 replies; 10+ messages in thread
From: Bin Meng @ 2019-12-15 0:29 UTC (permalink / raw)
To: u-boot
On Tue, Dec 10, 2019 at 10:06 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Mon, Dec 9, 2019 at 8:32 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
> > common Intel pinctrl support.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v7:
> > - Drop Glacier Lake code
> > - Fix value of GPIO_28_IRQ
> > - Update Kconfig to avoid using def_bool
> >
> > Changes in v6: None
> > Changes in v5: None
> > Changes in v4:
> > - Allow pinctrl nodes to have subnodes (i.e. GPIO nodes)
> > - Drop GPIO_NUM_PAD_CFG_REGS
> > - Switch over to use pinctrl for pad init/config
> > - Tidy up the header file a little
> > - apollolake -> Apollo Lake
> >
> > Changes in v3:
> > - Add various minor tidy-ups
> > - Fix mixed case in GPIO defines
> > - Rework how pads configuration is defined in TPL and SPL
> > - Use the IRQ uclass instead of ITSS
> >
> > Changes in v2: None
> >
> > arch/x86/include/asm/arch-apollolake/gpio.h | 485 ++++++++++++++++++++
> > drivers/pinctrl/intel/Kconfig | 16 +-
> > drivers/pinctrl/intel/Makefile | 1 +
> > drivers/pinctrl/intel/pinctrl_apl.c | 192 ++++++++
> > 4 files changed, 691 insertions(+), 3 deletions(-)
> > create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h
> > create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
applied to u-boot-x86/next, thanks!
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v7 03/17] x86: apl: Add systemagent driver
2019-12-10 14:06 ` Bin Meng
@ 2019-12-15 0:36 ` Bin Meng
0 siblings, 0 replies; 10+ messages in thread
From: Bin Meng @ 2019-12-15 0:36 UTC (permalink / raw)
To: u-boot
On Tue, Dec 10, 2019 at 10:06 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Mon, Dec 9, 2019 at 8:32 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > This driver handles communication with the systemagent which needs to be
> > told when U-Boot has completed its init.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> >
> > ---
> >
> > Changes in v7:
> > - Add a comment to enable_bios_reset_cpl()
> >
> > Changes in v6: None
> > Changes in v5: None
> > Changes in v4:
> > - Add a comment for enable_bios_reset_cpl()
> > - Tidy up header guards
> > - use GENMASK() for VTBAR_MASK
> >
> > Changes in v3: None
> > Changes in v2: None
> >
> > arch/x86/cpu/apollolake/Makefile | 2 +
> > arch/x86/cpu/apollolake/systemagent.c | 23 ++++++++++++
> > .../include/asm/arch-apollolake/systemagent.h | 37 +++++++++++++++++++
> > 3 files changed, 62 insertions(+)
> > create mode 100644 arch/x86/cpu/apollolake/systemagent.c
> > create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
applied to u-boot-x86/next, thanks!
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-12-15 0:36 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-09 0:32 [PATCH v7 00/17] x86: Add initial support for apollolake Simon Glass
2019-12-09 0:32 ` [PATCH v7 01/17] x86: apl: Add pinctrl driver Simon Glass
2019-12-10 14:06 ` Bin Meng
2019-12-15 0:29 ` Bin Meng
2019-12-09 0:32 ` [PATCH v7 02/17] i2c: designware: Add Apollo Lake support Simon Glass
2019-12-10 14:06 ` Bin Meng
2019-12-09 0:32 ` [PATCH v7 03/17] x86: apl: Add systemagent driver Simon Glass
2019-12-10 14:06 ` Bin Meng
2019-12-15 0:36 ` Bin Meng
2019-12-09 0:32 ` [PATCH v7 04/17] x86: apl: Add hostbridge driver Simon Glass
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