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Mon, 16 Dec 2019 05:58:28 -0500 (EST) Date: Mon, 16 Dec 2019 11:58:27 +0100 From: Maxime Ripard To: Miquel Raynal Cc: Rob Herring , Mark Rutland , devicetree@vger.kernel.org, Heiko Stuebner , linux-rockchip@lists.infradead.org, Daniel Vetter , David Airlie , Sandy Huang , linux-arm-kernel@lists.infradead.org, Paul Kocialkowski , Maxime Chevallier , Thomas Petazzoni , dri-devel@lists.freedesktop.org Subject: Re: [PATCH 09/12] drm/rockchip: lvds: Add PX30 support Message-ID: <20191216105827.rxkfbwemkqw446jx@gilmour.lan> References: <20191213181051.25983-1-miquel.raynal@bootlin.com> <20191213181051.25983-10-miquel.raynal@bootlin.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="akf2tzjwfz7nnjic" Content-Disposition: inline In-Reply-To: <20191213181051.25983-10-miquel.raynal@bootlin.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org --akf2tzjwfz7nnjic Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi, On Fri, Dec 13, 2019 at 07:10:48PM +0100, Miquel Raynal wrote: > +static int px30_lvds_grf_config(struct drm_encoder *encoder, > + struct drm_display_mode *mode) > +{ > + struct rockchip_lvds *lvds = encoder_to_lvds(encoder); > + u8 nhsync = !(mode->flags & DRM_MODE_FLAG_PHSYNC); > + u8 nvsync = !(mode->flags & DRM_MODE_FLAG_PVSYNC); > + u8 ndclk = !(mode->flags & DRM_MODE_FLAG_PCSYNC); > + int ret; > + > + if (lvds->output != DISPLAY_OUTPUT_LVDS) { > + DRM_DEV_ERROR(lvds->dev, "Unsupported display output %d\n", > + lvds->output); > + return -EINVAL; > + } > + > + if (nhsync ^ nvsync) { > + DRM_DEV_ERROR(lvds->dev, "Unsupported Hsync/Vsync polarity\n"); > + return -EINVAL; > + } > + > + /* Set format */ > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON1, > + PX30_LVDS_FORMAT(lvds->format), > + PX30_LVDS_FORMAT(lvds->format)); > + if (ret) > + return ret; > + > + /* Control Hsync/Vsync polarity */ > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON0, > + PX30_LVDS_TIE_CLKS(1), > + PX30_LVDS_TIE_CLKS(1)); > + if (ret) > + return ret; > + > + /* Set Hsync/Vsync polarity */ > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON0, > + PX30_LVDS_INVERT_CLKS(1), > + PX30_LVDS_INVERT_CLKS(nhsync)); > + if (ret) > + return ret; I don't know the hardware but it seems pretty weird to me. hsync and vsync in LVDS are not clocks (or even signals), they're a bit in the payload. Is there any explanation in the datasheet (or even a datasheet in the first place)? Maxime --akf2tzjwfz7nnjic Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXfdjUgAKCRDj7w1vZxhR xRBYAP44GLCelEvFF7JRcxbERsDpTT+xk8XxtfgoWUly8jPqegD+Jrne3aLXYopK ogFPLh6TeB2oQ1+pAWNgKDtT5Zntxwo= =SVmk -----END PGP SIGNATURE----- --akf2tzjwfz7nnjic-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH 09/12] drm/rockchip: lvds: Add PX30 support Date: Mon, 16 Dec 2019 11:58:27 +0100 Message-ID: <20191216105827.rxkfbwemkqw446jx@gilmour.lan> References: <20191213181051.25983-1-miquel.raynal@bootlin.com> <20191213181051.25983-10-miquel.raynal@bootlin.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============3093668142488151188==" Return-path: In-Reply-To: <20191213181051.25983-10-miquel.raynal@bootlin.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Miquel Raynal Cc: Mark Rutland , devicetree@vger.kernel.org, Thomas Petazzoni , Heiko Stuebner , David Airlie , Sandy Huang , dri-devel@lists.freedesktop.org, Maxime Chevallier , Paul Kocialkowski , linux-rockchip@lists.infradead.org, Rob Herring , Daniel Vetter , linux-arm-kernel@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org --===============3093668142488151188== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="akf2tzjwfz7nnjic" Content-Disposition: inline --akf2tzjwfz7nnjic Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi, On Fri, Dec 13, 2019 at 07:10:48PM +0100, Miquel Raynal wrote: > +static int px30_lvds_grf_config(struct drm_encoder *encoder, > + struct drm_display_mode *mode) > +{ > + struct rockchip_lvds *lvds = encoder_to_lvds(encoder); > + u8 nhsync = !(mode->flags & DRM_MODE_FLAG_PHSYNC); > + u8 nvsync = !(mode->flags & DRM_MODE_FLAG_PVSYNC); > + u8 ndclk = !(mode->flags & DRM_MODE_FLAG_PCSYNC); > + int ret; > + > + if (lvds->output != DISPLAY_OUTPUT_LVDS) { > + DRM_DEV_ERROR(lvds->dev, "Unsupported display output %d\n", > + lvds->output); > + return -EINVAL; > + } > + > + if (nhsync ^ nvsync) { > + DRM_DEV_ERROR(lvds->dev, "Unsupported Hsync/Vsync polarity\n"); > + return -EINVAL; > + } > + > + /* Set format */ > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON1, > + PX30_LVDS_FORMAT(lvds->format), > + PX30_LVDS_FORMAT(lvds->format)); > + if (ret) > + return ret; > + > + /* Control Hsync/Vsync polarity */ > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON0, > + PX30_LVDS_TIE_CLKS(1), > + PX30_LVDS_TIE_CLKS(1)); > + if (ret) > + return ret; > + > + /* Set Hsync/Vsync polarity */ > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON0, > + PX30_LVDS_INVERT_CLKS(1), > + PX30_LVDS_INVERT_CLKS(nhsync)); > + if (ret) > + return ret; I don't know the hardware but it seems pretty weird to me. hsync and vsync in LVDS are not clocks (or even signals), they're a bit in the payload. Is there any explanation in the datasheet (or even a datasheet in the first place)? Maxime --akf2tzjwfz7nnjic Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXfdjUgAKCRDj7w1vZxhR xRBYAP44GLCelEvFF7JRcxbERsDpTT+xk8XxtfgoWUly8jPqegD+Jrne3aLXYopK ogFPLh6TeB2oQ1+pAWNgKDtT5Zntxwo= =SVmk -----END PGP SIGNATURE----- --akf2tzjwfz7nnjic-- --===============3093668142488151188== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============3093668142488151188==-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9435C2D0CD for ; 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Mon, 16 Dec 2019 05:58:28 -0500 (EST) Date: Mon, 16 Dec 2019 11:58:27 +0100 From: Maxime Ripard To: Miquel Raynal Subject: Re: [PATCH 09/12] drm/rockchip: lvds: Add PX30 support Message-ID: <20191216105827.rxkfbwemkqw446jx@gilmour.lan> References: <20191213181051.25983-1-miquel.raynal@bootlin.com> <20191213181051.25983-10-miquel.raynal@bootlin.com> MIME-Version: 1.0 In-Reply-To: <20191213181051.25983-10-miquel.raynal@bootlin.com> X-Mailman-Approved-At: Tue, 17 Dec 2019 10:31:56 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Thomas Petazzoni , David Airlie , Sandy Huang , dri-devel@lists.freedesktop.org, Maxime Chevallier , Paul Kocialkowski , linux-rockchip@lists.infradead.org, Rob Herring , linux-arm-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============0981981204==" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --===============0981981204== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="akf2tzjwfz7nnjic" Content-Disposition: inline --akf2tzjwfz7nnjic Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi, On Fri, Dec 13, 2019 at 07:10:48PM +0100, Miquel Raynal wrote: > +static int px30_lvds_grf_config(struct drm_encoder *encoder, > + struct drm_display_mode *mode) > +{ > + struct rockchip_lvds *lvds = encoder_to_lvds(encoder); > + u8 nhsync = !(mode->flags & DRM_MODE_FLAG_PHSYNC); > + u8 nvsync = !(mode->flags & DRM_MODE_FLAG_PVSYNC); > + u8 ndclk = !(mode->flags & DRM_MODE_FLAG_PCSYNC); > + int ret; > + > + if (lvds->output != DISPLAY_OUTPUT_LVDS) { > + DRM_DEV_ERROR(lvds->dev, "Unsupported display output %d\n", > + lvds->output); > + return -EINVAL; > + } > + > + if (nhsync ^ nvsync) { > + DRM_DEV_ERROR(lvds->dev, "Unsupported Hsync/Vsync polarity\n"); > + return -EINVAL; > + } > + > + /* Set format */ > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON1, > + PX30_LVDS_FORMAT(lvds->format), > + PX30_LVDS_FORMAT(lvds->format)); > + if (ret) > + return ret; > + > + /* Control Hsync/Vsync polarity */ > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON0, > + PX30_LVDS_TIE_CLKS(1), > + PX30_LVDS_TIE_CLKS(1)); > + if (ret) > + return ret; > + > + /* Set Hsync/Vsync polarity */ > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON0, > + PX30_LVDS_INVERT_CLKS(1), > + PX30_LVDS_INVERT_CLKS(nhsync)); > + if (ret) > + return ret; I don't know the hardware but it seems pretty weird to me. hsync and vsync in LVDS are not clocks (or even signals), they're a bit in the payload. Is there any explanation in the datasheet (or even a datasheet in the first place)? Maxime --akf2tzjwfz7nnjic Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXfdjUgAKCRDj7w1vZxhR xRBYAP44GLCelEvFF7JRcxbERsDpTT+xk8XxtfgoWUly8jPqegD+Jrne3aLXYopK ogFPLh6TeB2oQ1+pAWNgKDtT5Zntxwo= =SVmk -----END PGP SIGNATURE----- --akf2tzjwfz7nnjic-- --===============0981981204== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel --===============0981981204==--