From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter De Schrijver Subject: Re: [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver Date: Mon, 16 Dec 2019 14:20:05 +0200 Message-ID: <20191216122005.GB28289@pdeschrijver-desktop.Nvidia.com> References: <288a1701-def6-d628-26bc-a305f817bdb1@gmail.com> <78644d45-2ae3-121f-99fc-0a46f205907d@nvidia.com> <49da77dc-b346-68eb-9ef8-42cfb3221489@nvidia.com> <3f1c9325-3017-62be-1e3b-82fd28540fdf@nvidia.com> <6fcbff3d-8695-7cd0-60de-6eb523b6964c@gmail.com> <20191211151028.GZ28289@pdeschrijver-desktop.Nvidia.com> <0930a710-174b-859b-294c-e9f81f6a3b5e@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Return-path: Content-Disposition: inline In-Reply-To: <0930a710-174b-859b-294c-e9f81f6a3b5e@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: Dmitry Osipenko Cc: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, mperttunen@nvidia.com, sboyd@kernel.org, gregkh@linuxfoundation.org, tglx@linutronix.de, robh+dt@kernel.org, mark.rutland@arm.com, allison@lohutok.net, pgaikwad@nvidia.com, mturquette@baylibre.com, horms+renesas@verge.net.au, Jisheng.Zhang@synaptics.com, krzk@kernel.org, arnd@arndb.de, spujar@nvidia.com, josephl@nvidia.com, vidyas@nvidia.com, daniel.lezcano@linaro.org, mmaddireddy@nvidia.com, markz@nvidia.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alexios.zavras@intel.comal List-Id: linux-tegra@vger.kernel.org On Thu, Dec 12, 2019 at 04:43:53AM +0300, Dmitry Osipenko wrote: > External email: Use caution opening links or attachments >=20 >=20 > 11.12.2019 18:10, Peter De Schrijver =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > On Tue, Dec 10, 2019 at 08:41:56PM +0300, Dmitry Osipenko wrote: > > > > .. > > > >>> > >>> PMC clock gate is based on the state of CLKx_ACCEPT_REQ and FORCE_EN > >>> like explained above. > >>> > >>> CLKx_ACCEPT_REQ is 0 default and FORCE_EN acts as gate to enable/disa= ble > >>> EXTPERIPH clock output to PMC CLK_OUT_1/2/3. > >> > >> [and to enable OSC as well] > >> > >>> So I believe we need to register as MUX and Gate rather than as a sin= gle > >>> clock. Please confirm. > >> > >> 1. The force-enabling is applied to both OSC and EXTERN sources of > >> PMC_CLK_OUT_x by PMC at once. > >> > >> 2. Both of PMC's force-enabling and OSC/EXTERN selection is internal t= o PMC. > >> > >> Should be better to define it as a single "pmc_clk_out_x". I don't see > >> any good reasons for differentiating PMC's Gate from the MUX, it's a > >> single hardware unit from a point of view of the rest of the system. > >> > >> Peter, do you have any objections? > > > > The reason to have separate gate and mux clocks, is to preserve compati= bility > > with existing users. > > Otherwise the current users would need to figure out if there's a > > single clock or 2 clocks to configure. I don't think adding that code i= n > > each user is worth it only to have a sligthly nicer modelling of the > > hardware. >=20 > Could you please clarify what do you mean by the "existing users"? > AFAIK, nothing in kernel uses mux clocks. The DT clk bindings allow for parent initialization, so it's certainly possible there are some DTs which rely on this. We promised to never break the bindings, which changing to 1 clock would do.=20 Peter. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD1EFC2D0C0 for ; Mon, 16 Dec 2019 12:20:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B3FB6206D3 for ; Mon, 16 Dec 2019 12:20:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="nM/NgqQU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727606AbfLPMUL (ORCPT ); Mon, 16 Dec 2019 07:20:11 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:7690 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727383AbfLPMUK (ORCPT ); Mon, 16 Dec 2019 07:20:10 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 16 Dec 2019 04:19:59 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 16 Dec 2019 04:20:08 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 16 Dec 2019 04:20:08 -0800 Received: from tbergstrom-lnx.Nvidia.com (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 16 Dec 2019 12:20:07 +0000 Received: by tbergstrom-lnx.Nvidia.com (Postfix, from userid 1000) id 944924280E; Mon, 16 Dec 2019 14:20:05 +0200 (EET) Date: Mon, 16 Dec 2019 14:20:05 +0200 From: Peter De Schrijver To: Dmitry Osipenko CC: Sowjanya Komatineni , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver Message-ID: <20191216122005.GB28289@pdeschrijver-desktop.Nvidia.com> References: <288a1701-def6-d628-26bc-a305f817bdb1@gmail.com> <78644d45-2ae3-121f-99fc-0a46f205907d@nvidia.com> <49da77dc-b346-68eb-9ef8-42cfb3221489@nvidia.com> <3f1c9325-3017-62be-1e3b-82fd28540fdf@nvidia.com> <6fcbff3d-8695-7cd0-60de-6eb523b6964c@gmail.com> <20191211151028.GZ28289@pdeschrijver-desktop.Nvidia.com> <0930a710-174b-859b-294c-e9f81f6a3b5e@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <0930a710-174b-859b-294c-e9f81f6a3b5e@gmail.com> X-NVConfidentiality: public User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1576498800; bh=b7XXctcmXb2fLo5udKQt//zAFp8PM7nufwkYOLIsnKo=; h=X-PGP-Universal:Date:From:To:CC:Subject:Message-ID:References: MIME-Version:Content-Type:Content-Disposition: Content-Transfer-Encoding:In-Reply-To:X-NVConfidentiality: User-Agent:X-Originating-IP:X-ClientProxiedBy; b=nM/NgqQUcSdZRcFF7d0Yn96EQPMCJJewZs/5fXVF74Go86ZnMyQwERe7ZTQTnlbfj ZcvR6MojJdcvYsx4lauCFN2Ya+MLViVVuzS34lOkzq1S2prnU5TqXaZCv+5edNo1SM Km5wJjXWUiokMRJK2NPDugSZinOdkdcXkkonttZB2qxecYprJ0V9NbkzCFVPYF0Zq9 TcXUgZihL0RnrDL3rgiLkB24ZO94eZg1Jtu6Ly4DWyZO4bHT/MVPbIYQ4piIV7pxtR /fuo+JDplJ5G9jQjchl9xQzDko/KvOOvOsLoLn7UMbIgo6dekW5fXziGIF2jY+6rAS mQEZWXAt/zm6g== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Dec 12, 2019 at 04:43:53AM +0300, Dmitry Osipenko wrote: > External email: Use caution opening links or attachments >=20 >=20 > 11.12.2019 18:10, Peter De Schrijver =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > On Tue, Dec 10, 2019 at 08:41:56PM +0300, Dmitry Osipenko wrote: > > > > .. > > > >>> > >>> PMC clock gate is based on the state of CLKx_ACCEPT_REQ and FORCE_EN > >>> like explained above. > >>> > >>> CLKx_ACCEPT_REQ is 0 default and FORCE_EN acts as gate to enable/disa= ble > >>> EXTPERIPH clock output to PMC CLK_OUT_1/2/3. > >> > >> [and to enable OSC as well] > >> > >>> So I believe we need to register as MUX and Gate rather than as a sin= gle > >>> clock. Please confirm. > >> > >> 1. The force-enabling is applied to both OSC and EXTERN sources of > >> PMC_CLK_OUT_x by PMC at once. > >> > >> 2. Both of PMC's force-enabling and OSC/EXTERN selection is internal t= o PMC. > >> > >> Should be better to define it as a single "pmc_clk_out_x". I don't see > >> any good reasons for differentiating PMC's Gate from the MUX, it's a > >> single hardware unit from a point of view of the rest of the system. > >> > >> Peter, do you have any objections? > > > > The reason to have separate gate and mux clocks, is to preserve compati= bility > > with existing users. > > Otherwise the current users would need to figure out if there's a > > single clock or 2 clocks to configure. I don't think adding that code i= n > > each user is worth it only to have a sligthly nicer modelling of the > > hardware. >=20 > Could you please clarify what do you mean by the "existing users"? > AFAIK, nothing in kernel uses mux clocks. The DT clk bindings allow for parent initialization, so it's certainly possible there are some DTs which rely on this. We promised to never break the bindings, which changing to 1 clock would do.=20 Peter. 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charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" T24gVGh1LCBEZWMgMTIsIDIwMTkgYXQgMDQ6NDM6NTNBTSArMDMwMCwgRG1pdHJ5IE9zaXBlbmtv IHdyb3RlOgo+IEV4dGVybmFsIGVtYWlsOiBVc2UgY2F1dGlvbiBvcGVuaW5nIGxpbmtzIG9yIGF0 dGFjaG1lbnRzCj4gCj4gCj4gMTEuMTIuMjAxOSAxODoxMCwgUGV0ZXIgRGUgU2NocmlqdmVyINC/ 0LjRiNC10YI6Cj4gPiBPbiBUdWUsIERlYyAxMCwgMjAxOSBhdCAwODo0MTo1NlBNICswMzAwLCBE bWl0cnkgT3NpcGVua28gd3JvdGU6Cj4gPgo+ID4gLi4KPiA+Cj4gPj4+Cj4gPj4+IFBNQyBjbG9j ayBnYXRlIGlzIGJhc2VkIG9uIHRoZSBzdGF0ZSBvZiBDTEt4X0FDQ0VQVF9SRVEgYW5kIEZPUkNF X0VOCj4gPj4+IGxpa2UgZXhwbGFpbmVkIGFib3ZlLgo+ID4+Pgo+ID4+PiBDTEt4X0FDQ0VQVF9S RVEgaXMgMCBkZWZhdWx0IGFuZCBGT1JDRV9FTiBhY3RzIGFzIGdhdGUgdG8gZW5hYmxlL2Rpc2Fi bGUKPiA+Pj4gRVhUUEVSSVBIIGNsb2NrIG91dHB1dCB0byBQTUMgQ0xLX09VVF8xLzIvMy4KPiA+ Pgo+ID4+IFthbmQgdG8gZW5hYmxlIE9TQyBhcyB3ZWxsXQo+ID4+Cj4gPj4+IFNvIEkgYmVsaWV2 ZSB3ZSBuZWVkIHRvIHJlZ2lzdGVyIGFzIE1VWCBhbmQgR2F0ZSByYXRoZXIgdGhhbiBhcyBhIHNp bmdsZQo+ID4+PiBjbG9jay4gUGxlYXNlIGNvbmZpcm0uCj4gPj4KPiA+PiAxLiBUaGUgZm9yY2Ut ZW5hYmxpbmcgaXMgYXBwbGllZCB0byBib3RoIE9TQyBhbmQgRVhURVJOIHNvdXJjZXMgb2YKPiA+ PiBQTUNfQ0xLX09VVF94IGJ5IFBNQyBhdCBvbmNlLgo+ID4+Cj4gPj4gMi4gQm90aCBvZiBQTUMn cyBmb3JjZS1lbmFibGluZyBhbmQgT1NDL0VYVEVSTiBzZWxlY3Rpb24gaXMgaW50ZXJuYWwgdG8g UE1DLgo+ID4+Cj4gPj4gU2hvdWxkIGJlIGJldHRlciB0byBkZWZpbmUgaXQgYXMgYSBzaW5nbGUg InBtY19jbGtfb3V0X3giLiBJIGRvbid0IHNlZQo+ID4+IGFueSBnb29kIHJlYXNvbnMgZm9yIGRp ZmZlcmVudGlhdGluZyBQTUMncyBHYXRlIGZyb20gdGhlIE1VWCwgaXQncyBhCj4gPj4gc2luZ2xl IGhhcmR3YXJlIHVuaXQgZnJvbSBhIHBvaW50IG9mIHZpZXcgb2YgdGhlIHJlc3Qgb2YgdGhlIHN5 c3RlbS4KPiA+Pgo+ID4+IFBldGVyLCBkbyB5b3UgaGF2ZSBhbnkgb2JqZWN0aW9ucz8KPiA+Cj4g PiBUaGUgcmVhc29uIHRvIGhhdmUgc2VwYXJhdGUgZ2F0ZSBhbmQgbXV4IGNsb2NrcywgaXMgdG8g cHJlc2VydmUgY29tcGF0aWJpbGl0eQo+ID4gd2l0aCBleGlzdGluZyB1c2Vycy4KPiA+IE90aGVy d2lzZSB0aGUgY3VycmVudCB1c2VycyB3b3VsZCBuZWVkIHRvIGZpZ3VyZSBvdXQgaWYgdGhlcmUn cyBhCj4gPiBzaW5nbGUgY2xvY2sgb3IgMiBjbG9ja3MgdG8gY29uZmlndXJlLiBJIGRvbid0IHRo aW5rIGFkZGluZyB0aGF0IGNvZGUgaW4KPiA+IGVhY2ggdXNlciBpcyB3b3J0aCBpdCBvbmx5IHRv IGhhdmUgYSBzbGlndGhseSBuaWNlciBtb2RlbGxpbmcgb2YgdGhlCj4gPiBoYXJkd2FyZS4KPiAK PiBDb3VsZCB5b3UgcGxlYXNlIGNsYXJpZnkgd2hhdCBkbyB5b3UgbWVhbiBieSB0aGUgImV4aXN0 aW5nIHVzZXJzIj8KPiBBRkFJSywgbm90aGluZyBpbiBrZXJuZWwgdXNlcyBtdXggY2xvY2tzLgoK VGhlIERUIGNsayBiaW5kaW5ncyBhbGxvdyBmb3IgcGFyZW50IGluaXRpYWxpemF0aW9uLCBzbyBp dCdzIGNlcnRhaW5seQpwb3NzaWJsZSB0aGVyZSBhcmUgc29tZSBEVHMgd2hpY2ggcmVseSBvbiB0 aGlzLiBXZSBwcm9taXNlZCB0byBuZXZlcgpicmVhayB0aGUgYmluZGluZ3MsIHdoaWNoIGNoYW5n aW5nIHRvIDEgY2xvY2sgd291bGQgZG8uIAoKUGV0ZXIuCl9fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fCkFsc2EtZGV2ZWwgbWFpbGluZyBsaXN0CkFsc2EtZGV2 ZWxAYWxzYS1wcm9qZWN0Lm9yZwpodHRwczovL21haWxtYW4uYWxzYS1wcm9qZWN0Lm9yZy9tYWls bWFuL2xpc3RpbmZvL2Fsc2EtZGV2ZWwK