[PATCH v2 0/9] DP Phy compliance auto test

[PATCH v2 0/9] DP Phy compliance auto test

[Animesh Manna]

Driver changes mainly to process the request coming from Test equipment
as short pulse hpd interrupt to change link-pattern/v-swing/pre-emphasis
Complete auto test suite takes much lesser time than manual run.

Overall design:
--------------
Automate test request will come to source device as HDP short pulse
interrupt from test scope.
Read DPCD 0x201, Check for bit 1 for automated test request.
If set continue and read DPCD 0x218.
Check for bit 3 for phy test pattern, If set continue.
Get the requested test pattern through DPCD 0x248.
Compute requested voltage swing level and pre-emphasis level
from DPCD 0x206 and 0x207
Set signal level through vswing programming sequence.
Write DDI_COMP_CTL and DDI_COMP_PATx as per requested pattern.
Configure the link and write the new test pattern through DPCD.

High level patch description.
-----------------------------
patch 1: drm level api added to get/set test pattern as per vesa
DP spec. This maybe useful for other driver so added in drm layer.
patch 2: Fix for a compilation issue.
patch 3: vswing/preemphasis adjustment calculation is needed during
phy compliance request processing along with existing link training
process, so moved the same function in intel_dp.c.
patch 4: Parse the test scope request regarding  rquested test pattern,
vswing level, preemphasis level.
patch 5: Notify testapp through uevent.
patch 6: Added debugfs entry for phy compliance.
patch 7: Register difnition of DP compliance register added.
patch 8: Function added to update the pattern in source side.
patch 9: This patch os mainly processing the request.

Currently through prototyping patch able to run DP compliance where
vswing, preemphasis and test pattern is changing fine but complete
test is under process. As per feedback redesigned the code. Could not test
due to unavailability of test scope, so sending as RFC again to get design
feedback.

v1: Redesigned the code as per review feedback from Manasi on RFC.
v2: Addressed review comments from Manasi.

Animesh Manna (9):
  drm/dp: get/set phy compliance pattern
  drm/amd/display: Fix compilation issue.
  drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
  drm/i915/dp: Preparation for DP phy compliance auto test
  drm/i915/dsb: Send uevent to testapp.
  drm/i915/dp: Add debugfs entry for DP phy compliance.
  drm/i915/dp: Register definition for DP compliance register
  drm/i915/dp: Update the pattern as per request
  drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern

 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |   2 +-
 drivers/gpu/drm/drm_dp_helper.c               |  93 +++++++++
 drivers/gpu/drm/i915/display/intel_display.c  |  24 ++-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 195 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   5 +
 .../drm/i915/display/intel_dp_link_training.c |  32 ---
 drivers/gpu/drm/i915/i915_debugfs.c           |  12 +-
 drivers/gpu/drm/i915/i915_drv.h               |   2 +
 drivers/gpu/drm/i915/i915_reg.h               |  20 ++
 include/drm/drm_dp_helper.h                   |  33 ++-
 11 files changed, 381 insertions(+), 38 deletions(-)

-- 
2.24.0

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[Intel-gfx] [PATCH v2 0/9] DP Phy compliance auto test

[Animesh Manna]

Driver changes mainly to process the request coming from Test equipment
as short pulse hpd interrupt to change link-pattern/v-swing/pre-emphasis
Complete auto test suite takes much lesser time than manual run.

Overall design:
--------------
Automate test request will come to source device as HDP short pulse
interrupt from test scope.
Read DPCD 0x201, Check for bit 1 for automated test request.
If set continue and read DPCD 0x218.
Check for bit 3 for phy test pattern, If set continue.
Get the requested test pattern through DPCD 0x248.
Compute requested voltage swing level and pre-emphasis level
from DPCD 0x206 and 0x207
Set signal level through vswing programming sequence.
Write DDI_COMP_CTL and DDI_COMP_PATx as per requested pattern.
Configure the link and write the new test pattern through DPCD.

High level patch description.
-----------------------------
patch 1: drm level api added to get/set test pattern as per vesa
DP spec. This maybe useful for other driver so added in drm layer.
patch 2: Fix for a compilation issue.
patch 3: vswing/preemphasis adjustment calculation is needed during
phy compliance request processing along with existing link training
process, so moved the same function in intel_dp.c.
patch 4: Parse the test scope request regarding  rquested test pattern,
vswing level, preemphasis level.
patch 5: Notify testapp through uevent.
patch 6: Added debugfs entry for phy compliance.
patch 7: Register difnition of DP compliance register added.
patch 8: Function added to update the pattern in source side.
patch 9: This patch os mainly processing the request.

Currently through prototyping patch able to run DP compliance where
vswing, preemphasis and test pattern is changing fine but complete
test is under process. As per feedback redesigned the code. Could not test
due to unavailability of test scope, so sending as RFC again to get design
feedback.

v1: Redesigned the code as per review feedback from Manasi on RFC.
v2: Addressed review comments from Manasi.

Animesh Manna (9):
  drm/dp: get/set phy compliance pattern
  drm/amd/display: Fix compilation issue.
  drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
  drm/i915/dp: Preparation for DP phy compliance auto test
  drm/i915/dsb: Send uevent to testapp.
  drm/i915/dp: Add debugfs entry for DP phy compliance.
  drm/i915/dp: Register definition for DP compliance register
  drm/i915/dp: Update the pattern as per request
  drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern

 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |   2 +-
 drivers/gpu/drm/drm_dp_helper.c               |  93 +++++++++
 drivers/gpu/drm/i915/display/intel_display.c  |  24 ++-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 195 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   5 +
 .../drm/i915/display/intel_dp_link_training.c |  32 ---
 drivers/gpu/drm/i915/i915_debugfs.c           |  12 +-
 drivers/gpu/drm/i915/i915_drv.h               |   2 +
 drivers/gpu/drm/i915/i915_reg.h               |  20 ++
 include/drm/drm_dp_helper.h                   |  33 ++-
 11 files changed, 381 insertions(+), 38 deletions(-)

-- 
2.24.0

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[PATCH v2 1/9] drm/dp: get/set phy compliance pattern

[Animesh Manna]

During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.

v2: As per review feedback from Manasi on RFC version,
- added dp revision as function argument in set_phy_pattern api.
- used int for link_rate and u8 for lane_count to align with existing code.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 93 +++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     | 33 +++++++++++-
 2 files changed, 125 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2c7870aef469..91c80973aa83 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1371,3 +1371,96 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 	return num_bpc;
 }
 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data)
+{
+	int err;
+	u8 rate, lanes;
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
+	if (err < 0)
+		return err;
+	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
+	if (err < 0)
+		return err;
+	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
+
+	if (lanes & DP_ENHANCED_FRAME_CAP)
+		data->enahanced_frame_cap = true;
+
+	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
+	if (err < 0)
+		return err;
+
+	switch (data->phy_pattern) {
+	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+				       &data->custom80, 10);
+		if (err < 0)
+			return err;
+
+		break;
+	case DP_PHY_TEST_PATTERN_CP2520:
+		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+				       &data->hbr2_reset, 2);
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data, u8 dp_rev)
+{
+	int err, i;
+	u8 link_config[2];
+	u8 test_pattern;
+
+	link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
+	link_config[1] = data->num_lanes;
+	if (data->enahanced_frame_cap)
+		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
+	if (err < 0)
+		return err;
+
+	test_pattern = data->phy_pattern;
+	if (dp_rev < 0x12) {
+		test_pattern = (test_pattern << 2) &
+			       DP_LINK_QUAL_PATTERN_11_MASK;
+		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
+					 test_pattern);
+		if (err < 0)
+			return err;
+	} else {
+		for (i = 0; i < data->num_lanes; i++) {
+			err = drm_dp_dpcd_writeb(aux,
+						 DP_LINK_QUAL_LANE0_SET + i,
+						 test_pattern);
+			if (err < 0)
+				return err;
+		}
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 8f8f3632e697..42a364748308 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -699,7 +699,16 @@
 # define DP_TEST_CRC_SUPPORTED		    (1 << 5)
 # define DP_TEST_COUNT_MASK		    0xf
 
-#define DP_TEST_PHY_PATTERN                 0x248
+#define DP_PHY_TEST_PATTERN                 0x248
+# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
+# define DP_PHY_TEST_PATTERN_NONE           0x0
+# define DP_PHY_TEST_PATTERN_D10_2          0x1
+# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
+# define DP_PHY_TEST_PATTERN_PRBS7          0x3
+# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
+# define DP_PHY_TEST_PATTERN_CP2520         0x5
+
+#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
@@ -1570,4 +1579,26 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
 
 #endif
 
+/**
+ * struct drm_dp_phy_test_params - DP Phy Compliance parameters
+ * @link: Link information.
+ * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
+ * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
+ *            0x24A and 0x24B (sink)
+ * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
+ *               through 0x259.
+ */
+struct drm_dp_phy_test_params {
+	int link_rate;
+	u8 num_lanes;
+	u8 phy_pattern;
+	u8 hbr2_reset[2];
+	u8 custom80[10];
+	bool enahanced_frame_cap;
+};
+
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data);
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data, u8 dp_rev);
 #endif /* _DRM_DP_HELPER_H_ */
-- 
2.24.0

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[Intel-gfx] [PATCH v2 1/9] drm/dp: get/set phy compliance pattern

[Animesh Manna]

During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.

v2: As per review feedback from Manasi on RFC version,
- added dp revision as function argument in set_phy_pattern api.
- used int for link_rate and u8 for lane_count to align with existing code.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 93 +++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     | 33 +++++++++++-
 2 files changed, 125 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2c7870aef469..91c80973aa83 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1371,3 +1371,96 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 	return num_bpc;
 }
 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data)
+{
+	int err;
+	u8 rate, lanes;
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
+	if (err < 0)
+		return err;
+	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
+	if (err < 0)
+		return err;
+	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
+
+	if (lanes & DP_ENHANCED_FRAME_CAP)
+		data->enahanced_frame_cap = true;
+
+	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
+	if (err < 0)
+		return err;
+
+	switch (data->phy_pattern) {
+	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+				       &data->custom80, 10);
+		if (err < 0)
+			return err;
+
+		break;
+	case DP_PHY_TEST_PATTERN_CP2520:
+		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+				       &data->hbr2_reset, 2);
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data, u8 dp_rev)
+{
+	int err, i;
+	u8 link_config[2];
+	u8 test_pattern;
+
+	link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
+	link_config[1] = data->num_lanes;
+	if (data->enahanced_frame_cap)
+		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
+	if (err < 0)
+		return err;
+
+	test_pattern = data->phy_pattern;
+	if (dp_rev < 0x12) {
+		test_pattern = (test_pattern << 2) &
+			       DP_LINK_QUAL_PATTERN_11_MASK;
+		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
+					 test_pattern);
+		if (err < 0)
+			return err;
+	} else {
+		for (i = 0; i < data->num_lanes; i++) {
+			err = drm_dp_dpcd_writeb(aux,
+						 DP_LINK_QUAL_LANE0_SET + i,
+						 test_pattern);
+			if (err < 0)
+				return err;
+		}
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 8f8f3632e697..42a364748308 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -699,7 +699,16 @@
 # define DP_TEST_CRC_SUPPORTED		    (1 << 5)
 # define DP_TEST_COUNT_MASK		    0xf
 
-#define DP_TEST_PHY_PATTERN                 0x248
+#define DP_PHY_TEST_PATTERN                 0x248
+# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
+# define DP_PHY_TEST_PATTERN_NONE           0x0
+# define DP_PHY_TEST_PATTERN_D10_2          0x1
+# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
+# define DP_PHY_TEST_PATTERN_PRBS7          0x3
+# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
+# define DP_PHY_TEST_PATTERN_CP2520         0x5
+
+#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
@@ -1570,4 +1579,26 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
 
 #endif
 
+/**
+ * struct drm_dp_phy_test_params - DP Phy Compliance parameters
+ * @link: Link information.
+ * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
+ * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
+ *            0x24A and 0x24B (sink)
+ * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
+ *               through 0x259.
+ */
+struct drm_dp_phy_test_params {
+	int link_rate;
+	u8 num_lanes;
+	u8 phy_pattern;
+	u8 hbr2_reset[2];
+	u8 custom80[10];
+	bool enahanced_frame_cap;
+};
+
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data);
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data, u8 dp_rev);
 #endif /* _DRM_DP_HELPER_H_ */
-- 
2.24.0

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[PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Animesh Manna]

[Why]:
Aligh with DP spec wanted to follow same naming convention.

[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 42aa889fd0f5..1a6109be2fce 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 	/* get phy test pattern and pattern parameters from DP receiver */
 	core_link_read_dpcd(
 			link,
-			DP_TEST_PHY_PATTERN,
+			DP_PHY_TEST_PATTERN,
 			&dpcd_test_pattern.raw,
 			sizeof(dpcd_test_pattern));
 	core_link_read_dpcd(
-- 
2.24.0

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[Intel-gfx] [PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Animesh Manna]

[Why]:
Aligh with DP spec wanted to follow same naming convention.

[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 42aa889fd0f5..1a6109be2fce 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 	/* get phy test pattern and pattern parameters from DP receiver */
 	core_link_read_dpcd(
 			link,
-			DP_TEST_PHY_PATTERN,
+			DP_PHY_TEST_PATTERN,
 			&dpcd_test_pattern.raw,
 			sizeof(dpcd_test_pattern));
 	core_link_read_dpcd(
-- 
2.24.0

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[PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Animesh Manna]

vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.

No functional change.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
 .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
 3 files changed, 35 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2f31d226c6eb..ca82835b6dcf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
 	}
 }
 
+void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+		       const u8 *link_status)
+{
+	u8 v = 0;
+	u8 p = 0;
+	int lane;
+	u8 voltage_max;
+	u8 preemph_max;
+
+	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
+		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
+
+		if (this_v > v)
+			v = this_v;
+		if (this_p > p)
+			p = this_p;
+	}
+
+	voltage_max = intel_dp_voltage_max(intel_dp);
+	if (v >= voltage_max)
+		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+	if (p >= preemph_max)
+		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+	for (lane = 0; lane < 4; lane++)
+		intel_dp->train_set[lane] = v | p;
+}
+
 void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..0d0cb692f701 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -91,6 +91,9 @@ void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 				       u8 dp_train_pat);
 void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+		       const u8 *link_status);
+void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
 u8
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..1e38584e7d56 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
 		      link_status[3], link_status[4], link_status[5]);
 }
 
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
-		       const u8 link_status[DP_LINK_STATUS_SIZE])
-{
-	u8 v = 0;
-	u8 p = 0;
-	int lane;
-	u8 voltage_max;
-	u8 preemph_max;
-
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
-		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
-		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-
-		if (this_v > v)
-			v = this_v;
-		if (this_p > p)
-			p = this_p;
-	}
-
-	voltage_max = intel_dp_voltage_max(intel_dp);
-	if (v >= voltage_max)
-		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
-
-	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
-	if (p >= preemph_max)
-		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
-	for (lane = 0; lane < 4; lane++)
-		intel_dp->train_set[lane] = v | p;
-}
-
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
 			u8 dp_train_pat)
-- 
2.24.0

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[Intel-gfx] [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Animesh Manna]

vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.

No functional change.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
 .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
 3 files changed, 35 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2f31d226c6eb..ca82835b6dcf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
 	}
 }
 
+void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+		       const u8 *link_status)
+{
+	u8 v = 0;
+	u8 p = 0;
+	int lane;
+	u8 voltage_max;
+	u8 preemph_max;
+
+	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
+		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
+
+		if (this_v > v)
+			v = this_v;
+		if (this_p > p)
+			p = this_p;
+	}
+
+	voltage_max = intel_dp_voltage_max(intel_dp);
+	if (v >= voltage_max)
+		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+	if (p >= preemph_max)
+		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+	for (lane = 0; lane < 4; lane++)
+		intel_dp->train_set[lane] = v | p;
+}
+
 void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..0d0cb692f701 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -91,6 +91,9 @@ void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 				       u8 dp_train_pat);
 void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+		       const u8 *link_status);
+void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
 u8
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..1e38584e7d56 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
 		      link_status[3], link_status[4], link_status[5]);
 }
 
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
-		       const u8 link_status[DP_LINK_STATUS_SIZE])
-{
-	u8 v = 0;
-	u8 p = 0;
-	int lane;
-	u8 voltage_max;
-	u8 preemph_max;
-
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
-		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
-		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-
-		if (this_v > v)
-			v = this_v;
-		if (this_p > p)
-			p = this_p;
-	}
-
-	voltage_max = intel_dp_voltage_max(intel_dp);
-	if (v >= voltage_max)
-		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
-
-	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
-	if (p >= preemph_max)
-		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
-	for (lane = 0; lane < 4; lane++)
-		intel_dp->train_set[lane] = v | p;
-}
-
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
 			u8 dp_train_pat)
-- 
2.24.0

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[PATCH v2 4/9] drm/i915/dp: Preparation for DP phy compliance auto test

[Animesh Manna]

During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 24 +++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..c17866f126c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1205,6 +1205,7 @@ struct intel_dp_compliance_data {
 	u8 video_pattern;
 	u16 hdisplay, vdisplay;
 	u8 bpc;
+	struct drm_dp_phy_test_params phytest;
 };
 
 struct intel_dp_compliance {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ca82835b6dcf..a871834b90d9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4984,9 +4984,33 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
 	return test_result;
 }
 
+static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
+{
+	struct drm_dp_phy_test_params *data =
+		&intel_dp->compliance.test_data.phytest;
+
+	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
+		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+		return DP_TEST_NAK;
+	}
+
+	/*
+	 * link_mst is set to false to avoid executing mst related code
+	 * during compliance testing.
+	 */
+	intel_dp->link_mst = false;
+
+	return DP_TEST_ACK;
+}
+
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
 	u8 test_result = DP_TEST_NAK;
+
+	test_result = intel_dp_prepare_phytest(intel_dp);
+	if (test_result != DP_TEST_ACK)
+		DRM_ERROR("Phy test preparation failed\n");
+
 	return test_result;
 }
 
-- 
2.24.0

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[Intel-gfx] [PATCH v2 4/9] drm/i915/dp: Preparation for DP phy compliance auto test

[Animesh Manna]

During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 24 +++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..c17866f126c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1205,6 +1205,7 @@ struct intel_dp_compliance_data {
 	u8 video_pattern;
 	u16 hdisplay, vdisplay;
 	u8 bpc;
+	struct drm_dp_phy_test_params phytest;
 };
 
 struct intel_dp_compliance {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ca82835b6dcf..a871834b90d9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4984,9 +4984,33 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
 	return test_result;
 }
 
+static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
+{
+	struct drm_dp_phy_test_params *data =
+		&intel_dp->compliance.test_data.phytest;
+
+	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
+		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+		return DP_TEST_NAK;
+	}
+
+	/*
+	 * link_mst is set to false to avoid executing mst related code
+	 * during compliance testing.
+	 */
+	intel_dp->link_mst = false;
+
+	return DP_TEST_ACK;
+}
+
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
 	u8 test_result = DP_TEST_NAK;
+
+	test_result = intel_dp_prepare_phytest(intel_dp);
+	if (test_result != DP_TEST_ACK)
+		DRM_ERROR("Phy test preparation failed\n");
+
 	return test_result;
 }
 
-- 
2.24.0

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[PATCH v2 5/9] drm/i915/dsb: Send uevent to testapp.

[Animesh Manna]

Send uevent to testapp and set test_active flag. To align with link
compliance design existing intel_dp_compliance tool will be used to
get the phy request in userspace through uevent.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a871834b90d9..81eeb9bbb050 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5011,6 +5011,9 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 	if (test_result != DP_TEST_ACK)
 		DRM_ERROR("Phy test preparation failed\n");
 
+	/* Set test active flag here so userspace doesn't interrupt things */
+	intel_dp->compliance.test_active = 1;
+
 	return test_result;
 }
 
@@ -5336,8 +5339,11 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
 
 	intel_psr_short_pulse(intel_dp);
 
-	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
-		DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
+	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING ||
+	    intel_dp->compliance.test_type ==
+	    DP_TEST_LINK_PHY_TEST_PATTERN) {
+		DRM_DEBUG_KMS("Compliance Test requested, test-type = 0x%lx\n",
+			      intel_dp->compliance.test_type);
 		/* Send a Hotplug Uevent to userspace to start modeset */
 		drm_kms_helper_hotplug_event(&dev_priv->drm);
 	}
-- 
2.24.0

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[Intel-gfx] [PATCH v2 5/9] drm/i915/dsb: Send uevent to testapp.

[Animesh Manna]

Send uevent to testapp and set test_active flag. To align with link
compliance design existing intel_dp_compliance tool will be used to
get the phy request in userspace through uevent.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a871834b90d9..81eeb9bbb050 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5011,6 +5011,9 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 	if (test_result != DP_TEST_ACK)
 		DRM_ERROR("Phy test preparation failed\n");
 
+	/* Set test active flag here so userspace doesn't interrupt things */
+	intel_dp->compliance.test_active = 1;
+
 	return test_result;
 }
 
@@ -5336,8 +5339,11 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
 
 	intel_psr_short_pulse(intel_dp);
 
-	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
-		DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
+	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING ||
+	    intel_dp->compliance.test_type ==
+	    DP_TEST_LINK_PHY_TEST_PATTERN) {
+		DRM_DEBUG_KMS("Compliance Test requested, test-type = 0x%lx\n",
+			      intel_dp->compliance.test_type);
 		/* Send a Hotplug Uevent to userspace to start modeset */
 		drm_kms_helper_hotplug_event(&dev_priv->drm);
 	}
-- 
2.24.0

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[PATCH v2 6/9] drm/i915/dp: Add debugfs entry for DP phy compliance.

[Animesh Manna]

These debugfs entry will help testapp to understand the test request
during dp phy compliance mode.

Acked-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d28468eaed57..715a6c26d0c9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3173,6 +3173,16 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
 					   intel_dp->compliance.test_data.vdisplay);
 				seq_printf(m, "bpc: %u\n",
 					   intel_dp->compliance.test_data.bpc);
+			} else if (intel_dp->compliance.test_type ==
+				   DP_TEST_LINK_PHY_TEST_PATTERN) {
+				seq_printf(m, "pattern: %d\n",
+					   intel_dp->compliance.test_data.phytest.phy_pattern);
+				seq_printf(m, "Number of lanes: %d\n",
+					   intel_dp->compliance.test_data.phytest.num_lanes);
+				seq_printf(m, "Link Rate: %d\n",
+					   intel_dp->compliance.test_data.phytest.link_rate);
+				seq_printf(m, "level: %02x\n",
+					   intel_dp->train_set[0]);
 			}
 		} else
 			seq_puts(m, "0");
@@ -3205,7 +3215,7 @@ static int i915_displayport_test_type_show(struct seq_file *m, void *data)
 
 		if (encoder && connector->status == connector_status_connected) {
 			intel_dp = enc_to_intel_dp(&encoder->base);
-			seq_printf(m, "%02lx", intel_dp->compliance.test_type);
+			seq_printf(m, "%02lx\n", intel_dp->compliance.test_type);
 		} else
 			seq_puts(m, "0");
 	}
-- 
2.24.0

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[Intel-gfx] [PATCH v2 6/9] drm/i915/dp: Add debugfs entry for DP phy compliance.

[Animesh Manna]

These debugfs entry will help testapp to understand the test request
during dp phy compliance mode.

Acked-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d28468eaed57..715a6c26d0c9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3173,6 +3173,16 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
 					   intel_dp->compliance.test_data.vdisplay);
 				seq_printf(m, "bpc: %u\n",
 					   intel_dp->compliance.test_data.bpc);
+			} else if (intel_dp->compliance.test_type ==
+				   DP_TEST_LINK_PHY_TEST_PATTERN) {
+				seq_printf(m, "pattern: %d\n",
+					   intel_dp->compliance.test_data.phytest.phy_pattern);
+				seq_printf(m, "Number of lanes: %d\n",
+					   intel_dp->compliance.test_data.phytest.num_lanes);
+				seq_printf(m, "Link Rate: %d\n",
+					   intel_dp->compliance.test_data.phytest.link_rate);
+				seq_printf(m, "level: %02x\n",
+					   intel_dp->train_set[0]);
 			}
 		} else
 			seq_puts(m, "0");
@@ -3205,7 +3215,7 @@ static int i915_displayport_test_type_show(struct seq_file *m, void *data)
 
 		if (encoder && connector->status == connector_status_connected) {
 			intel_dp = enc_to_intel_dp(&encoder->base);
-			seq_printf(m, "%02lx", intel_dp->compliance.test_type);
+			seq_printf(m, "%02lx\n", intel_dp->compliance.test_type);
 		} else
 			seq_puts(m, "0");
 	}
-- 
2.24.0

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[PATCH v2 7/9] drm/i915/dp: Register definition for DP compliance register

[Animesh Manna]

DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbb4689af432..fc54143bd4a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9788,6 +9788,26 @@ enum skl_power_gate {
 #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
 #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
 
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A                      0x605F0
+#define DDI_DP_COMP_CTL_B                      0x615F0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \
+					 DDI_DP_COMP_CTL_B)
+#define  DDI_DP_COMP_CTL_ENABLE                        (1 << 31)
+#define  DDI_DP_COMP_CTL_D10_2                 (0 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_0           (1 << 28)
+#define  DDI_DP_COMP_CTL_PRBS7                 (2 << 28)
+#define  DDI_DP_COMP_CTL_CUSTOM80                      (3 << 28)
+#define  DDI_DP_COMP_CTL_HBR2                  (4 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_1           (5 << 28)
+#define  DDI_DP_COMP_CTL_HBR2_RESET            (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A                      0x605F4
+#define DDI_DP_COMP_PAT_B                      0x615F4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \
+					     DDI_DP_COMP_PAT_B) + (i) * 4)
+
 /* Sideband Interface (SBI) is programmed indirectly, via
  * SBI_ADDR, which contains the register offset; and SBI_DATA,
  * which contains the payload */
-- 
2.24.0

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[Intel-gfx] [PATCH v2 7/9] drm/i915/dp: Register definition for DP compliance register

[Animesh Manna]

DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbb4689af432..fc54143bd4a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9788,6 +9788,26 @@ enum skl_power_gate {
 #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
 #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
 
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A                      0x605F0
+#define DDI_DP_COMP_CTL_B                      0x615F0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \
+					 DDI_DP_COMP_CTL_B)
+#define  DDI_DP_COMP_CTL_ENABLE                        (1 << 31)
+#define  DDI_DP_COMP_CTL_D10_2                 (0 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_0           (1 << 28)
+#define  DDI_DP_COMP_CTL_PRBS7                 (2 << 28)
+#define  DDI_DP_COMP_CTL_CUSTOM80                      (3 << 28)
+#define  DDI_DP_COMP_CTL_HBR2                  (4 << 28)
+#define  DDI_DP_COMP_CTL_SCRAMBLED_1           (5 << 28)
+#define  DDI_DP_COMP_CTL_HBR2_RESET            (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A                      0x605F4
+#define DDI_DP_COMP_PAT_B                      0x615F4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \
+					     DDI_DP_COMP_PAT_B) + (i) * 4)
+
 /* Sideband Interface (SBI) is programmed indirectly, via
  * SBI_ADDR, which contains the register offset; and SBI_DATA,
  * which contains the payload */
-- 
2.24.0

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[PATCH v2 8/9] drm/i915/dp: Update the pattern as per request

[Animesh Manna]

As per request from DP phy compliance test few special
test pattern need to set by source. Added function
to set pattern in DP_COMP_CTL register. It will be
called along with other test parameters like vswing,
pre-emphasis programming in atomic_commit_tail path.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 81eeb9bbb050..f38929db1f2e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5003,6 +5003,61 @@ static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
 	return DP_TEST_ACK;
 }
 
+static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv =
+			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_dp_phy_test_params *data =
+			&intel_dp->compliance.test_data.phytest;
+	u32 temp;
+
+	switch (data->phy_pattern) {
+	case DP_PHY_TEST_PATTERN_NONE:
+		DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), 0x0);
+		break;
+	case DP_PHY_TEST_PATTERN_D10_2:
+		DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
+		break;
+	case DP_PHY_TEST_PATTERN_ERROR_COUNT:
+		DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE |
+			   DDI_DP_COMP_CTL_SCRAMBLED_0);
+		break;
+	case DP_PHY_TEST_PATTERN_PRBS7:
+		DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
+		break;
+	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+		DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern\n");
+		temp = ((data->custom80[0] << 24) | (data->custom80[1] << 16) |
+			(data->custom80[2] << 8) | (data->custom80[3]));
+		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 0), temp);
+		temp = ((data->custom80[4] << 24) | (data->custom80[5] << 16) |
+			(data->custom80[6] << 8) | (data->custom80[7]));
+		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 1), temp);
+		temp = ((data->custom80[8] << 8) | data->custom80[9]);
+		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 2), temp);
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80);
+		break;
+	case DP_PHY_TEST_PATTERN_CP2520:
+		DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
+		temp = ((data->hbr2_reset[1] << 8) | data->hbr2_reset[0]);
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
+			   temp);
+		break;
+	default:
+		WARN(1, "Invalid Phy Test PAttern\n");
+	}
+}
+
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
 	u8 test_result = DP_TEST_NAK;
-- 
2.24.0

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[Intel-gfx] [PATCH v2 8/9] drm/i915/dp: Update the pattern as per request

[Animesh Manna]

As per request from DP phy compliance test few special
test pattern need to set by source. Added function
to set pattern in DP_COMP_CTL register. It will be
called along with other test parameters like vswing,
pre-emphasis programming in atomic_commit_tail path.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 81eeb9bbb050..f38929db1f2e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5003,6 +5003,61 @@ static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
 	return DP_TEST_ACK;
 }
 
+static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv =
+			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_dp_phy_test_params *data =
+			&intel_dp->compliance.test_data.phytest;
+	u32 temp;
+
+	switch (data->phy_pattern) {
+	case DP_PHY_TEST_PATTERN_NONE:
+		DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), 0x0);
+		break;
+	case DP_PHY_TEST_PATTERN_D10_2:
+		DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
+		break;
+	case DP_PHY_TEST_PATTERN_ERROR_COUNT:
+		DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE |
+			   DDI_DP_COMP_CTL_SCRAMBLED_0);
+		break;
+	case DP_PHY_TEST_PATTERN_PRBS7:
+		DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
+		break;
+	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+		DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern\n");
+		temp = ((data->custom80[0] << 24) | (data->custom80[1] << 16) |
+			(data->custom80[2] << 8) | (data->custom80[3]));
+		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 0), temp);
+		temp = ((data->custom80[4] << 24) | (data->custom80[5] << 16) |
+			(data->custom80[6] << 8) | (data->custom80[7]));
+		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 1), temp);
+		temp = ((data->custom80[8] << 8) | data->custom80[9]);
+		I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 2), temp);
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80);
+		break;
+	case DP_PHY_TEST_PATTERN_CP2520:
+		DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
+		temp = ((data->hbr2_reset[1] << 8) | data->hbr2_reset[0]);
+		I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+			   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
+			   temp);
+		break;
+	default:
+		WARN(1, "Invalid Phy Test PAttern\n");
+	}
+}
+
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
 	u8 test_result = DP_TEST_NAK;
-- 
2.24.0

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[PATCH v2 9/9] drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern

[Animesh Manna]

This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.

Note: FIXME tag added as design discusion is ongoing in previous patch
series. Some temporary fix added and the patch is under-development, not for
review.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 24 ++++++-
 drivers/gpu/drm/i915/display/intel_dp.c      | 74 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h      |  2 +
 drivers/gpu/drm/i915/i915_drv.h              |  2 +
 4 files changed, 101 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e18ee1f17d6e..2d58ed249452 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14084,6 +14084,9 @@ static int intel_atomic_check(struct drm_device *dev,
 	int ret, i;
 	bool any_ms = false;
 
+	if (dev_priv->dp_phy_comp)
+		return 0;
+
 	/* Catch I915_MODE_FLAG_INHERITED */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
@@ -14692,10 +14695,23 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_crtc *crtc;
+	const struct drm_connector_state *conn_state;
+	struct drm_connector *conn;
 	u64 put_domains[I915_MAX_PIPES] = {};
 	intel_wakeref_t wakeref = 0;
 	int i;
 
+	if(dev_priv->dp_phy_comp) {
+		for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+			struct intel_encoder *encoder =
+				to_intel_encoder(conn_state->best_encoder);
+			struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+			intel_dp_process_phy_request(intel_dp);
+		}
+		goto dp_phy_comp1;
+	}
+
 	intel_atomic_commit_fence_wait(state);
 
 	drm_atomic_helper_wait_for_dependencies(&state->base);
@@ -14830,6 +14846,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	if (state->modeset && intel_can_enable_sagv(state))
 		intel_enable_sagv(dev_priv);
 
+dp_phy_comp1:
 	drm_atomic_helper_commit_hw_done(&state->base);
 
 	if (state->modeset) {
@@ -14921,6 +14938,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
 	drm_atomic_state_get(&state->base);
+	if (!dev_priv->dp_phy_comp) {
 	i915_sw_fence_init(&state->commit_ready,
 			   intel_atomic_commit_ready);
 
@@ -14959,11 +14977,13 @@ static int intel_atomic_commit(struct drm_device *dev,
 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
 		return ret;
 	}
+	}
 
 	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
 	if (!ret)
 		ret = drm_atomic_helper_swap_state(&state->base, true);
 
+	if (!dev_priv->dp_phy_comp) {
 	if (ret) {
 		i915_sw_fence_commit(&state->commit_ready);
 
@@ -14974,6 +14994,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 	dev_priv->wm.distrust_bios_wm = false;
 	intel_shared_dpll_swap_state(state);
 	intel_atomic_track_fbs(state);
+	}
 
 	if (state->global_state_changed) {
 		assert_global_state_locked(dev_priv);
@@ -14990,8 +15011,9 @@ static int intel_atomic_commit(struct drm_device *dev,
 
 	drm_atomic_state_get(&state->base);
 	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
-
+	if (!dev_priv->dp_phy_comp) {
 	i915_sw_fence_commit(&state->commit_ready);
+	}
 	if (nonblock && state->modeset) {
 		queue_work(dev_priv->modeset_wq, &state->base.commit_work);
 	} else if (nonblock) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f38929db1f2e..4b4fa9074d18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5058,9 +5058,82 @@ static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 	}
 }
 
+static void
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum port port = intel_dig_port->base.port;
+	u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+	ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+	dp_tp_ctl_value = I915_READ(TGL_DP_TP_CTL(port));
+	trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+	ddi_buf_ctl_value        &= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK);
+	dp_tp_ctl_value          &= ~DP_TP_CTL_ENABLE;
+	trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
+				      DDI_PORT_WIDTH_MASK);
+
+	I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+	I915_WRITE(TGL_DP_TP_CTL(port), dp_tp_ctl_value);
+	I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+}
+
+static void
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum port port = intel_dig_port->base.port;
+	u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+	ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+	dp_tp_ctl_value = I915_READ(TGL_DP_TP_CTL(port));
+	trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+	ddi_buf_ctl_value |= DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH(lane_cnt);
+	dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
+	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
+				    DDI_PORT_WIDTH(lane_cnt);
+
+	I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+	I915_WRITE(TGL_DP_TP_CTL(port), dp_tp_ctl_value);
+	I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+}
+
+void intel_dp_process_phy_request(struct intel_dp *intel_dp)
+{
+	struct drm_dp_phy_test_params *data =
+		&intel_dp->compliance.test_data.phytest;
+	u8 link_status[DP_LINK_STATUS_SIZE];
+
+	if (!intel_dp_get_link_status(intel_dp, link_status)) {
+		DRM_DEBUG_KMS("failed to get link status\n");
+		return;
+	}
+
+	/* retrieve vswing & pre-emphasis setting */
+	intel_get_adjust_train(intel_dp, link_status);
+
+	intel_dp_autotest_phy_ddi_disable(intel_dp);
+
+	intel_dp_set_signal_levels(intel_dp);
+
+	intel_dp_phy_pattern_update(intel_dp);
+
+	intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
+
+	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
+				    link_status[DP_DPCD_REV]);
+}
+
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
 	u8 test_result = DP_TEST_NAK;
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
 	test_result = intel_dp_prepare_phytest(intel_dp);
 	if (test_result != DP_TEST_ACK)
@@ -5068,6 +5141,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 
 	/* Set test active flag here so userspace doesn't interrupt things */
 	intel_dp->compliance.test_active = 1;
+	dev_priv->dp_phy_comp = true;
 
 	return test_result;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0d0cb692f701..b1274ecffc7f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -120,6 +120,8 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
+void intel_dp_process_phy_request(struct intel_dp *intel_dp);
+
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0781b6326b8c..e14cae4039a1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1286,6 +1286,8 @@ struct drm_i915_private {
 
 	I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
 
+	bool dp_phy_comp;
+
 	/*
 	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
 	 * will be rejected. Instead look for a better place.
-- 
2.24.0

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[Intel-gfx] [PATCH v2 9/9] drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern

[Animesh Manna]

This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.

Note: FIXME tag added as design discusion is ongoing in previous patch
series. Some temporary fix added and the patch is under-development, not for
review.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 24 ++++++-
 drivers/gpu/drm/i915/display/intel_dp.c      | 74 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h      |  2 +
 drivers/gpu/drm/i915/i915_drv.h              |  2 +
 4 files changed, 101 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e18ee1f17d6e..2d58ed249452 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14084,6 +14084,9 @@ static int intel_atomic_check(struct drm_device *dev,
 	int ret, i;
 	bool any_ms = false;
 
+	if (dev_priv->dp_phy_comp)
+		return 0;
+
 	/* Catch I915_MODE_FLAG_INHERITED */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
@@ -14692,10 +14695,23 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_crtc *crtc;
+	const struct drm_connector_state *conn_state;
+	struct drm_connector *conn;
 	u64 put_domains[I915_MAX_PIPES] = {};
 	intel_wakeref_t wakeref = 0;
 	int i;
 
+	if(dev_priv->dp_phy_comp) {
+		for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+			struct intel_encoder *encoder =
+				to_intel_encoder(conn_state->best_encoder);
+			struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+			intel_dp_process_phy_request(intel_dp);
+		}
+		goto dp_phy_comp1;
+	}
+
 	intel_atomic_commit_fence_wait(state);
 
 	drm_atomic_helper_wait_for_dependencies(&state->base);
@@ -14830,6 +14846,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	if (state->modeset && intel_can_enable_sagv(state))
 		intel_enable_sagv(dev_priv);
 
+dp_phy_comp1:
 	drm_atomic_helper_commit_hw_done(&state->base);
 
 	if (state->modeset) {
@@ -14921,6 +14938,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
 	drm_atomic_state_get(&state->base);
+	if (!dev_priv->dp_phy_comp) {
 	i915_sw_fence_init(&state->commit_ready,
 			   intel_atomic_commit_ready);
 
@@ -14959,11 +14977,13 @@ static int intel_atomic_commit(struct drm_device *dev,
 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
 		return ret;
 	}
+	}
 
 	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
 	if (!ret)
 		ret = drm_atomic_helper_swap_state(&state->base, true);
 
+	if (!dev_priv->dp_phy_comp) {
 	if (ret) {
 		i915_sw_fence_commit(&state->commit_ready);
 
@@ -14974,6 +14994,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 	dev_priv->wm.distrust_bios_wm = false;
 	intel_shared_dpll_swap_state(state);
 	intel_atomic_track_fbs(state);
+	}
 
 	if (state->global_state_changed) {
 		assert_global_state_locked(dev_priv);
@@ -14990,8 +15011,9 @@ static int intel_atomic_commit(struct drm_device *dev,
 
 	drm_atomic_state_get(&state->base);
 	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
-
+	if (!dev_priv->dp_phy_comp) {
 	i915_sw_fence_commit(&state->commit_ready);
+	}
 	if (nonblock && state->modeset) {
 		queue_work(dev_priv->modeset_wq, &state->base.commit_work);
 	} else if (nonblock) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f38929db1f2e..4b4fa9074d18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5058,9 +5058,82 @@ static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 	}
 }
 
+static void
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum port port = intel_dig_port->base.port;
+	u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+	ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+	dp_tp_ctl_value = I915_READ(TGL_DP_TP_CTL(port));
+	trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+	ddi_buf_ctl_value        &= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK);
+	dp_tp_ctl_value          &= ~DP_TP_CTL_ENABLE;
+	trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
+				      DDI_PORT_WIDTH_MASK);
+
+	I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+	I915_WRITE(TGL_DP_TP_CTL(port), dp_tp_ctl_value);
+	I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+}
+
+static void
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum port port = intel_dig_port->base.port;
+	u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+	ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+	dp_tp_ctl_value = I915_READ(TGL_DP_TP_CTL(port));
+	trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+	ddi_buf_ctl_value |= DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH(lane_cnt);
+	dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
+	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
+				    DDI_PORT_WIDTH(lane_cnt);
+
+	I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+	I915_WRITE(TGL_DP_TP_CTL(port), dp_tp_ctl_value);
+	I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+}
+
+void intel_dp_process_phy_request(struct intel_dp *intel_dp)
+{
+	struct drm_dp_phy_test_params *data =
+		&intel_dp->compliance.test_data.phytest;
+	u8 link_status[DP_LINK_STATUS_SIZE];
+
+	if (!intel_dp_get_link_status(intel_dp, link_status)) {
+		DRM_DEBUG_KMS("failed to get link status\n");
+		return;
+	}
+
+	/* retrieve vswing & pre-emphasis setting */
+	intel_get_adjust_train(intel_dp, link_status);
+
+	intel_dp_autotest_phy_ddi_disable(intel_dp);
+
+	intel_dp_set_signal_levels(intel_dp);
+
+	intel_dp_phy_pattern_update(intel_dp);
+
+	intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
+
+	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
+				    link_status[DP_DPCD_REV]);
+}
+
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
 	u8 test_result = DP_TEST_NAK;
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
 	test_result = intel_dp_prepare_phytest(intel_dp);
 	if (test_result != DP_TEST_ACK)
@@ -5068,6 +5141,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 
 	/* Set test active flag here so userspace doesn't interrupt things */
 	intel_dp->compliance.test_active = 1;
+	dev_priv->dp_phy_comp = true;
 
 	return test_result;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0d0cb692f701..b1274ecffc7f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -120,6 +120,8 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
+void intel_dp_process_phy_request(struct intel_dp *intel_dp);
+
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0781b6326b8c..e14cae4039a1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1286,6 +1286,8 @@ struct drm_i915_private {
 
 	I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
 
+	bool dp_phy_comp;
+
 	/*
 	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
 	 * will be rejected. Instead look for a better place.
-- 
2.24.0

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Re: [PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Harry Wentland]

On 2019-12-18 10:13 a.m., Animesh Manna wrote:
> [Why]:
> Aligh with DP spec wanted to follow same naming convention.
> 
> [How]:
> Changed the macro name of the dpcd address used for getting requested
> test-pattern.
> 

Please roll this into your patch that renames the definition. All
patches should compile on their own.

Thanks,
Harry

> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 42aa889fd0f5..1a6109be2fce 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
>  	/* get phy test pattern and pattern parameters from DP receiver */
>  	core_link_read_dpcd(
>  			link,
> -			DP_TEST_PHY_PATTERN,
> +			DP_PHY_TEST_PATTERN,
>  			&dpcd_test_pattern.raw,
>  			sizeof(dpcd_test_pattern));
>  	core_link_read_dpcd(
> 
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Re: [Intel-gfx] [PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Harry Wentland]

On 2019-12-18 10:13 a.m., Animesh Manna wrote:
> [Why]:
> Aligh with DP spec wanted to follow same naming convention.
> 
> [How]:
> Changed the macro name of the dpcd address used for getting requested
> test-pattern.
> 

Please roll this into your patch that renames the definition. All
patches should compile on their own.

Thanks,
Harry

> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 42aa889fd0f5..1a6109be2fce 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
>  	/* get phy test pattern and pattern parameters from DP receiver */
>  	core_link_read_dpcd(
>  			link,
> -			DP_TEST_PHY_PATTERN,
> +			DP_PHY_TEST_PATTERN,
>  			&dpcd_test_pattern.raw,
>  			sizeof(dpcd_test_pattern));
>  	core_link_read_dpcd(
> 
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Re: [PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Manna, Animesh]

On 18-12-2019 21:12, Harry Wentland wrote:
> On 2019-12-18 10:13 a.m., Animesh Manna wrote:
>> [Why]:
>> Aligh with DP spec wanted to follow same naming convention.
>>
>> [How]:
>> Changed the macro name of the dpcd address used for getting requested
>> test-pattern.
>>
> Please roll this into your patch that renames the definition. All
> patches should compile on their own.


Thanks Harry for review, wanted to follow similar commit-description 
format followed in amd-driver compare to i915 and created a separate 
patch. Maybe is it good idea to change the patch sequence and make it as 
first patch.

Regards,
Animesh

>
> Thanks,
> Harry
>
>> Cc: Harry Wentland <harry.wentland@amd.com>
>> Cc: Alex Deucher <alexander.deucher@amd.com>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> index 42aa889fd0f5..1a6109be2fce 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> @@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
>>   	/* get phy test pattern and pattern parameters from DP receiver */
>>   	core_link_read_dpcd(
>>   			link,
>> -			DP_TEST_PHY_PATTERN,
>> +			DP_PHY_TEST_PATTERN,
>>   			&dpcd_test_pattern.raw,
>>   			sizeof(dpcd_test_pattern));
>>   	core_link_read_dpcd(
>>
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Re: [Intel-gfx] [PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Manna, Animesh]

On 18-12-2019 21:12, Harry Wentland wrote:
> On 2019-12-18 10:13 a.m., Animesh Manna wrote:
>> [Why]:
>> Aligh with DP spec wanted to follow same naming convention.
>>
>> [How]:
>> Changed the macro name of the dpcd address used for getting requested
>> test-pattern.
>>
> Please roll this into your patch that renames the definition. All
> patches should compile on their own.


Thanks Harry for review, wanted to follow similar commit-description 
format followed in amd-driver compare to i915 and created a separate 
patch. Maybe is it good idea to change the patch sequence and make it as 
first patch.

Regards,
Animesh

>
> Thanks,
> Harry
>
>> Cc: Harry Wentland <harry.wentland@amd.com>
>> Cc: Alex Deucher <alexander.deucher@amd.com>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> index 42aa889fd0f5..1a6109be2fce 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> @@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
>>   	/* get phy test pattern and pattern parameters from DP receiver */
>>   	core_link_read_dpcd(
>>   			link,
>> -			DP_TEST_PHY_PATTERN,
>> +			DP_PHY_TEST_PATTERN,
>>   			&dpcd_test_pattern.raw,
>>   			sizeof(dpcd_test_pattern));
>>   	core_link_read_dpcd(
>>
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Re: [PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Harry Wentland]

On 2019-12-18 11:13 a.m., Manna, Animesh wrote:
> 
> On 18-12-2019 21:12, Harry Wentland wrote:
>> On 2019-12-18 10:13 a.m., Animesh Manna wrote:
>>> [Why]:
>>> Aligh with DP spec wanted to follow same naming convention.
>>>
>>> [How]:
>>> Changed the macro name of the dpcd address used for getting requested
>>> test-pattern.
>>>
>> Please roll this into your patch that renames the definition. All
>> patches should compile on their own.
> 
> 
> Thanks Harry for review, wanted to follow similar commit-description
> format followed in amd-driver compare to i915 and created a separate
> patch. Maybe is it good idea to change the patch sequence and make it as
> first patch.
> 

Thanks for looking to follow the commit style from the rest of the amd
driver but in this case we need to combine them or you'll be left with
one patch in the sequence that won't build on its own.

Harry

> Regards,
> Animesh
> 
>>
>> Thanks,
>> Harry
>>
>>> Cc: Harry Wentland <harry.wentland@amd.com>
>>> Cc: Alex Deucher <alexander.deucher@amd.com>
>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>> ---
>>>   drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> index 42aa889fd0f5..1a6109be2fce 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> @@ -2491,7 +2491,7 @@ static void
>>> dp_test_send_phy_test_pattern(struct dc_link *link)
>>>       /* get phy test pattern and pattern parameters from DP receiver */
>>>       core_link_read_dpcd(
>>>               link,
>>> -            DP_TEST_PHY_PATTERN,
>>> +            DP_PHY_TEST_PATTERN,
>>>               &dpcd_test_pattern.raw,
>>>               sizeof(dpcd_test_pattern));
>>>       core_link_read_dpcd(
>>>
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Re: [Intel-gfx] [PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Harry Wentland]

On 2019-12-18 11:13 a.m., Manna, Animesh wrote:
> 
> On 18-12-2019 21:12, Harry Wentland wrote:
>> On 2019-12-18 10:13 a.m., Animesh Manna wrote:
>>> [Why]:
>>> Aligh with DP spec wanted to follow same naming convention.
>>>
>>> [How]:
>>> Changed the macro name of the dpcd address used for getting requested
>>> test-pattern.
>>>
>> Please roll this into your patch that renames the definition. All
>> patches should compile on their own.
> 
> 
> Thanks Harry for review, wanted to follow similar commit-description
> format followed in amd-driver compare to i915 and created a separate
> patch. Maybe is it good idea to change the patch sequence and make it as
> first patch.
> 

Thanks for looking to follow the commit style from the rest of the amd
driver but in this case we need to combine them or you'll be left with
one patch in the sequence that won't build on its own.

Harry

> Regards,
> Animesh
> 
>>
>> Thanks,
>> Harry
>>
>>> Cc: Harry Wentland <harry.wentland@amd.com>
>>> Cc: Alex Deucher <alexander.deucher@amd.com>
>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>> ---
>>>   drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> index 42aa889fd0f5..1a6109be2fce 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> @@ -2491,7 +2491,7 @@ static void
>>> dp_test_send_phy_test_pattern(struct dc_link *link)
>>>       /* get phy test pattern and pattern parameters from DP receiver */
>>>       core_link_read_dpcd(
>>>               link,
>>> -            DP_TEST_PHY_PATTERN,
>>> +            DP_PHY_TEST_PATTERN,
>>>               &dpcd_test_pattern.raw,
>>>               sizeof(dpcd_test_pattern));
>>>       core_link_read_dpcd(
>>>
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DP Phy compliance auto test

[Patchwork]

== Series Details ==

Series: DP Phy compliance auto test
URL   : https://patchwork.freedesktop.org/series/71121/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b177259a3656 drm/dp: get/set phy compliance pattern
701d1cb86d03 drm/amd/display: Fix compilation issue.
b553ef602d04 drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
0f5e33d5d6c0 drm/i915/dp: Preparation for DP phy compliance auto test
391d0f4e1225 drm/i915/dsb: Send uevent to testapp.
5ba33dc9aa02 drm/i915/dp: Add debugfs entry for DP phy compliance.
ee3972d67e5d drm/i915/dp: Register definition for DP compliance register
644f91780a71 drm/i915/dp: Update the pattern as per request
c81ef6762f12 drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
series. Some temporary fix added and the patch is under-development, not for

-:40: ERROR:SPACING: space required before the open parenthesis '('
#40: FILE: drivers/gpu/drm/i915/display/intel_display.c:14670:
+	if(dev_priv->dp_phy_comp) {

-:66: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 8)
#66: FILE: drivers/gpu/drm/i915/display/intel_display.c:14907:
+	if (!dev_priv->dp_phy_comp) {
 	i915_sw_fence_init(&state->commit_ready,

-:80: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 8)
#80: FILE: drivers/gpu/drm/i915/display/intel_display.c:14952:
+	if (!dev_priv->dp_phy_comp) {
 	if (ret) {

-:97: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 8)
#97: FILE: drivers/gpu/drm/i915/display/intel_display.c:14980:
+	if (!dev_priv->dp_phy_comp) {
 	i915_sw_fence_commit(&state->commit_ready);

-:97: WARNING:BRACES: braces {} are not necessary for single statement blocks
#97: FILE: drivers/gpu/drm/i915/display/intel_display.c:14980:
+	if (!dev_priv->dp_phy_comp) {
 	i915_sw_fence_commit(&state->commit_ready);
+	}

total: 1 errors, 5 warnings, 0 checks, 181 lines checked

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DP Phy compliance auto test

[Patchwork]

== Series Details ==

Series: DP Phy compliance auto test
URL   : https://patchwork.freedesktop.org/series/71121/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test

[Patchwork]

== Series Details ==

Series: DP Phy compliance auto test
URL   : https://patchwork.freedesktop.org/series/71121/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7599 -> Patchwork_15828
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/index.html

Known issues
------------

  Here are the changes found in Patchwork_15828 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770r:       [PASS][1] -> [DMESG-FAIL][2] ([i915#725])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-hsw-4770r/igt@i915_selftest@live_blt.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/fi-hsw-4770r/igt@i915_selftest@live_blt.html
    - fi-bsw-n3050:       [PASS][3] -> [DMESG-FAIL][4] ([i915#723])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-bsw-n3050/igt@i915_selftest@live_blt.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/fi-bsw-n3050/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-byt-j1900:       [PASS][5] -> [INCOMPLETE][6] ([i915#45])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@gem_exec_gttfill@basic:
    - {fi-tgl-u}:         [INCOMPLETE][7] ([fdo#111593]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-tgl-u/igt@gem_exec_gttfill@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/fi-tgl-u/igt@gem_exec_gttfill@basic.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770:        [DMESG-FAIL][9] ([i915#725]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/fi-hsw-4770/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-cfl-8700k:       [INCOMPLETE][11] ([i915#424]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-kbl-x1275:       [DMESG-WARN][13] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([fdo#107139] / [i915#62] / [i915#92])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - fi-kbl-x1275:       [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +5 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-kbl-x1275:       [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
  [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
  [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
  [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#723]: https://gitlab.freedesktop.org/drm/intel/issues/723
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (48 -> 40)
------------------------------

  Additional (2): fi-snb-2520m fi-kbl-7500u 
  Missing    (10): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-pnv-d510 fi-elk-e7500 fi-bsw-kefka fi-blb-e6850 fi-tgl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7599 -> Patchwork_15828

  CI-20190529: 20190529
  CI_DRM_7599: 03dfaf2e5f39b632d0187544f3c988b8596f11b0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5351: e7fdcef72d1d6b3bb9f3003bbc37571959e6e8bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15828: c81ef6762f122c61a6d7c3dbda225430fdb7db7b @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c81ef6762f12 drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern
644f91780a71 drm/i915/dp: Update the pattern as per request
ee3972d67e5d drm/i915/dp: Register definition for DP compliance register
5ba33dc9aa02 drm/i915/dp: Add debugfs entry for DP phy compliance.
391d0f4e1225 drm/i915/dsb: Send uevent to testapp.
0f5e33d5d6c0 drm/i915/dp: Preparation for DP phy compliance auto test
b553ef602d04 drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
701d1cb86d03 drm/amd/display: Fix compilation issue.
b177259a3656 drm/dp: get/set phy compliance pattern

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/index.html
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Re: [PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Manasi Navare]

On Wed, Dec 18, 2019 at 09:43:49PM +0530, Manna, Animesh wrote:
> 
> On 18-12-2019 21:12, Harry Wentland wrote:
> >On 2019-12-18 10:13 a.m., Animesh Manna wrote:
> >>[Why]:
> >>Aligh with DP spec wanted to follow same naming convention.
> >>
> >>[How]:
> >>Changed the macro name of the dpcd address used for getting requested
> >>test-pattern.
> >>
> >Please roll this into your patch that renames the definition. All
> >patches should compile on their own.
> 
> 
> Thanks Harry for review, wanted to follow similar commit-description format
> followed in amd-driver compare to i915 and created a separate patch. Maybe
> is it good idea to change the patch sequence and make it as first patch.
> 
> Regards,
> Animesh

Like Harry said, all these changes should happen in the same patch that renames the DP_TEST_PHY_PATTERN
which is patch 1/9 because like you see the build still fails now since patch 1 doesnt compile.

So the idea would be in patch 1 - rename, make changes in AMD and existing place where it gets used
Patch 2 - get/set PHY test paarams that use this renamed value

Manasi

> 
> >
> >Thanks,
> >Harry
> >
> >>Cc: Harry Wentland <harry.wentland@amd.com>
> >>Cc: Alex Deucher <alexander.deucher@amd.com>
> >>Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >>---
> >>  drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> >>index 42aa889fd0f5..1a6109be2fce 100644
> >>--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> >>+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> >>@@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
> >>  	/* get phy test pattern and pattern parameters from DP receiver */
> >>  	core_link_read_dpcd(
> >>  			link,
> >>-			DP_TEST_PHY_PATTERN,
> >>+			DP_PHY_TEST_PATTERN,
> >>  			&dpcd_test_pattern.raw,
> >>  			sizeof(dpcd_test_pattern));
> >>  	core_link_read_dpcd(
> >>
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Re: [Intel-gfx] [PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Manasi Navare]

On Wed, Dec 18, 2019 at 09:43:49PM +0530, Manna, Animesh wrote:
> 
> On 18-12-2019 21:12, Harry Wentland wrote:
> >On 2019-12-18 10:13 a.m., Animesh Manna wrote:
> >>[Why]:
> >>Aligh with DP spec wanted to follow same naming convention.
> >>
> >>[How]:
> >>Changed the macro name of the dpcd address used for getting requested
> >>test-pattern.
> >>
> >Please roll this into your patch that renames the definition. All
> >patches should compile on their own.
> 
> 
> Thanks Harry for review, wanted to follow similar commit-description format
> followed in amd-driver compare to i915 and created a separate patch. Maybe
> is it good idea to change the patch sequence and make it as first patch.
> 
> Regards,
> Animesh

Like Harry said, all these changes should happen in the same patch that renames the DP_TEST_PHY_PATTERN
which is patch 1/9 because like you see the build still fails now since patch 1 doesnt compile.

So the idea would be in patch 1 - rename, make changes in AMD and existing place where it gets used
Patch 2 - get/set PHY test paarams that use this renamed value

Manasi

> 
> >
> >Thanks,
> >Harry
> >
> >>Cc: Harry Wentland <harry.wentland@amd.com>
> >>Cc: Alex Deucher <alexander.deucher@amd.com>
> >>Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >>---
> >>  drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> >>index 42aa889fd0f5..1a6109be2fce 100644
> >>--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> >>+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> >>@@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
> >>  	/* get phy test pattern and pattern parameters from DP receiver */
> >>  	core_link_read_dpcd(
> >>  			link,
> >>-			DP_TEST_PHY_PATTERN,
> >>+			DP_PHY_TEST_PATTERN,
> >>  			&dpcd_test_pattern.raw,
> >>  			sizeof(dpcd_test_pattern));
> >>  	core_link_read_dpcd(
> >>
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Re: [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Jani Nikula]

On Wed, 18 Dec 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> vswing/pre-emphasis adjustment calculation is needed in processing
> of auto phy compliance request other than link training, so moved
> the same function in intel_dp.c.
>
> No functional change.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
>  .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
>  3 files changed, 35 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2f31d226c6eb..ca82835b6dcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
>  	}
>  }
>  
> +void
> +intel_get_adjust_train(struct intel_dp *intel_dp,

Please follow the naming convention of prefixing non-static functions in
foo.c with foo_. I.e. intel_dp_ here.

BR,
Jani.

> +		       const u8 *link_status)
> +{
> +	u8 v = 0;
> +	u8 p = 0;
> +	int lane;
> +	u8 voltage_max;
> +	u8 preemph_max;
> +
> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> +		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> +		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> +
> +		if (this_v > v)
> +			v = this_v;
> +		if (this_p > p)
> +			p = this_p;
> +	}
> +
> +	voltage_max = intel_dp_voltage_max(intel_dp);
> +	if (v >= voltage_max)
> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> +
> +	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> +	if (p >= preemph_max)
> +		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> +
> +	for (lane = 0; lane < 4; lane++)
> +		intel_dp->train_set[lane] = v | p;
> +}
> +
>  void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3da166054788..0d0cb692f701 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -91,6 +91,9 @@ void
>  intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>  				       u8 dp_train_pat);
>  void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> +		       const u8 *link_status);
> +void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>  void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
>  u8
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2a1130dd1ad0..1e38584e7d56 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>  		      link_status[3], link_status[4], link_status[5]);
>  }
>  
> -static void
> -intel_get_adjust_train(struct intel_dp *intel_dp,
> -		       const u8 link_status[DP_LINK_STATUS_SIZE])
> -{
> -	u8 v = 0;
> -	u8 p = 0;
> -	int lane;
> -	u8 voltage_max;
> -	u8 preemph_max;
> -
> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> -
> -		if (this_v > v)
> -			v = this_v;
> -		if (this_p > p)
> -			p = this_p;
> -	}
> -
> -	voltage_max = intel_dp_voltage_max(intel_dp);
> -	if (v >= voltage_max)
> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> -
> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> -	if (p >= preemph_max)
> -		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> -
> -	for (lane = 0; lane < 4; lane++)
> -		intel_dp->train_set[lane] = v | p;
> -}
> -
>  static bool
>  intel_dp_set_link_train(struct intel_dp *intel_dp,
>  			u8 dp_train_pat)

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Jani Nikula]

On Wed, 18 Dec 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> vswing/pre-emphasis adjustment calculation is needed in processing
> of auto phy compliance request other than link training, so moved
> the same function in intel_dp.c.
>
> No functional change.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
>  .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
>  3 files changed, 35 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2f31d226c6eb..ca82835b6dcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
>  	}
>  }
>  
> +void
> +intel_get_adjust_train(struct intel_dp *intel_dp,

Please follow the naming convention of prefixing non-static functions in
foo.c with foo_. I.e. intel_dp_ here.

BR,
Jani.

> +		       const u8 *link_status)
> +{
> +	u8 v = 0;
> +	u8 p = 0;
> +	int lane;
> +	u8 voltage_max;
> +	u8 preemph_max;
> +
> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> +		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> +		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> +
> +		if (this_v > v)
> +			v = this_v;
> +		if (this_p > p)
> +			p = this_p;
> +	}
> +
> +	voltage_max = intel_dp_voltage_max(intel_dp);
> +	if (v >= voltage_max)
> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> +
> +	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> +	if (p >= preemph_max)
> +		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> +
> +	for (lane = 0; lane < 4; lane++)
> +		intel_dp->train_set[lane] = v | p;
> +}
> +
>  void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3da166054788..0d0cb692f701 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -91,6 +91,9 @@ void
>  intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>  				       u8 dp_train_pat);
>  void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> +		       const u8 *link_status);
> +void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>  void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
>  u8
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2a1130dd1ad0..1e38584e7d56 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>  		      link_status[3], link_status[4], link_status[5]);
>  }
>  
> -static void
> -intel_get_adjust_train(struct intel_dp *intel_dp,
> -		       const u8 link_status[DP_LINK_STATUS_SIZE])
> -{
> -	u8 v = 0;
> -	u8 p = 0;
> -	int lane;
> -	u8 voltage_max;
> -	u8 preemph_max;
> -
> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> -
> -		if (this_v > v)
> -			v = this_v;
> -		if (this_p > p)
> -			p = this_p;
> -	}
> -
> -	voltage_max = intel_dp_voltage_max(intel_dp);
> -	if (v >= voltage_max)
> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> -
> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> -	if (p >= preemph_max)
> -		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> -
> -	for (lane = 0; lane < 4; lane++)
> -		intel_dp->train_set[lane] = v | p;
> -}
> -
>  static bool
>  intel_dp_set_link_train(struct intel_dp *intel_dp,
>  			u8 dp_train_pat)

-- 
Jani Nikula, Intel Open Source Graphics Center
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Ville Syrjälä]

On Wed, Dec 18, 2019 at 08:43:44PM +0530, Animesh Manna wrote:
> vswing/pre-emphasis adjustment calculation is needed in processing
> of auto phy compliance request other than link training, so moved
> the same function in intel_dp.c.
> 
> No functional change.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
>  .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
>  3 files changed, 35 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2f31d226c6eb..ca82835b6dcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
>  	}
>  }
>  
> +void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> +		       const u8 *link_status)

I'd prefer to keep the arrayish notation so we have some idea how big
this is supposed to be. I guess that woukld mean including some
drm dp header in intel_dp.h?

> +{
> +	u8 v = 0;
> +	u8 p = 0;
> +	int lane;
> +	u8 voltage_max;
> +	u8 preemph_max;
> +
> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> +		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> +		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> +
> +		if (this_v > v)
> +			v = this_v;
> +		if (this_p > p)
> +			p = this_p;
> +	}
> +
> +	voltage_max = intel_dp_voltage_max(intel_dp);
> +	if (v >= voltage_max)
> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> +
> +	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> +	if (p >= preemph_max)
> +		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> +
> +	for (lane = 0; lane < 4; lane++)
> +		intel_dp->train_set[lane] = v | p;
> +}
> +
>  void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3da166054788..0d0cb692f701 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -91,6 +91,9 @@ void
>  intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>  				       u8 dp_train_pat);
>  void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> +		       const u8 *link_status);
> +void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>  void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
>  u8
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2a1130dd1ad0..1e38584e7d56 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>  		      link_status[3], link_status[4], link_status[5]);
>  }
>  
> -static void
> -intel_get_adjust_train(struct intel_dp *intel_dp,
> -		       const u8 link_status[DP_LINK_STATUS_SIZE])
> -{
> -	u8 v = 0;
> -	u8 p = 0;
> -	int lane;
> -	u8 voltage_max;
> -	u8 preemph_max;
> -
> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> -
> -		if (this_v > v)
> -			v = this_v;
> -		if (this_p > p)
> -			p = this_p;
> -	}
> -
> -	voltage_max = intel_dp_voltage_max(intel_dp);
> -	if (v >= voltage_max)
> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> -
> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> -	if (p >= preemph_max)
> -		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> -
> -	for (lane = 0; lane < 4; lane++)
> -		intel_dp->train_set[lane] = v | p;
> -}
> -
>  static bool
>  intel_dp_set_link_train(struct intel_dp *intel_dp,
>  			u8 dp_train_pat)
> -- 
> 2.24.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Ville Syrjälä]

On Wed, Dec 18, 2019 at 08:43:44PM +0530, Animesh Manna wrote:
> vswing/pre-emphasis adjustment calculation is needed in processing
> of auto phy compliance request other than link training, so moved
> the same function in intel_dp.c.
> 
> No functional change.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
>  .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
>  3 files changed, 35 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2f31d226c6eb..ca82835b6dcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
>  	}
>  }
>  
> +void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> +		       const u8 *link_status)

I'd prefer to keep the arrayish notation so we have some idea how big
this is supposed to be. I guess that woukld mean including some
drm dp header in intel_dp.h?

> +{
> +	u8 v = 0;
> +	u8 p = 0;
> +	int lane;
> +	u8 voltage_max;
> +	u8 preemph_max;
> +
> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> +		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> +		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> +
> +		if (this_v > v)
> +			v = this_v;
> +		if (this_p > p)
> +			p = this_p;
> +	}
> +
> +	voltage_max = intel_dp_voltage_max(intel_dp);
> +	if (v >= voltage_max)
> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> +
> +	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> +	if (p >= preemph_max)
> +		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> +
> +	for (lane = 0; lane < 4; lane++)
> +		intel_dp->train_set[lane] = v | p;
> +}
> +
>  void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3da166054788..0d0cb692f701 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -91,6 +91,9 @@ void
>  intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>  				       u8 dp_train_pat);
>  void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> +		       const u8 *link_status);
> +void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>  void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
>  u8
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2a1130dd1ad0..1e38584e7d56 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>  		      link_status[3], link_status[4], link_status[5]);
>  }
>  
> -static void
> -intel_get_adjust_train(struct intel_dp *intel_dp,
> -		       const u8 link_status[DP_LINK_STATUS_SIZE])
> -{
> -	u8 v = 0;
> -	u8 p = 0;
> -	int lane;
> -	u8 voltage_max;
> -	u8 preemph_max;
> -
> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> -
> -		if (this_v > v)
> -			v = this_v;
> -		if (this_p > p)
> -			p = this_p;
> -	}
> -
> -	voltage_max = intel_dp_voltage_max(intel_dp);
> -	if (v >= voltage_max)
> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> -
> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> -	if (p >= preemph_max)
> -		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> -
> -	for (lane = 0; lane < 4; lane++)
> -		intel_dp->train_set[lane] = v | p;
> -}
> -
>  static bool
>  intel_dp_set_link_train(struct intel_dp *intel_dp,
>  			u8 dp_train_pat)
> -- 
> 2.24.0

-- 
Ville Syrjälä
Intel
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Manna, Animesh]

On 19-12-2019 16:21, Jani Nikula wrote:
> On Wed, 18 Dec 2019, Animesh Manna <animesh.manna@intel.com> wrote:
>> vswing/pre-emphasis adjustment calculation is needed in processing
>> of auto phy compliance request other than link training, so moved
>> the same function in intel_dp.c.
>>
>> No functional change.
>>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
>>   .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
>>   3 files changed, 35 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 2f31d226c6eb..ca82835b6dcf 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
>>   	}
>>   }
>>   
>> +void
>> +intel_get_adjust_train(struct intel_dp *intel_dp,
> Please follow the naming convention of prefixing non-static functions in
> foo.c with foo_. I.e. intel_dp_ here.

Sure, will do.

Regards,
Animesh

>
> BR,
> Jani.
>
>> +		       const u8 *link_status)
>> +{
>> +	u8 v = 0;
>> +	u8 p = 0;
>> +	int lane;
>> +	u8 voltage_max;
>> +	u8 preemph_max;
>> +
>> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> +		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>> +		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>> +
>> +		if (this_v > v)
>> +			v = this_v;
>> +		if (this_p > p)
>> +			p = this_p;
>> +	}
>> +
>> +	voltage_max = intel_dp_voltage_max(intel_dp);
>> +	if (v >= voltage_max)
>> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>> +
>> +	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>> +	if (p >= preemph_max)
>> +		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>> +
>> +	for (lane = 0; lane < 4; lane++)
>> +		intel_dp->train_set[lane] = v | p;
>> +}
>> +
>>   void
>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>>   {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 3da166054788..0d0cb692f701 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -91,6 +91,9 @@ void
>>   intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>>   				       u8 dp_train_pat);
>>   void
>> +intel_get_adjust_train(struct intel_dp *intel_dp,
>> +		       const u8 *link_status);
>> +void
>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>>   void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
>>   u8
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 2a1130dd1ad0..1e38584e7d56 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>>   		      link_status[3], link_status[4], link_status[5]);
>>   }
>>   
>> -static void
>> -intel_get_adjust_train(struct intel_dp *intel_dp,
>> -		       const u8 link_status[DP_LINK_STATUS_SIZE])
>> -{
>> -	u8 v = 0;
>> -	u8 p = 0;
>> -	int lane;
>> -	u8 voltage_max;
>> -	u8 preemph_max;
>> -
>> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>> -
>> -		if (this_v > v)
>> -			v = this_v;
>> -		if (this_p > p)
>> -			p = this_p;
>> -	}
>> -
>> -	voltage_max = intel_dp_voltage_max(intel_dp);
>> -	if (v >= voltage_max)
>> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>> -
>> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>> -	if (p >= preemph_max)
>> -		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>> -
>> -	for (lane = 0; lane < 4; lane++)
>> -		intel_dp->train_set[lane] = v | p;
>> -}
>> -
>>   static bool
>>   intel_dp_set_link_train(struct intel_dp *intel_dp,
>>   			u8 dp_train_pat)
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Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Manna, Animesh]

On 19-12-2019 16:21, Jani Nikula wrote:
> On Wed, 18 Dec 2019, Animesh Manna <animesh.manna@intel.com> wrote:
>> vswing/pre-emphasis adjustment calculation is needed in processing
>> of auto phy compliance request other than link training, so moved
>> the same function in intel_dp.c.
>>
>> No functional change.
>>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
>>   .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
>>   3 files changed, 35 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 2f31d226c6eb..ca82835b6dcf 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
>>   	}
>>   }
>>   
>> +void
>> +intel_get_adjust_train(struct intel_dp *intel_dp,
> Please follow the naming convention of prefixing non-static functions in
> foo.c with foo_. I.e. intel_dp_ here.

Sure, will do.

Regards,
Animesh

>
> BR,
> Jani.
>
>> +		       const u8 *link_status)
>> +{
>> +	u8 v = 0;
>> +	u8 p = 0;
>> +	int lane;
>> +	u8 voltage_max;
>> +	u8 preemph_max;
>> +
>> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> +		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>> +		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>> +
>> +		if (this_v > v)
>> +			v = this_v;
>> +		if (this_p > p)
>> +			p = this_p;
>> +	}
>> +
>> +	voltage_max = intel_dp_voltage_max(intel_dp);
>> +	if (v >= voltage_max)
>> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>> +
>> +	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>> +	if (p >= preemph_max)
>> +		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>> +
>> +	for (lane = 0; lane < 4; lane++)
>> +		intel_dp->train_set[lane] = v | p;
>> +}
>> +
>>   void
>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>>   {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 3da166054788..0d0cb692f701 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -91,6 +91,9 @@ void
>>   intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>>   				       u8 dp_train_pat);
>>   void
>> +intel_get_adjust_train(struct intel_dp *intel_dp,
>> +		       const u8 *link_status);
>> +void
>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>>   void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
>>   u8
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 2a1130dd1ad0..1e38584e7d56 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>>   		      link_status[3], link_status[4], link_status[5]);
>>   }
>>   
>> -static void
>> -intel_get_adjust_train(struct intel_dp *intel_dp,
>> -		       const u8 link_status[DP_LINK_STATUS_SIZE])
>> -{
>> -	u8 v = 0;
>> -	u8 p = 0;
>> -	int lane;
>> -	u8 voltage_max;
>> -	u8 preemph_max;
>> -
>> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>> -
>> -		if (this_v > v)
>> -			v = this_v;
>> -		if (this_p > p)
>> -			p = this_p;
>> -	}
>> -
>> -	voltage_max = intel_dp_voltage_max(intel_dp);
>> -	if (v >= voltage_max)
>> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>> -
>> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>> -	if (p >= preemph_max)
>> -		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>> -
>> -	for (lane = 0; lane < 4; lane++)
>> -		intel_dp->train_set[lane] = v | p;
>> -}
>> -
>>   static bool
>>   intel_dp_set_link_train(struct intel_dp *intel_dp,
>>   			u8 dp_train_pat)
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Re: [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Manna, Animesh]

On 19-12-2019 18:03, Ville Syrjälä wrote:
> On Wed, Dec 18, 2019 at 08:43:44PM +0530, Animesh Manna wrote:
>> vswing/pre-emphasis adjustment calculation is needed in processing
>> of auto phy compliance request other than link training, so moved
>> the same function in intel_dp.c.
>>
>> No functional change.
>>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
>>   .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
>>   3 files changed, 35 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 2f31d226c6eb..ca82835b6dcf 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
>>   	}
>>   }
>>   
>> +void
>> +intel_get_adjust_train(struct intel_dp *intel_dp,
>> +		       const u8 *link_status)
> I'd prefer to keep the arrayish notation so we have some idea how big
> this is supposed to be. I guess that woukld mean including some
> drm dp header in intel_dp.h?

Yes, will add.

Regards,
Animesh

>
>> +{
>> +	u8 v = 0;
>> +	u8 p = 0;
>> +	int lane;
>> +	u8 voltage_max;
>> +	u8 preemph_max;
>> +
>> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> +		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>> +		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>> +
>> +		if (this_v > v)
>> +			v = this_v;
>> +		if (this_p > p)
>> +			p = this_p;
>> +	}
>> +
>> +	voltage_max = intel_dp_voltage_max(intel_dp);
>> +	if (v >= voltage_max)
>> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>> +
>> +	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>> +	if (p >= preemph_max)
>> +		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>> +
>> +	for (lane = 0; lane < 4; lane++)
>> +		intel_dp->train_set[lane] = v | p;
>> +}
>> +
>>   void
>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>>   {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 3da166054788..0d0cb692f701 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -91,6 +91,9 @@ void
>>   intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>>   				       u8 dp_train_pat);
>>   void
>> +intel_get_adjust_train(struct intel_dp *intel_dp,
>> +		       const u8 *link_status);
>> +void
>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>>   void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
>>   u8
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 2a1130dd1ad0..1e38584e7d56 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>>   		      link_status[3], link_status[4], link_status[5]);
>>   }
>>   
>> -static void
>> -intel_get_adjust_train(struct intel_dp *intel_dp,
>> -		       const u8 link_status[DP_LINK_STATUS_SIZE])
>> -{
>> -	u8 v = 0;
>> -	u8 p = 0;
>> -	int lane;
>> -	u8 voltage_max;
>> -	u8 preemph_max;
>> -
>> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>> -
>> -		if (this_v > v)
>> -			v = this_v;
>> -		if (this_p > p)
>> -			p = this_p;
>> -	}
>> -
>> -	voltage_max = intel_dp_voltage_max(intel_dp);
>> -	if (v >= voltage_max)
>> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>> -
>> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>> -	if (p >= preemph_max)
>> -		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>> -
>> -	for (lane = 0; lane < 4; lane++)
>> -		intel_dp->train_set[lane] = v | p;
>> -}
>> -
>>   static bool
>>   intel_dp_set_link_train(struct intel_dp *intel_dp,
>>   			u8 dp_train_pat)
>> -- 
>> 2.24.0
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Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Manna, Animesh]

On 19-12-2019 18:03, Ville Syrjälä wrote:
> On Wed, Dec 18, 2019 at 08:43:44PM +0530, Animesh Manna wrote:
>> vswing/pre-emphasis adjustment calculation is needed in processing
>> of auto phy compliance request other than link training, so moved
>> the same function in intel_dp.c.
>>
>> No functional change.
>>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c       | 32 +++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dp.h       |  3 ++
>>   .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
>>   3 files changed, 35 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 2f31d226c6eb..ca82835b6dcf 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
>>   	}
>>   }
>>   
>> +void
>> +intel_get_adjust_train(struct intel_dp *intel_dp,
>> +		       const u8 *link_status)
> I'd prefer to keep the arrayish notation so we have some idea how big
> this is supposed to be. I guess that woukld mean including some
> drm dp header in intel_dp.h?

Yes, will add.

Regards,
Animesh

>
>> +{
>> +	u8 v = 0;
>> +	u8 p = 0;
>> +	int lane;
>> +	u8 voltage_max;
>> +	u8 preemph_max;
>> +
>> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> +		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>> +		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>> +
>> +		if (this_v > v)
>> +			v = this_v;
>> +		if (this_p > p)
>> +			p = this_p;
>> +	}
>> +
>> +	voltage_max = intel_dp_voltage_max(intel_dp);
>> +	if (v >= voltage_max)
>> +		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>> +
>> +	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>> +	if (p >= preemph_max)
>> +		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>> +
>> +	for (lane = 0; lane < 4; lane++)
>> +		intel_dp->train_set[lane] = v | p;
>> +}
>> +
>>   void
>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>>   {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 3da166054788..0d0cb692f701 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -91,6 +91,9 @@ void
>>   intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>>   				       u8 dp_train_pat);
>>   void
>> +intel_get_adjust_train(struct intel_dp *intel_dp,
>> +		       const u8 *link_status);
>> +void
>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp);
>>   void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
>>   u8
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 2a1130dd1ad0..1e38584e7d56 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
>>   		      link_status[3], link_status[4], link_status[5]);
>>   }
>>   
>> -static void
>> -intel_get_adjust_train(struct intel_dp *intel_dp,
>> -		       const u8 link_status[DP_LINK_STATUS_SIZE])
>> -{
>> -	u8 v = 0;
>> -	u8 p = 0;
>> -	int lane;
>> -	u8 voltage_max;
>> -	u8 preemph_max;
>> -
>> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> -		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>> -		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>> -
>> -		if (this_v > v)
>> -			v = this_v;
>> -		if (this_p > p)
>> -			p = this_p;
>> -	}
>> -
>> -	voltage_max = intel_dp_voltage_max(intel_dp);
>> -	if (v >= voltage_max)
>> -		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
>> -
>> -	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
>> -	if (p >= preemph_max)
>> -		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>> -
>> -	for (lane = 0; lane < 4; lane++)
>> -		intel_dp->train_set[lane] = v | p;
>> -}
>> -
>>   static bool
>>   intel_dp_set_link_train(struct intel_dp *intel_dp,
>>   			u8 dp_train_pat)
>> -- 
>> 2.24.0
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Re: [PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Manna, Animesh]

On 19-12-2019 05:23, Manasi Navare wrote:
> On Wed, Dec 18, 2019 at 09:43:49PM +0530, Manna, Animesh wrote:
>> On 18-12-2019 21:12, Harry Wentland wrote:
>>> On 2019-12-18 10:13 a.m., Animesh Manna wrote:
>>>> [Why]:
>>>> Aligh with DP spec wanted to follow same naming convention.
>>>>
>>>> [How]:
>>>> Changed the macro name of the dpcd address used for getting requested
>>>> test-pattern.
>>>>
>>> Please roll this into your patch that renames the definition. All
>>> patches should compile on their own.
>>
>> Thanks Harry for review, wanted to follow similar commit-description format
>> followed in amd-driver compare to i915 and created a separate patch. Maybe
>> is it good idea to change the patch sequence and make it as first patch.
>>
>> Regards,
>> Animesh
> Like Harry said, all these changes should happen in the same patch that renames the DP_TEST_PHY_PATTERN
> which is patch 1/9 because like you see the build still fails now since patch 1 doesnt compile.
>
> So the idea would be in patch 1 - rename, make changes in AMD and existing place where it gets used
> Patch 2 - get/set PHY test paarams that use this renamed value

Thanks Manasi. Yes, I want to mean the same.

Regards,
Animesh

>
> Manasi
>
>>> Thanks,
>>> Harry
>>>
>>>> Cc: Harry Wentland <harry.wentland@amd.com>
>>>> Cc: Alex Deucher <alexander.deucher@amd.com>
>>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
>>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>>> index 42aa889fd0f5..1a6109be2fce 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>>> @@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
>>>>   	/* get phy test pattern and pattern parameters from DP receiver */
>>>>   	core_link_read_dpcd(
>>>>   			link,
>>>> -			DP_TEST_PHY_PATTERN,
>>>> +			DP_PHY_TEST_PATTERN,
>>>>   			&dpcd_test_pattern.raw,
>>>>   			sizeof(dpcd_test_pattern));
>>>>   	core_link_read_dpcd(
>>>>
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Re: [Intel-gfx] [PATCH v2 2/9] drm/amd/display: Fix compilation issue.

[Manna, Animesh]

On 19-12-2019 05:23, Manasi Navare wrote:
> On Wed, Dec 18, 2019 at 09:43:49PM +0530, Manna, Animesh wrote:
>> On 18-12-2019 21:12, Harry Wentland wrote:
>>> On 2019-12-18 10:13 a.m., Animesh Manna wrote:
>>>> [Why]:
>>>> Aligh with DP spec wanted to follow same naming convention.
>>>>
>>>> [How]:
>>>> Changed the macro name of the dpcd address used for getting requested
>>>> test-pattern.
>>>>
>>> Please roll this into your patch that renames the definition. All
>>> patches should compile on their own.
>>
>> Thanks Harry for review, wanted to follow similar commit-description format
>> followed in amd-driver compare to i915 and created a separate patch. Maybe
>> is it good idea to change the patch sequence and make it as first patch.
>>
>> Regards,
>> Animesh
> Like Harry said, all these changes should happen in the same patch that renames the DP_TEST_PHY_PATTERN
> which is patch 1/9 because like you see the build still fails now since patch 1 doesnt compile.
>
> So the idea would be in patch 1 - rename, make changes in AMD and existing place where it gets used
> Patch 2 - get/set PHY test paarams that use this renamed value

Thanks Manasi. Yes, I want to mean the same.

Regards,
Animesh

>
> Manasi
>
>>> Thanks,
>>> Harry
>>>
>>>> Cc: Harry Wentland <harry.wentland@amd.com>
>>>> Cc: Alex Deucher <alexander.deucher@amd.com>
>>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
>>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>>> index 42aa889fd0f5..1a6109be2fce 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>>> @@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
>>>>   	/* get phy test pattern and pattern parameters from DP receiver */
>>>>   	core_link_read_dpcd(
>>>>   			link,
>>>> -			DP_TEST_PHY_PATTERN,
>>>> +			DP_PHY_TEST_PATTERN,
>>>>   			&dpcd_test_pattern.raw,
>>>>   			sizeof(dpcd_test_pattern));
>>>>   	core_link_read_dpcd(
>>>>
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[Intel-gfx] ✗ Fi.CI.IGT: failure for DP Phy compliance auto test

[Patchwork]

== Series Details ==

Series: DP Phy compliance auto test
URL   : https://patchwork.freedesktop.org/series/71121/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7599_full -> Patchwork_15828_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15828_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15828_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15828_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_ctx_shared@exec-shared-gtt-render:
    - shard-apl:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-apl6/igt@gem_ctx_shared@exec-shared-gtt-render.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-apl2/igt@gem_ctx_shared@exec-shared-gtt-render.html

  
New tests
---------

  New tests have been introduced between CI_DRM_7599_full and Patchwork_15828_full:

### New Piglit tests (6) ###

  * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 42 8 8 1:
    - Statuses : 1 fail(s)
    - Exec time: [12.78] s

  * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 42 8 8 3:
    - Statuses : 1 fail(s)
    - Exec time: [12.75] s

  * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 42 8 8 4:
    - Statuses : 1 fail(s)
    - Exec time: [12.71] s

  * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 42 8 8 7:
    - Statuses : 1 fail(s)
    - Exec time: [12.69] s

  * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_mat2_array3-position-double_dmat2x4_array2:
    - Statuses : 1 fail(s)
    - Exec time: [0.17] s

  * spec@sgis_generate_mipmap@gen-teximage:
    - Statuses : 1 fail(s)
    - Exec time: [4.53] s

  

Known issues
------------

  Here are the changes found in Patchwork_15828_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_shared@q-smoketest-bsd1:
    - shard-tglb:         [PASS][3] -> [INCOMPLETE][4] ([fdo#111735]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb9/igt@gem_ctx_shared@q-smoketest-bsd1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb3/igt@gem_ctx_shared@q-smoketest-bsd1.html

  * igt@gem_exec_parallel@vecs0:
    - shard-tglb:         [PASS][5] -> [INCOMPLETE][6] ([fdo#111736])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb4/igt@gem_exec_parallel@vecs0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb4/igt@gem_exec_parallel@vecs0.html

  * igt@gem_exec_schedule@smoketest-bsd2:
    - shard-tglb:         [PASS][7] -> [INCOMPLETE][8] ([i915#707])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb5/igt@gem_exec_schedule@smoketest-bsd2.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb3/igt@gem_exec_schedule@smoketest-bsd2.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-apl:          [PASS][9] -> [FAIL][10] ([i915#644])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-apl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-apl8/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-tglb:         [PASS][11] -> [INCOMPLETE][12] ([i915#456] / [i915#460]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb2/igt@i915_suspend@fence-restore-tiled2untiled.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb5/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([i915#54]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +3 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([i915#79]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([i915#34])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-skl4/igt@kms_flip@plain-flip-fb-recreate.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-skl6/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-tglb:         [PASS][21] -> [FAIL][22] ([i915#49])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-tglb:         [PASS][23] -> [DMESG-WARN][24] ([i915#766])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
    - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([i915#435] / [i915#667])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-iclb:         [PASS][27] -> [INCOMPLETE][28] ([i915#123] / [i915#140])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-iclb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-iclb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          [PASS][29] -> [INCOMPLETE][30] ([fdo#103665])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +7 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-kbl4/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vecs0-s3:
    - shard-tglb:         [INCOMPLETE][37] ([i915#456]) -> [PASS][38] +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb1/igt@gem_ctx_isolation@vecs0-s3.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb5/igt@gem_ctx_isolation@vecs0-s3.html

  * igt@gem_exec_create@forked:
    - shard-tglb:         [INCOMPLETE][39] ([fdo#108838] / [i915#435]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb5/igt@gem_exec_create@forked.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb2/igt@gem_exec_create@forked.html

  * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing:
    - shard-iclb:         [TIMEOUT][41] ([i915#530]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-iclb8/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-iclb8/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-snb:          [TIMEOUT][43] ([i915#530]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-snb5/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-snb6/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@gem_pipe_control_store_loop@reused-buffer:
    - shard-skl:          [TIMEOUT][45] ([fdo#111732]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-skl2/igt@gem_pipe_control_store_loop@reused-buffer.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-skl3/igt@gem_pipe_control_store_loop@reused-buffer.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [FAIL][47] ([i915#644]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [INCOMPLETE][49] ([i915#69]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-skl10/igt@gem_softpin@noreloc-s3.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-skl2/igt@gem_softpin@noreloc-s3.html

  * igt@gem_sync@basic-all:
    - shard-tglb:         [INCOMPLETE][51] ([i915#470] / [i915#472]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb3/igt@gem_sync@basic-all.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb4/igt@gem_sync@basic-all.html

  * igt@gem_sync@basic-store-each:
    - shard-tglb:         [INCOMPLETE][53] ([i915#435] / [i915#472]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb3/igt@gem_sync@basic-store-each.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb4/igt@gem_sync@basic-store-each.html

  * {igt@gen9_exec_parse@allowed-single}:
    - shard-apl:          [DMESG-WARN][55] ([i915#716]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-apl3/igt@gen9_exec_parse@allowed-single.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-apl3/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_pm_dc@dc5-dpms:
    - shard-iclb:         [FAIL][57] ([i915#447]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-iclb8/igt@i915_pm_dc@dc5-dpms.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding:
    - shard-skl:          [FAIL][61] ([i915#54]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
    - shard-hsw:          [DMESG-WARN][63] ([IGT#6]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-hsw6/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-hsw7/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html

  * igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
    - shard-skl:          [INCOMPLETE][65] -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-skl10/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-skl1/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-tglb:         [FAIL][67] ([i915#49]) -> [PASS][68] +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
    - shard-tglb:         [INCOMPLETE][69] ([i915#474] / [i915#667]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-tglb:         [INCOMPLETE][71] ([i915#456] / [i915#460] / [i915#474]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-tglb:         [INCOMPLETE][73] ([i915#456] / [i915#460]) -> [PASS][74] +4 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb5/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - shard-skl:          [INCOMPLETE][75] ([i915#648] / [i915#667]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-skl4/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-skl6/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs2-none:
    - shard-tglb:         [SKIP][77] ([fdo#111912] / [fdo#112080]) -> [SKIP][78] ([fdo#112080])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb4/igt@gem_ctx_isolation@vcs2-none.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb9/igt@gem_ctx_isolation@vcs2-none.html

  * igt@gem_ctx_isolation@vcs2-nonpriv-switch:
    - shard-tglb:         [SKIP][79] ([fdo#112080]) -> [SKIP][80] ([fdo#111912] / [fdo#112080])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb9/igt@gem_ctx_isolation@vcs2-nonpriv-switch.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb3/igt@gem_ctx_isolation@vcs2-nonpriv-switch.html

  * igt@kms_atomic_transition@6x-modeset-transitions-nonblocking:
    - shard-tglb:         [SKIP][81] ([fdo#112021]) -> [SKIP][82] ([fdo#112016] / [fdo#112021])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb9/igt@kms_atomic_transition@6x-modeset-transitions-nonblocking.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb3/igt@kms_atomic_transition@6x-modeset-transitions-nonblocking.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-tglb:         [INCOMPLETE][83] ([i915#474] / [i915#667]) -> [FAIL][84] ([i915#49])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_plane@pixel-format-pipe-b-planes:
    - shard-skl:          [INCOMPLETE][85] ([i915#648]) -> [INCOMPLETE][86] ([i915#648] / [i915#667])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-skl1/igt@kms_plane@pixel-format-pipe-b-planes.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-skl4/igt@kms_plane@pixel-format-pipe-b-planes.html

  * igt@kms_psr@psr2_suspend:
    - shard-tglb:         [INCOMPLETE][87] ([i915#456] / [i915#460]) -> [DMESG-WARN][88] ([i915#402])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/shard-tglb2/igt@kms_psr@psr2_suspend.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/shard-tglb2/igt@kms_psr@psr2_suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108838]: https://bugs.freedesktop.org/show_bug.cgi?id=108838
  [fdo#111732]: https://bugs.freedesktop.org/show_bug.cgi?id=111732
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#112016]: https://bugs.freedesktop.org/show_bug.cgi?id=112016
  [fdo#112021]: https://bugs.freedesktop.org/show_bug.cgi?id=112021
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
  [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
  [i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
  [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
  [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
  [i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
  [i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#766]: https://gitlab.freedesktop.org/drm/intel/issues/766
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Participating hosts (10 -> 11)
------------------------------

  Additional (1): pig-glk-j5005 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7599 -> Patchwork_15828

  CI-20190529: 20190529
  CI_DRM_7599: 03dfaf2e5f39b632d0187544f3c988b8596f11b0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5351: e7fdcef72d1d6b3bb9f3003bbc37571959e6e8bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15828: c81ef6762f122c61a6d7c3dbda225430fdb7db7b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15828/index.html
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[PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Animesh Manna]

vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.

No functional change.

v1: initial patch.
v2:
- used "intel_dp" prefix in function name. (Jani)
- used array notation instead pointer for link_status. (Ville)

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 34 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h       |  4 +++
 .../drm/i915/display/intel_dp_link_training.c | 32 -----------------
 3 files changed, 38 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2f31d226c6eb..4703e533feb3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4110,6 +4110,40 @@ ivb_cpu_edp_signal_levels(u8 train_set)
 	}
 }
 
+void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			  const u8 link_status[DP_LINK_STATUS_SIZE])
+{
+	u8 v = 0;
+	u8 p = 0;
+	int lane;
+	u8 voltage_max;
+	u8 preemph_max;
+
+	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+		u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
+							      lane);
+		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
+								   lane);
+
+		if (this_v > v)
+			v = this_v;
+		if (this_p > p)
+			p = this_p;
+	}
+
+	voltage_max = intel_dp_voltage_max(intel_dp);
+	if (v >= voltage_max)
+		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+	if (p >= preemph_max)
+		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+	for (lane = 0; lane < 4; lane++)
+		intel_dp->train_set[lane] = v | p;
+}
+
 void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..83eadc87af26 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -9,6 +9,7 @@
 #include <linux/types.h>
 
 #include <drm/i915_drm.h>
+#include <drm/drm_dp_helper.h>
 
 #include "i915_reg.h"
 
@@ -91,6 +92,9 @@ void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 				       u8 dp_train_pat);
 void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			  const u8 link_status[DP_LINK_STATUS_SIZE]);
+void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
 u8
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..1e38584e7d56 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
 		      link_status[3], link_status[4], link_status[5]);
 }
 
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
-		       const u8 link_status[DP_LINK_STATUS_SIZE])
-{
-	u8 v = 0;
-	u8 p = 0;
-	int lane;
-	u8 voltage_max;
-	u8 preemph_max;
-
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
-		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
-		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-
-		if (this_v > v)
-			v = this_v;
-		if (this_p > p)
-			p = this_p;
-	}
-
-	voltage_max = intel_dp_voltage_max(intel_dp);
-	if (v >= voltage_max)
-		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
-
-	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
-	if (p >= preemph_max)
-		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
-	for (lane = 0; lane < 4; lane++)
-		intel_dp->train_set[lane] = v | p;
-}
-
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
 			u8 dp_train_pat)
-- 
2.24.0

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[Intel-gfx] [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation

[Animesh Manna]

vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.

No functional change.

v1: initial patch.
v2:
- used "intel_dp" prefix in function name. (Jani)
- used array notation instead pointer for link_status. (Ville)

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 34 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h       |  4 +++
 .../drm/i915/display/intel_dp_link_training.c | 32 -----------------
 3 files changed, 38 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2f31d226c6eb..4703e533feb3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4110,6 +4110,40 @@ ivb_cpu_edp_signal_levels(u8 train_set)
 	}
 }
 
+void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			  const u8 link_status[DP_LINK_STATUS_SIZE])
+{
+	u8 v = 0;
+	u8 p = 0;
+	int lane;
+	u8 voltage_max;
+	u8 preemph_max;
+
+	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+		u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
+							      lane);
+		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
+								   lane);
+
+		if (this_v > v)
+			v = this_v;
+		if (this_p > p)
+			p = this_p;
+	}
+
+	voltage_max = intel_dp_voltage_max(intel_dp);
+	if (v >= voltage_max)
+		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+	if (p >= preemph_max)
+		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+	for (lane = 0; lane < 4; lane++)
+		intel_dp->train_set[lane] = v | p;
+}
+
 void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..83eadc87af26 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -9,6 +9,7 @@
 #include <linux/types.h>
 
 #include <drm/i915_drm.h>
+#include <drm/drm_dp_helper.h>
 
 #include "i915_reg.h"
 
@@ -91,6 +92,9 @@ void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 				       u8 dp_train_pat);
 void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			  const u8 link_status[DP_LINK_STATUS_SIZE]);
+void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
 u8
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..1e38584e7d56 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
 		      link_status[3], link_status[4], link_status[5]);
 }
 
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
-		       const u8 link_status[DP_LINK_STATUS_SIZE])
-{
-	u8 v = 0;
-	u8 p = 0;
-	int lane;
-	u8 voltage_max;
-	u8 preemph_max;
-
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
-		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
-		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-
-		if (this_v > v)
-			v = this_v;
-		if (this_p > p)
-			p = this_p;
-	}
-
-	voltage_max = intel_dp_voltage_max(intel_dp);
-	if (v >= voltage_max)
-		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
-
-	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
-	if (p >= preemph_max)
-		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
-	for (lane = 0; lane < 4; lane++)
-		intel_dp->train_set[lane] = v | p;
-}
-
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
 			u8 dp_train_pat)
-- 
2.24.0

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[PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec

[Animesh Manna]

[Why]:
Aligh with DP spec wanted to follow same naming convention.

[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 include/drm/drm_dp_helper.h                      | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 42aa889fd0f5..1a6109be2fce 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 	/* get phy test pattern and pattern parameters from DP receiver */
 	core_link_read_dpcd(
 			link,
-			DP_TEST_PHY_PATTERN,
+			DP_PHY_TEST_PATTERN,
 			&dpcd_test_pattern.raw,
 			sizeof(dpcd_test_pattern));
 	core_link_read_dpcd(
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 8f8f3632e697..d6e560870fb1 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -699,7 +699,7 @@
 # define DP_TEST_CRC_SUPPORTED		    (1 << 5)
 # define DP_TEST_COUNT_MASK		    0xf
 
-#define DP_TEST_PHY_PATTERN                 0x248
+#define DP_PHY_TEST_PATTERN                 0x248
 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
-- 
2.24.0

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[Intel-gfx] [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec

[Animesh Manna]

[Why]:
Aligh with DP spec wanted to follow same naming convention.

[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 include/drm/drm_dp_helper.h                      | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 42aa889fd0f5..1a6109be2fce 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 	/* get phy test pattern and pattern parameters from DP receiver */
 	core_link_read_dpcd(
 			link,
-			DP_TEST_PHY_PATTERN,
+			DP_PHY_TEST_PATTERN,
 			&dpcd_test_pattern.raw,
 			sizeof(dpcd_test_pattern));
 	core_link_read_dpcd(
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 8f8f3632e697..d6e560870fb1 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -699,7 +699,7 @@
 # define DP_TEST_CRC_SUPPORTED		    (1 << 5)
 # define DP_TEST_COUNT_MASK		    0xf
 
-#define DP_TEST_PHY_PATTERN                 0x248
+#define DP_PHY_TEST_PATTERN                 0x248
 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
-- 
2.24.0

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[PATCH v3 2/9] drm/dp: get/set phy compliance pattern

[Animesh Manna]

During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.

v2: As per review feedback from Manasi on RFC version,
- added dp revision as function argument in set_phy_pattern api.
- used int for link_rate and u8 for lane_count to align with existing code.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 93 +++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     | 31 +++++++++++
 2 files changed, 124 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2c7870aef469..91c80973aa83 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1371,3 +1371,96 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 	return num_bpc;
 }
 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data)
+{
+	int err;
+	u8 rate, lanes;
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
+	if (err < 0)
+		return err;
+	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
+	if (err < 0)
+		return err;
+	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
+
+	if (lanes & DP_ENHANCED_FRAME_CAP)
+		data->enahanced_frame_cap = true;
+
+	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
+	if (err < 0)
+		return err;
+
+	switch (data->phy_pattern) {
+	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+				       &data->custom80, 10);
+		if (err < 0)
+			return err;
+
+		break;
+	case DP_PHY_TEST_PATTERN_CP2520:
+		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+				       &data->hbr2_reset, 2);
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data, u8 dp_rev)
+{
+	int err, i;
+	u8 link_config[2];
+	u8 test_pattern;
+
+	link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
+	link_config[1] = data->num_lanes;
+	if (data->enahanced_frame_cap)
+		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
+	if (err < 0)
+		return err;
+
+	test_pattern = data->phy_pattern;
+	if (dp_rev < 0x12) {
+		test_pattern = (test_pattern << 2) &
+			       DP_LINK_QUAL_PATTERN_11_MASK;
+		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
+					 test_pattern);
+		if (err < 0)
+			return err;
+	} else {
+		for (i = 0; i < data->num_lanes; i++) {
+			err = drm_dp_dpcd_writeb(aux,
+						 DP_LINK_QUAL_LANE0_SET + i,
+						 test_pattern);
+			if (err < 0)
+				return err;
+		}
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index d6e560870fb1..42a364748308 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -700,6 +700,15 @@
 # define DP_TEST_COUNT_MASK		    0xf
 
 #define DP_PHY_TEST_PATTERN                 0x248
+# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
+# define DP_PHY_TEST_PATTERN_NONE           0x0
+# define DP_PHY_TEST_PATTERN_D10_2          0x1
+# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
+# define DP_PHY_TEST_PATTERN_PRBS7          0x3
+# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
+# define DP_PHY_TEST_PATTERN_CP2520         0x5
+
+#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
@@ -1570,4 +1579,26 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
 
 #endif
 
+/**
+ * struct drm_dp_phy_test_params - DP Phy Compliance parameters
+ * @link: Link information.
+ * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
+ * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
+ *            0x24A and 0x24B (sink)
+ * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
+ *               through 0x259.
+ */
+struct drm_dp_phy_test_params {
+	int link_rate;
+	u8 num_lanes;
+	u8 phy_pattern;
+	u8 hbr2_reset[2];
+	u8 custom80[10];
+	bool enahanced_frame_cap;
+};
+
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data);
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data, u8 dp_rev);
 #endif /* _DRM_DP_HELPER_H_ */
-- 
2.24.0

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[Intel-gfx] [PATCH v3 2/9] drm/dp: get/set phy compliance pattern

[Animesh Manna]

During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.

v2: As per review feedback from Manasi on RFC version,
- added dp revision as function argument in set_phy_pattern api.
- used int for link_rate and u8 for lane_count to align with existing code.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 93 +++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     | 31 +++++++++++
 2 files changed, 124 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2c7870aef469..91c80973aa83 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1371,3 +1371,96 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 	return num_bpc;
 }
 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data)
+{
+	int err;
+	u8 rate, lanes;
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
+	if (err < 0)
+		return err;
+	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
+	if (err < 0)
+		return err;
+	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
+
+	if (lanes & DP_ENHANCED_FRAME_CAP)
+		data->enahanced_frame_cap = true;
+
+	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
+	if (err < 0)
+		return err;
+
+	switch (data->phy_pattern) {
+	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+				       &data->custom80, 10);
+		if (err < 0)
+			return err;
+
+		break;
+	case DP_PHY_TEST_PATTERN_CP2520:
+		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+				       &data->hbr2_reset, 2);
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data, u8 dp_rev)
+{
+	int err, i;
+	u8 link_config[2];
+	u8 test_pattern;
+
+	link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
+	link_config[1] = data->num_lanes;
+	if (data->enahanced_frame_cap)
+		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
+	if (err < 0)
+		return err;
+
+	test_pattern = data->phy_pattern;
+	if (dp_rev < 0x12) {
+		test_pattern = (test_pattern << 2) &
+			       DP_LINK_QUAL_PATTERN_11_MASK;
+		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
+					 test_pattern);
+		if (err < 0)
+			return err;
+	} else {
+		for (i = 0; i < data->num_lanes; i++) {
+			err = drm_dp_dpcd_writeb(aux,
+						 DP_LINK_QUAL_LANE0_SET + i,
+						 test_pattern);
+			if (err < 0)
+				return err;
+		}
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index d6e560870fb1..42a364748308 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -700,6 +700,15 @@
 # define DP_TEST_COUNT_MASK		    0xf
 
 #define DP_PHY_TEST_PATTERN                 0x248
+# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
+# define DP_PHY_TEST_PATTERN_NONE           0x0
+# define DP_PHY_TEST_PATTERN_D10_2          0x1
+# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
+# define DP_PHY_TEST_PATTERN_PRBS7          0x3
+# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
+# define DP_PHY_TEST_PATTERN_CP2520         0x5
+
+#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
 #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
@@ -1570,4 +1579,26 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
 
 #endif
 
+/**
+ * struct drm_dp_phy_test_params - DP Phy Compliance parameters
+ * @link: Link information.
+ * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
+ * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
+ *            0x24A and 0x24B (sink)
+ * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
+ *               through 0x259.
+ */
+struct drm_dp_phy_test_params {
+	int link_rate;
+	u8 num_lanes;
+	u8 phy_pattern;
+	u8 hbr2_reset[2];
+	u8 custom80[10];
+	bool enahanced_frame_cap;
+};
+
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data);
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data, u8 dp_rev);
 #endif /* _DRM_DP_HELPER_H_ */
-- 
2.24.0

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[Intel-gfx] ✗ Fi.CI.BUILD: failure for DP Phy compliance auto test (rev4)

[Patchwork]

== Series Details ==

Series: DP Phy compliance auto test (rev4)
URL   : https://patchwork.freedesktop.org/series/71121/
State : failure

== Summary ==

Applying: drm/dp: get/set phy compliance pattern
Applying: drm/dp: get/set phy compliance pattern
error: sha1 information is lacking or useless (include/drm/drm_dp_helper.h).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0002 drm/dp: get/set phy compliance pattern
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [PATCH v3 2/9] drm/dp: get/set phy compliance pattern

[Harry Wentland]

On 2019-12-23 12:03 p.m., Animesh Manna wrote:
> During phy compliance auto test mode source need to read
> requested test pattern from sink through DPCD. After processing
> the request source need to set the pattern. So set/get method
> added in drm layer as it is DP protocol.
> 
> v2: As per review feedback from Manasi on RFC version,
> - added dp revision as function argument in set_phy_pattern api.
> - used int for link_rate and u8 for lane_count to align with existing code.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 93 +++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     | 31 +++++++++++
>  2 files changed, 124 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 2c7870aef469..91c80973aa83 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1371,3 +1371,96 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>  	return num_bpc;
>  }
>  EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> +
> +/**
> + * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
> + * @aux: DisplayPort AUX channel
> + * @data: DP phy compliance test parameters.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
> +				struct drm_dp_phy_test_params *data)
> +{
> +	int err;
> +	u8 rate, lanes;
> +
> +	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
> +	if (err < 0)
> +		return err;
> +	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
> +
> +	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
> +	if (err < 0)
> +		return err;
> +	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
> +
> +	if (lanes & DP_ENHANCED_FRAME_CAP)
> +		data->enahanced_frame_cap = true;
> +
> +	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
> +	if (err < 0)
> +		return err;
> +
> +	switch (data->phy_pattern) {
> +	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
> +		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
> +				       &data->custom80, 10);

Using sizeof(data->custom80) might be safer.

> +		if (err < 0)
> +			return err;
> +
> +		break;
> +	case DP_PHY_TEST_PATTERN_CP2520:
> +		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
> +				       &data->hbr2_reset, 2);

Same here, using sizeof(data->hbr2_reset).

> +		if (err < 0)
> +			return err;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
> +
> +/**
> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
> + * @aux: DisplayPort AUX channel
> + * @data: DP phy compliance test parameters.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
> +				struct drm_dp_phy_test_params *data, u8 dp_rev)
> +{
> +	int err, i;
> +	u8 link_config[2];
> +	u8 test_pattern;
> +
> +	link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
> +	link_config[1] = data->num_lanes;
> +	if (data->enahanced_frame_cap)
> +		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> +	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
> +	if (err < 0)
> +		return err;
> +
> +	test_pattern = data->phy_pattern;
> +	if (dp_rev < 0x12) {
> +		test_pattern = (test_pattern << 2) &
> +			       DP_LINK_QUAL_PATTERN_11_MASK;
> +		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
> +					 test_pattern);
> +		if (err < 0)
> +			return err;
> +	} else {
> +		for (i = 0; i < data->num_lanes; i++) {
> +			err = drm_dp_dpcd_writeb(aux,
> +						 DP_LINK_QUAL_LANE0_SET + i,
> +						 test_pattern);
> +			if (err < 0)
> +				return err;
> +		}
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index d6e560870fb1..42a364748308 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -700,6 +700,15 @@
>  # define DP_TEST_COUNT_MASK		    0xf
>  
>  #define DP_PHY_TEST_PATTERN                 0x248
> +# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
> +# define DP_PHY_TEST_PATTERN_NONE           0x0
> +# define DP_PHY_TEST_PATTERN_D10_2          0x1
> +# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
> +# define DP_PHY_TEST_PATTERN_PRBS7          0x3
> +# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
> +# define DP_PHY_TEST_PATTERN_CP2520         0x5
> +
> +#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
>  #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
>  #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
>  #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
> @@ -1570,4 +1579,26 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>  
>  #endif
>  
> +/**
> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
> + * @link: Link information.

@link seems to be from a previous patch version. Please describe
link_rate and num_lanes instead.

> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
> + *            0x24A and 0x24B (sink)
> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
> + *               through 0x259.

Missing doc for enhanced_frame_cap.

> + */
> +struct drm_dp_phy_test_params {
> +	int link_rate;

Is there a reason you're not using u8 here? Would be nice to keep it
consistent with num_lanes.

> +	u8 num_lanes;
> +	u8 phy_pattern;
> +	u8 hbr2_reset[2];
> +	u8 custom80[10];
> +	bool enahanced_frame_cap;

Typo. Should be enhanved_frame_cap.

Harry

> +};
> +
> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
> +				struct drm_dp_phy_test_params *data);
> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
> +				struct drm_dp_phy_test_params *data, u8 dp_rev);
>  #endif /* _DRM_DP_HELPER_H_ */
> 
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Re: [Intel-gfx] [PATCH v3 2/9] drm/dp: get/set phy compliance pattern

[Harry Wentland]

On 2019-12-23 12:03 p.m., Animesh Manna wrote:
> During phy compliance auto test mode source need to read
> requested test pattern from sink through DPCD. After processing
> the request source need to set the pattern. So set/get method
> added in drm layer as it is DP protocol.
> 
> v2: As per review feedback from Manasi on RFC version,
> - added dp revision as function argument in set_phy_pattern api.
> - used int for link_rate and u8 for lane_count to align with existing code.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 93 +++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     | 31 +++++++++++
>  2 files changed, 124 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 2c7870aef469..91c80973aa83 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1371,3 +1371,96 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>  	return num_bpc;
>  }
>  EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> +
> +/**
> + * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
> + * @aux: DisplayPort AUX channel
> + * @data: DP phy compliance test parameters.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
> +				struct drm_dp_phy_test_params *data)
> +{
> +	int err;
> +	u8 rate, lanes;
> +
> +	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
> +	if (err < 0)
> +		return err;
> +	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
> +
> +	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
> +	if (err < 0)
> +		return err;
> +	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
> +
> +	if (lanes & DP_ENHANCED_FRAME_CAP)
> +		data->enahanced_frame_cap = true;
> +
> +	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
> +	if (err < 0)
> +		return err;
> +
> +	switch (data->phy_pattern) {
> +	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
> +		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
> +				       &data->custom80, 10);

Using sizeof(data->custom80) might be safer.

> +		if (err < 0)
> +			return err;
> +
> +		break;
> +	case DP_PHY_TEST_PATTERN_CP2520:
> +		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
> +				       &data->hbr2_reset, 2);

Same here, using sizeof(data->hbr2_reset).

> +		if (err < 0)
> +			return err;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
> +
> +/**
> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
> + * @aux: DisplayPort AUX channel
> + * @data: DP phy compliance test parameters.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
> +				struct drm_dp_phy_test_params *data, u8 dp_rev)
> +{
> +	int err, i;
> +	u8 link_config[2];
> +	u8 test_pattern;
> +
> +	link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
> +	link_config[1] = data->num_lanes;
> +	if (data->enahanced_frame_cap)
> +		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> +	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
> +	if (err < 0)
> +		return err;
> +
> +	test_pattern = data->phy_pattern;
> +	if (dp_rev < 0x12) {
> +		test_pattern = (test_pattern << 2) &
> +			       DP_LINK_QUAL_PATTERN_11_MASK;
> +		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
> +					 test_pattern);
> +		if (err < 0)
> +			return err;
> +	} else {
> +		for (i = 0; i < data->num_lanes; i++) {
> +			err = drm_dp_dpcd_writeb(aux,
> +						 DP_LINK_QUAL_LANE0_SET + i,
> +						 test_pattern);
> +			if (err < 0)
> +				return err;
> +		}
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index d6e560870fb1..42a364748308 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -700,6 +700,15 @@
>  # define DP_TEST_COUNT_MASK		    0xf
>  
>  #define DP_PHY_TEST_PATTERN                 0x248
> +# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
> +# define DP_PHY_TEST_PATTERN_NONE           0x0
> +# define DP_PHY_TEST_PATTERN_D10_2          0x1
> +# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
> +# define DP_PHY_TEST_PATTERN_PRBS7          0x3
> +# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
> +# define DP_PHY_TEST_PATTERN_CP2520         0x5
> +
> +#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
>  #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
>  #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
>  #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
> @@ -1570,4 +1579,26 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>  
>  #endif
>  
> +/**
> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
> + * @link: Link information.

@link seems to be from a previous patch version. Please describe
link_rate and num_lanes instead.

> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
> + *            0x24A and 0x24B (sink)
> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
> + *               through 0x259.

Missing doc for enhanced_frame_cap.

> + */
> +struct drm_dp_phy_test_params {
> +	int link_rate;

Is there a reason you're not using u8 here? Would be nice to keep it
consistent with num_lanes.

> +	u8 num_lanes;
> +	u8 phy_pattern;
> +	u8 hbr2_reset[2];
> +	u8 custom80[10];
> +	bool enahanced_frame_cap;

Typo. Should be enhanved_frame_cap.

Harry

> +};
> +
> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
> +				struct drm_dp_phy_test_params *data);
> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
> +				struct drm_dp_phy_test_params *data, u8 dp_rev);
>  #endif /* _DRM_DP_HELPER_H_ */
> 
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Re: [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec

[Harry Wentland]

On 2019-12-23 12:03 p.m., Animesh Manna wrote:
> [Why]:
> Aligh with DP spec wanted to follow same naming convention.
> 
> [How]:
> Changed the macro name of the dpcd address used for getting requested
> test-pattern.
> 
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
>  include/drm/drm_dp_helper.h                      | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 42aa889fd0f5..1a6109be2fce 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
>  	/* get phy test pattern and pattern parameters from DP receiver */
>  	core_link_read_dpcd(
>  			link,
> -			DP_TEST_PHY_PATTERN,
> +			DP_PHY_TEST_PATTERN,
>  			&dpcd_test_pattern.raw,
>  			sizeof(dpcd_test_pattern));
>  	core_link_read_dpcd(
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 8f8f3632e697..d6e560870fb1 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -699,7 +699,7 @@
>  # define DP_TEST_CRC_SUPPORTED		    (1 << 5)
>  # define DP_TEST_COUNT_MASK		    0xf
>  
> -#define DP_TEST_PHY_PATTERN                 0x248
> +#define DP_PHY_TEST_PATTERN                 0x248
>  #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
>  #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
>  #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
> 
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Re: [Intel-gfx] [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec

[Harry Wentland]

On 2019-12-23 12:03 p.m., Animesh Manna wrote:
> [Why]:
> Aligh with DP spec wanted to follow same naming convention.
> 
> [How]:
> Changed the macro name of the dpcd address used for getting requested
> test-pattern.
> 
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
>  include/drm/drm_dp_helper.h                      | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 42aa889fd0f5..1a6109be2fce 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
>  	/* get phy test pattern and pattern parameters from DP receiver */
>  	core_link_read_dpcd(
>  			link,
> -			DP_TEST_PHY_PATTERN,
> +			DP_PHY_TEST_PATTERN,
>  			&dpcd_test_pattern.raw,
>  			sizeof(dpcd_test_pattern));
>  	core_link_read_dpcd(
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 8f8f3632e697..d6e560870fb1 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -699,7 +699,7 @@
>  # define DP_TEST_CRC_SUPPORTED		    (1 << 5)
>  # define DP_TEST_COUNT_MASK		    0xf
>  
> -#define DP_TEST_PHY_PATTERN                 0x248
> +#define DP_PHY_TEST_PATTERN                 0x248
>  #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
>  #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
>  #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
> 
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Re: [PATCH v3 2/9] drm/dp: get/set phy compliance pattern

[Manna, Animesh]

On 24-12-2019 01:23, Harry Wentland wrote:
>
> On 2019-12-23 12:03 p.m., Animesh Manna wrote:
>> During phy compliance auto test mode source need to read
>> requested test pattern from sink through DPCD. After processing
>> the request source need to set the pattern. So set/get method
>> added in drm layer as it is DP protocol.
>>
>> v2: As per review feedback from Manasi on RFC version,
>> - added dp revision as function argument in set_phy_pattern api.
>> - used int for link_rate and u8 for lane_count to align with existing code.
>>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/drm_dp_helper.c | 93 +++++++++++++++++++++++++++++++++
>>   include/drm/drm_dp_helper.h     | 31 +++++++++++
>>   2 files changed, 124 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
>> index 2c7870aef469..91c80973aa83 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -1371,3 +1371,96 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>>   	return num_bpc;
>>   }
>>   EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>> +
>> +/**
>> + * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
>> + * @aux: DisplayPort AUX channel
>> + * @data: DP phy compliance test parameters.
>> + *
>> + * Returns 0 on success or a negative error code on failure.
>> + */
>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>> +				struct drm_dp_phy_test_params *data)
>> +{
>> +	int err;
>> +	u8 rate, lanes;
>> +
>> +	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
>> +	if (err < 0)
>> +		return err;
>> +	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
>> +
>> +	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
>> +	if (err < 0)
>> +		return err;
>> +	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
>> +
>> +	if (lanes & DP_ENHANCED_FRAME_CAP)
>> +		data->enahanced_frame_cap = true;
>> +
>> +	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
>> +	if (err < 0)
>> +		return err;
>> +
>> +	switch (data->phy_pattern) {
>> +	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
>> +		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
>> +				       &data->custom80, 10);
> Using sizeof(data->custom80) might be safer.
>
>> +		if (err < 0)
>> +			return err;
>> +
>> +		break;
>> +	case DP_PHY_TEST_PATTERN_CP2520:
>> +		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
>> +				       &data->hbr2_reset, 2);
> Same here, using sizeof(data->hbr2_reset).
>
>> +		if (err < 0)
>> +			return err;
>> +	}
>> +
>> +	return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
>> +
>> +/**
>> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
>> + * @aux: DisplayPort AUX channel
>> + * @data: DP phy compliance test parameters.
>> + *
>> + * Returns 0 on success or a negative error code on failure.
>> + */
>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>> +				struct drm_dp_phy_test_params *data, u8 dp_rev)
>> +{
>> +	int err, i;
>> +	u8 link_config[2];
>> +	u8 test_pattern;
>> +
>> +	link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
>> +	link_config[1] = data->num_lanes;
>> +	if (data->enahanced_frame_cap)
>> +		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> +	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
>> +	if (err < 0)
>> +		return err;
>> +
>> +	test_pattern = data->phy_pattern;
>> +	if (dp_rev < 0x12) {
>> +		test_pattern = (test_pattern << 2) &
>> +			       DP_LINK_QUAL_PATTERN_11_MASK;
>> +		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
>> +					 test_pattern);
>> +		if (err < 0)
>> +			return err;
>> +	} else {
>> +		for (i = 0; i < data->num_lanes; i++) {
>> +			err = drm_dp_dpcd_writeb(aux,
>> +						 DP_LINK_QUAL_LANE0_SET + i,
>> +						 test_pattern);
>> +			if (err < 0)
>> +				return err;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index d6e560870fb1..42a364748308 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -700,6 +700,15 @@
>>   # define DP_TEST_COUNT_MASK		    0xf
>>   
>>   #define DP_PHY_TEST_PATTERN                 0x248
>> +# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
>> +# define DP_PHY_TEST_PATTERN_NONE           0x0
>> +# define DP_PHY_TEST_PATTERN_D10_2          0x1
>> +# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
>> +# define DP_PHY_TEST_PATTERN_PRBS7          0x3
>> +# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
>> +# define DP_PHY_TEST_PATTERN_CP2520         0x5
>> +
>> +#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
>>   #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
>>   #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
>>   #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
>> @@ -1570,4 +1579,26 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>>   
>>   #endif
>>   
>> +/**
>> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
>> + * @link: Link information.
> @link seems to be from a previous patch version. Please describe
> link_rate and num_lanes instead.
>
>> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
>> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
>> + *            0x24A and 0x24B (sink)
>> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
>> + *               through 0x259.
> Missing doc for enhanced_frame_cap.
>
>> + */
>> +struct drm_dp_phy_test_params {
>> +	int link_rate;
> Is there a reason you're not using u8 here? Would be nice to keep it
> consistent with num_lanes.

link_rate variable is used here to store actual clock value after multiplying with 27000 (0.27 gbps) with link-code using drm_dp_bw_code_to_link_rate().
Followed the same and u8 maybe not be sufficient. Added other suggested changes. Thanks for review.

Regrads,
Animesh

>
>> +	u8 num_lanes;
>> +	u8 phy_pattern;
>> +	u8 hbr2_reset[2];
>> +	u8 custom80[10];
>> +	bool enahanced_frame_cap;
> Typo. Should be enhanved_frame_cap.
>
> Harry
>
>> +};
>> +
>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>> +				struct drm_dp_phy_test_params *data);
>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>> +				struct drm_dp_phy_test_params *data, u8 dp_rev);
>>   #endif /* _DRM_DP_HELPER_H_ */
>>
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Re: [Intel-gfx] [PATCH v3 2/9] drm/dp: get/set phy compliance pattern

[Manna, Animesh]

On 24-12-2019 01:23, Harry Wentland wrote:
>
> On 2019-12-23 12:03 p.m., Animesh Manna wrote:
>> During phy compliance auto test mode source need to read
>> requested test pattern from sink through DPCD. After processing
>> the request source need to set the pattern. So set/get method
>> added in drm layer as it is DP protocol.
>>
>> v2: As per review feedback from Manasi on RFC version,
>> - added dp revision as function argument in set_phy_pattern api.
>> - used int for link_rate and u8 for lane_count to align with existing code.
>>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/drm_dp_helper.c | 93 +++++++++++++++++++++++++++++++++
>>   include/drm/drm_dp_helper.h     | 31 +++++++++++
>>   2 files changed, 124 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
>> index 2c7870aef469..91c80973aa83 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -1371,3 +1371,96 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>>   	return num_bpc;
>>   }
>>   EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>> +
>> +/**
>> + * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
>> + * @aux: DisplayPort AUX channel
>> + * @data: DP phy compliance test parameters.
>> + *
>> + * Returns 0 on success or a negative error code on failure.
>> + */
>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>> +				struct drm_dp_phy_test_params *data)
>> +{
>> +	int err;
>> +	u8 rate, lanes;
>> +
>> +	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
>> +	if (err < 0)
>> +		return err;
>> +	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
>> +
>> +	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
>> +	if (err < 0)
>> +		return err;
>> +	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
>> +
>> +	if (lanes & DP_ENHANCED_FRAME_CAP)
>> +		data->enahanced_frame_cap = true;
>> +
>> +	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
>> +	if (err < 0)
>> +		return err;
>> +
>> +	switch (data->phy_pattern) {
>> +	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
>> +		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
>> +				       &data->custom80, 10);
> Using sizeof(data->custom80) might be safer.
>
>> +		if (err < 0)
>> +			return err;
>> +
>> +		break;
>> +	case DP_PHY_TEST_PATTERN_CP2520:
>> +		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
>> +				       &data->hbr2_reset, 2);
> Same here, using sizeof(data->hbr2_reset).
>
>> +		if (err < 0)
>> +			return err;
>> +	}
>> +
>> +	return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
>> +
>> +/**
>> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
>> + * @aux: DisplayPort AUX channel
>> + * @data: DP phy compliance test parameters.
>> + *
>> + * Returns 0 on success or a negative error code on failure.
>> + */
>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>> +				struct drm_dp_phy_test_params *data, u8 dp_rev)
>> +{
>> +	int err, i;
>> +	u8 link_config[2];
>> +	u8 test_pattern;
>> +
>> +	link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
>> +	link_config[1] = data->num_lanes;
>> +	if (data->enahanced_frame_cap)
>> +		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> +	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
>> +	if (err < 0)
>> +		return err;
>> +
>> +	test_pattern = data->phy_pattern;
>> +	if (dp_rev < 0x12) {
>> +		test_pattern = (test_pattern << 2) &
>> +			       DP_LINK_QUAL_PATTERN_11_MASK;
>> +		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
>> +					 test_pattern);
>> +		if (err < 0)
>> +			return err;
>> +	} else {
>> +		for (i = 0; i < data->num_lanes; i++) {
>> +			err = drm_dp_dpcd_writeb(aux,
>> +						 DP_LINK_QUAL_LANE0_SET + i,
>> +						 test_pattern);
>> +			if (err < 0)
>> +				return err;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index d6e560870fb1..42a364748308 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -700,6 +700,15 @@
>>   # define DP_TEST_COUNT_MASK		    0xf
>>   
>>   #define DP_PHY_TEST_PATTERN                 0x248
>> +# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
>> +# define DP_PHY_TEST_PATTERN_NONE           0x0
>> +# define DP_PHY_TEST_PATTERN_D10_2          0x1
>> +# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
>> +# define DP_PHY_TEST_PATTERN_PRBS7          0x3
>> +# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
>> +# define DP_PHY_TEST_PATTERN_CP2520         0x5
>> +
>> +#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
>>   #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
>>   #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
>>   #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
>> @@ -1570,4 +1579,26 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>>   
>>   #endif
>>   
>> +/**
>> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
>> + * @link: Link information.
> @link seems to be from a previous patch version. Please describe
> link_rate and num_lanes instead.
>
>> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
>> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
>> + *            0x24A and 0x24B (sink)
>> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
>> + *               through 0x259.
> Missing doc for enhanced_frame_cap.
>
>> + */
>> +struct drm_dp_phy_test_params {
>> +	int link_rate;
> Is there a reason you're not using u8 here? Would be nice to keep it
> consistent with num_lanes.

link_rate variable is used here to store actual clock value after multiplying with 27000 (0.27 gbps) with link-code using drm_dp_bw_code_to_link_rate().
Followed the same and u8 maybe not be sufficient. Added other suggested changes. Thanks for review.

Regrads,
Animesh

>
>> +	u8 num_lanes;
>> +	u8 phy_pattern;
>> +	u8 hbr2_reset[2];
>> +	u8 custom80[10];
>> +	bool enahanced_frame_cap;
> Typo. Should be enhanved_frame_cap.
>
> Harry
>
>> +};
>> +
>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>> +				struct drm_dp_phy_test_params *data);
>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>> +				struct drm_dp_phy_test_params *data, u8 dp_rev);
>>   #endif /* _DRM_DP_HELPER_H_ */
>>
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Re: [PATCH v3 2/9] drm/dp: get/set phy compliance pattern

[Harry Wentland]

On 2019-12-30 11:05 a.m., Manna, Animesh wrote:
> On 24-12-2019 01:23, Harry Wentland wrote:
>>
>> On 2019-12-23 12:03 p.m., Animesh Manna wrote:
>>> During phy compliance auto test mode source need to read
>>> requested test pattern from sink through DPCD. After processing
>>> the request source need to set the pattern. So set/get method
>>> added in drm layer as it is DP protocol.
>>>
>>> v2: As per review feedback from Manasi on RFC version,
>>> - added dp revision as function argument in set_phy_pattern api.
>>> - used int for link_rate and u8 for lane_count to align with
>>> existing code.
>>>
>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>> ---
>>>   drivers/gpu/drm/drm_dp_helper.c | 93
>>> +++++++++++++++++++++++++++++++++
>>>   include/drm/drm_dp_helper.h     | 31 +++++++++++
>>>   2 files changed, 124 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/drm_dp_helper.c
>>> b/drivers/gpu/drm/drm_dp_helper.c
>>> index 2c7870aef469..91c80973aa83 100644
>>> --- a/drivers/gpu/drm/drm_dp_helper.c
>>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>>> @@ -1371,3 +1371,96 @@ int
>>> drm_dp_dsc_sink_supported_input_bpcs(const u8
>>> dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>>>       return num_bpc;
>>>   }
>>>   EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>>> +
>>> +/**
>>> + * drm_dp_get_phy_test_pattern() - get the requested pattern from
>>> the sink.
>>> + * @aux: DisplayPort AUX channel
>>> + * @data: DP phy compliance test parameters.
>>> + *
>>> + * Returns 0 on success or a negative error code on failure.
>>> + */
>>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>>> +                struct drm_dp_phy_test_params *data)
>>> +{
>>> +    int err;
>>> +    u8 rate, lanes;
>>> +
>>> +    err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
>>> +    if (err < 0)
>>> +        return err;
>>> +    data->link_rate = drm_dp_bw_code_to_link_rate(rate);
>>> +
>>> +    err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
>>> +    if (err < 0)
>>> +        return err;
>>> +    data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
>>> +
>>> +    if (lanes & DP_ENHANCED_FRAME_CAP)
>>> +        data->enahanced_frame_cap = true;
>>> +
>>> +    err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN,
>>> &data->phy_pattern);
>>> +    if (err < 0)
>>> +        return err;
>>> +
>>> +    switch (data->phy_pattern) {
>>> +    case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
>>> +        err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
>>> +                       &data->custom80, 10);
>> Using sizeof(data->custom80) might be safer.
>>
>>> +        if (err < 0)
>>> +            return err;
>>> +
>>> +        break;
>>> +    case DP_PHY_TEST_PATTERN_CP2520:
>>> +        err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
>>> +                       &data->hbr2_reset, 2);
>> Same here, using sizeof(data->hbr2_reset).
>>
>>> +        if (err < 0)
>>> +            return err;
>>> +    }
>>> +
>>> +    return 0;
>>> +}
>>> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
>>> +
>>> +/**
>>> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
>>> + * @aux: DisplayPort AUX channel
>>> + * @data: DP phy compliance test parameters.
>>> + *
>>> + * Returns 0 on success or a negative error code on failure.
>>> + */
>>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>>> +                struct drm_dp_phy_test_params *data, u8 dp_rev)
>>> +{
>>> +    int err, i;
>>> +    u8 link_config[2];
>>> +    u8 test_pattern;
>>> +
>>> +    link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
>>> +    link_config[1] = data->num_lanes;
>>> +    if (data->enahanced_frame_cap)
>>> +        link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>>> +    err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
>>> +    if (err < 0)
>>> +        return err;
>>> +
>>> +    test_pattern = data->phy_pattern;
>>> +    if (dp_rev < 0x12) {
>>> +        test_pattern = (test_pattern << 2) &
>>> +                   DP_LINK_QUAL_PATTERN_11_MASK;
>>> +        err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
>>> +                     test_pattern);
>>> +        if (err < 0)
>>> +            return err;
>>> +    } else {
>>> +        for (i = 0; i < data->num_lanes; i++) {
>>> +            err = drm_dp_dpcd_writeb(aux,
>>> +                         DP_LINK_QUAL_LANE0_SET + i,
>>> +                         test_pattern);
>>> +            if (err < 0)
>>> +                return err;
>>> +        }
>>> +    }
>>> +
>>> +    return 0;
>>> +}
>>> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
>>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>>> index d6e560870fb1..42a364748308 100644
>>> --- a/include/drm/drm_dp_helper.h
>>> +++ b/include/drm/drm_dp_helper.h
>>> @@ -700,6 +700,15 @@
>>>   # define DP_TEST_COUNT_MASK            0xf
>>>     #define DP_PHY_TEST_PATTERN                 0x248
>>> +# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
>>> +# define DP_PHY_TEST_PATTERN_NONE           0x0
>>> +# define DP_PHY_TEST_PATTERN_D10_2          0x1
>>> +# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
>>> +# define DP_PHY_TEST_PATTERN_PRBS7          0x3
>>> +# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
>>> +# define DP_PHY_TEST_PATTERN_CP2520         0x5
>>> +
>>> +#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
>>>   #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
>>>   #define    DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
>>>   #define    DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
>>> @@ -1570,4 +1579,26 @@ static inline void
>>> drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>>>     #endif
>>>   +/**
>>> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
>>> + * @link: Link information.
>> @link seems to be from a previous patch version. Please describe
>> link_rate and num_lanes instead.
>>
>>> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
>>> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
>>> + *            0x24A and 0x24B (sink)
>>> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
>>> + *               through 0x259.
>> Missing doc for enhanced_frame_cap.
>>
>>> + */
>>> +struct drm_dp_phy_test_params {
>>> +    int link_rate;
>> Is there a reason you're not using u8 here? Would be nice to keep it
>> consistent with num_lanes.
>
> link_rate variable is used here to store actual clock value after
> multiplying with 27000 (0.27 gbps) with link-code using
> drm_dp_bw_code_to_link_rate().
> Followed the same and u8 maybe not be sufficient. Added other
> suggested changes. Thanks for review.
>
That makes sense. I missed that. In that case feel free to add my
Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> Regrads,
> Animesh
>
>>
>>> +    u8 num_lanes;
>>> +    u8 phy_pattern;
>>> +    u8 hbr2_reset[2];
>>> +    u8 custom80[10];
>>> +    bool enahanced_frame_cap;
>> Typo. Should be enhanved_frame_cap.
>>
>> Harry
>>
>>> +};
>>> +
>>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>>> +                struct drm_dp_phy_test_params *data);
>>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>>> +                struct drm_dp_phy_test_params *data, u8 dp_rev);
>>>   #endif /* _DRM_DP_HELPER_H_ */
>>>

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Re: [Intel-gfx] [PATCH v3 2/9] drm/dp: get/set phy compliance pattern

[Harry Wentland]

On 2019-12-30 11:05 a.m., Manna, Animesh wrote:
> On 24-12-2019 01:23, Harry Wentland wrote:
>>
>> On 2019-12-23 12:03 p.m., Animesh Manna wrote:
>>> During phy compliance auto test mode source need to read
>>> requested test pattern from sink through DPCD. After processing
>>> the request source need to set the pattern. So set/get method
>>> added in drm layer as it is DP protocol.
>>>
>>> v2: As per review feedback from Manasi on RFC version,
>>> - added dp revision as function argument in set_phy_pattern api.
>>> - used int for link_rate and u8 for lane_count to align with
>>> existing code.
>>>
>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>> ---
>>>   drivers/gpu/drm/drm_dp_helper.c | 93
>>> +++++++++++++++++++++++++++++++++
>>>   include/drm/drm_dp_helper.h     | 31 +++++++++++
>>>   2 files changed, 124 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/drm_dp_helper.c
>>> b/drivers/gpu/drm/drm_dp_helper.c
>>> index 2c7870aef469..91c80973aa83 100644
>>> --- a/drivers/gpu/drm/drm_dp_helper.c
>>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>>> @@ -1371,3 +1371,96 @@ int
>>> drm_dp_dsc_sink_supported_input_bpcs(const u8
>>> dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>>>       return num_bpc;
>>>   }
>>>   EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>>> +
>>> +/**
>>> + * drm_dp_get_phy_test_pattern() - get the requested pattern from
>>> the sink.
>>> + * @aux: DisplayPort AUX channel
>>> + * @data: DP phy compliance test parameters.
>>> + *
>>> + * Returns 0 on success or a negative error code on failure.
>>> + */
>>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>>> +                struct drm_dp_phy_test_params *data)
>>> +{
>>> +    int err;
>>> +    u8 rate, lanes;
>>> +
>>> +    err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
>>> +    if (err < 0)
>>> +        return err;
>>> +    data->link_rate = drm_dp_bw_code_to_link_rate(rate);
>>> +
>>> +    err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
>>> +    if (err < 0)
>>> +        return err;
>>> +    data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
>>> +
>>> +    if (lanes & DP_ENHANCED_FRAME_CAP)
>>> +        data->enahanced_frame_cap = true;
>>> +
>>> +    err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN,
>>> &data->phy_pattern);
>>> +    if (err < 0)
>>> +        return err;
>>> +
>>> +    switch (data->phy_pattern) {
>>> +    case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
>>> +        err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
>>> +                       &data->custom80, 10);
>> Using sizeof(data->custom80) might be safer.
>>
>>> +        if (err < 0)
>>> +            return err;
>>> +
>>> +        break;
>>> +    case DP_PHY_TEST_PATTERN_CP2520:
>>> +        err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
>>> +                       &data->hbr2_reset, 2);
>> Same here, using sizeof(data->hbr2_reset).
>>
>>> +        if (err < 0)
>>> +            return err;
>>> +    }
>>> +
>>> +    return 0;
>>> +}
>>> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
>>> +
>>> +/**
>>> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
>>> + * @aux: DisplayPort AUX channel
>>> + * @data: DP phy compliance test parameters.
>>> + *
>>> + * Returns 0 on success or a negative error code on failure.
>>> + */
>>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>>> +                struct drm_dp_phy_test_params *data, u8 dp_rev)
>>> +{
>>> +    int err, i;
>>> +    u8 link_config[2];
>>> +    u8 test_pattern;
>>> +
>>> +    link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
>>> +    link_config[1] = data->num_lanes;
>>> +    if (data->enahanced_frame_cap)
>>> +        link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>>> +    err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
>>> +    if (err < 0)
>>> +        return err;
>>> +
>>> +    test_pattern = data->phy_pattern;
>>> +    if (dp_rev < 0x12) {
>>> +        test_pattern = (test_pattern << 2) &
>>> +                   DP_LINK_QUAL_PATTERN_11_MASK;
>>> +        err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
>>> +                     test_pattern);
>>> +        if (err < 0)
>>> +            return err;
>>> +    } else {
>>> +        for (i = 0; i < data->num_lanes; i++) {
>>> +            err = drm_dp_dpcd_writeb(aux,
>>> +                         DP_LINK_QUAL_LANE0_SET + i,
>>> +                         test_pattern);
>>> +            if (err < 0)
>>> +                return err;
>>> +        }
>>> +    }
>>> +
>>> +    return 0;
>>> +}
>>> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
>>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>>> index d6e560870fb1..42a364748308 100644
>>> --- a/include/drm/drm_dp_helper.h
>>> +++ b/include/drm/drm_dp_helper.h
>>> @@ -700,6 +700,15 @@
>>>   # define DP_TEST_COUNT_MASK            0xf
>>>     #define DP_PHY_TEST_PATTERN                 0x248
>>> +# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
>>> +# define DP_PHY_TEST_PATTERN_NONE           0x0
>>> +# define DP_PHY_TEST_PATTERN_D10_2          0x1
>>> +# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
>>> +# define DP_PHY_TEST_PATTERN_PRBS7          0x3
>>> +# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
>>> +# define DP_PHY_TEST_PATTERN_CP2520         0x5
>>> +
>>> +#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
>>>   #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
>>>   #define    DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
>>>   #define    DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
>>> @@ -1570,4 +1579,26 @@ static inline void
>>> drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>>>     #endif
>>>   +/**
>>> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
>>> + * @link: Link information.
>> @link seems to be from a previous patch version. Please describe
>> link_rate and num_lanes instead.
>>
>>> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
>>> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
>>> + *            0x24A and 0x24B (sink)
>>> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
>>> + *               through 0x259.
>> Missing doc for enhanced_frame_cap.
>>
>>> + */
>>> +struct drm_dp_phy_test_params {
>>> +    int link_rate;
>> Is there a reason you're not using u8 here? Would be nice to keep it
>> consistent with num_lanes.
>
> link_rate variable is used here to store actual clock value after
> multiplying with 27000 (0.27 gbps) with link-code using
> drm_dp_bw_code_to_link_rate().
> Followed the same and u8 maybe not be sufficient. Added other
> suggested changes. Thanks for review.
>
That makes sense. I missed that. In that case feel free to add my
Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> Regrads,
> Animesh
>
>>
>>> +    u8 num_lanes;
>>> +    u8 phy_pattern;
>>> +    u8 hbr2_reset[2];
>>> +    u8 custom80[10];
>>> +    bool enahanced_frame_cap;
>> Typo. Should be enhanved_frame_cap.
>>
>> Harry
>>
>>> +};
>>> +
>>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>>> +                struct drm_dp_phy_test_params *data);
>>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>>> +                struct drm_dp_phy_test_params *data, u8 dp_rev);
>>>   #endif /* _DRM_DP_HELPER_H_ */
>>>

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Re: [PATCH v3 2/9] drm/dp: get/set phy compliance pattern

[Manna, Animesh]

On 30-12-2019 21:41, Harry Wentland wrote:

>
> On 2019-12-30 11:05 a.m., Manna, Animesh wrote:
>> On 24-12-2019 01:23, Harry Wentland wrote:
>>> On 2019-12-23 12:03 p.m., Animesh Manna wrote:
>>>> During phy compliance auto test mode source need to read
>>>> requested test pattern from sink through DPCD. After processing
>>>> the request source need to set the pattern. So set/get method
>>>> added in drm layer as it is DP protocol.
>>>>
>>>> v2: As per review feedback from Manasi on RFC version,
>>>> - added dp revision as function argument in set_phy_pattern api.
>>>> - used int for link_rate and u8 for lane_count to align with
>>>> existing code.
>>>>
>>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/drm_dp_helper.c | 93
>>>> +++++++++++++++++++++++++++++++++
>>>>    include/drm/drm_dp_helper.h     | 31 +++++++++++
>>>>    2 files changed, 124 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/drm_dp_helper.c
>>>> b/drivers/gpu/drm/drm_dp_helper.c
>>>> index 2c7870aef469..91c80973aa83 100644
>>>> --- a/drivers/gpu/drm/drm_dp_helper.c
>>>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>>>> @@ -1371,3 +1371,96 @@ int
>>>> drm_dp_dsc_sink_supported_input_bpcs(const u8
>>>> dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>>>>        return num_bpc;
>>>>    }
>>>>    EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>>>> +
>>>> +/**
>>>> + * drm_dp_get_phy_test_pattern() - get the requested pattern from
>>>> the sink.
>>>> + * @aux: DisplayPort AUX channel
>>>> + * @data: DP phy compliance test parameters.
>>>> + *
>>>> + * Returns 0 on success or a negative error code on failure.
>>>> + */
>>>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>>>> +                struct drm_dp_phy_test_params *data)
>>>> +{
>>>> +    int err;
>>>> +    u8 rate, lanes;
>>>> +
>>>> +    err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
>>>> +    if (err < 0)
>>>> +        return err;
>>>> +    data->link_rate = drm_dp_bw_code_to_link_rate(rate);
>>>> +
>>>> +    err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
>>>> +    if (err < 0)
>>>> +        return err;
>>>> +    data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
>>>> +
>>>> +    if (lanes & DP_ENHANCED_FRAME_CAP)
>>>> +        data->enahanced_frame_cap = true;
>>>> +
>>>> +    err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN,
>>>> &data->phy_pattern);
>>>> +    if (err < 0)
>>>> +        return err;
>>>> +
>>>> +    switch (data->phy_pattern) {
>>>> +    case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
>>>> +        err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
>>>> +                       &data->custom80, 10);
>>> Using sizeof(data->custom80) might be safer.
>>>
>>>> +        if (err < 0)
>>>> +            return err;
>>>> +
>>>> +        break;
>>>> +    case DP_PHY_TEST_PATTERN_CP2520:
>>>> +        err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
>>>> +                       &data->hbr2_reset, 2);
>>> Same here, using sizeof(data->hbr2_reset).
>>>
>>>> +        if (err < 0)
>>>> +            return err;
>>>> +    }
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
>>>> +
>>>> +/**
>>>> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
>>>> + * @aux: DisplayPort AUX channel
>>>> + * @data: DP phy compliance test parameters.
>>>> + *
>>>> + * Returns 0 on success or a negative error code on failure.
>>>> + */
>>>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>>>> +                struct drm_dp_phy_test_params *data, u8 dp_rev)
>>>> +{
>>>> +    int err, i;
>>>> +    u8 link_config[2];
>>>> +    u8 test_pattern;
>>>> +
>>>> +    link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
>>>> +    link_config[1] = data->num_lanes;
>>>> +    if (data->enahanced_frame_cap)
>>>> +        link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>>>> +    err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
>>>> +    if (err < 0)
>>>> +        return err;
>>>> +
>>>> +    test_pattern = data->phy_pattern;
>>>> +    if (dp_rev < 0x12) {
>>>> +        test_pattern = (test_pattern << 2) &
>>>> +                   DP_LINK_QUAL_PATTERN_11_MASK;
>>>> +        err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
>>>> +                     test_pattern);
>>>> +        if (err < 0)
>>>> +            return err;
>>>> +    } else {
>>>> +        for (i = 0; i < data->num_lanes; i++) {
>>>> +            err = drm_dp_dpcd_writeb(aux,
>>>> +                         DP_LINK_QUAL_LANE0_SET + i,
>>>> +                         test_pattern);
>>>> +            if (err < 0)
>>>> +                return err;
>>>> +        }
>>>> +    }
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
>>>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>>>> index d6e560870fb1..42a364748308 100644
>>>> --- a/include/drm/drm_dp_helper.h
>>>> +++ b/include/drm/drm_dp_helper.h
>>>> @@ -700,6 +700,15 @@
>>>>    # define DP_TEST_COUNT_MASK            0xf
>>>>      #define DP_PHY_TEST_PATTERN                 0x248
>>>> +# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
>>>> +# define DP_PHY_TEST_PATTERN_NONE           0x0
>>>> +# define DP_PHY_TEST_PATTERN_D10_2          0x1
>>>> +# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
>>>> +# define DP_PHY_TEST_PATTERN_PRBS7          0x3
>>>> +# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
>>>> +# define DP_PHY_TEST_PATTERN_CP2520         0x5
>>>> +
>>>> +#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
>>>>    #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
>>>>    #define    DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
>>>>    #define    DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
>>>> @@ -1570,4 +1579,26 @@ static inline void
>>>> drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>>>>      #endif
>>>>    +/**
>>>> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
>>>> + * @link: Link information.
>>> @link seems to be from a previous patch version. Please describe
>>> link_rate and num_lanes instead.
>>>
>>>> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
>>>> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
>>>> + *            0x24A and 0x24B (sink)
>>>> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
>>>> + *               through 0x259.
>>> Missing doc for enhanced_frame_cap.
>>>
>>>> + */
>>>> +struct drm_dp_phy_test_params {
>>>> +    int link_rate;
>>> Is there a reason you're not using u8 here? Would be nice to keep it
>>> consistent with num_lanes.
>> link_rate variable is used here to store actual clock value after
>> multiplying with 27000 (0.27 gbps) with link-code using
>> drm_dp_bw_code_to_link_rate().
>> Followed the same and u8 maybe not be sufficient. Added other
>> suggested changes. Thanks for review.
>>
> That makes sense. I missed that. In that case feel free to add my
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Sure will add your r-b in next version. Thanks.

Regards,
Animesh

>
> Harry
>
>> Regrads,
>> Animesh
>>
>>>> +    u8 num_lanes;
>>>> +    u8 phy_pattern;
>>>> +    u8 hbr2_reset[2];
>>>> +    u8 custom80[10];
>>>> +    bool enahanced_frame_cap;
>>> Typo. Should be enhanved_frame_cap.
>>>
>>> Harry
>>>
>>>> +};
>>>> +
>>>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>>>> +                struct drm_dp_phy_test_params *data);
>>>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>>>> +                struct drm_dp_phy_test_params *data, u8 dp_rev);
>>>>    #endif /* _DRM_DP_HELPER_H_ */
>>>>
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Re: [Intel-gfx] [PATCH v3 2/9] drm/dp: get/set phy compliance pattern

[Manna, Animesh]

On 30-12-2019 21:41, Harry Wentland wrote:

>
> On 2019-12-30 11:05 a.m., Manna, Animesh wrote:
>> On 24-12-2019 01:23, Harry Wentland wrote:
>>> On 2019-12-23 12:03 p.m., Animesh Manna wrote:
>>>> During phy compliance auto test mode source need to read
>>>> requested test pattern from sink through DPCD. After processing
>>>> the request source need to set the pattern. So set/get method
>>>> added in drm layer as it is DP protocol.
>>>>
>>>> v2: As per review feedback from Manasi on RFC version,
>>>> - added dp revision as function argument in set_phy_pattern api.
>>>> - used int for link_rate and u8 for lane_count to align with
>>>> existing code.
>>>>
>>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/drm_dp_helper.c | 93
>>>> +++++++++++++++++++++++++++++++++
>>>>    include/drm/drm_dp_helper.h     | 31 +++++++++++
>>>>    2 files changed, 124 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/drm_dp_helper.c
>>>> b/drivers/gpu/drm/drm_dp_helper.c
>>>> index 2c7870aef469..91c80973aa83 100644
>>>> --- a/drivers/gpu/drm/drm_dp_helper.c
>>>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>>>> @@ -1371,3 +1371,96 @@ int
>>>> drm_dp_dsc_sink_supported_input_bpcs(const u8
>>>> dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>>>>        return num_bpc;
>>>>    }
>>>>    EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>>>> +
>>>> +/**
>>>> + * drm_dp_get_phy_test_pattern() - get the requested pattern from
>>>> the sink.
>>>> + * @aux: DisplayPort AUX channel
>>>> + * @data: DP phy compliance test parameters.
>>>> + *
>>>> + * Returns 0 on success or a negative error code on failure.
>>>> + */
>>>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>>>> +                struct drm_dp_phy_test_params *data)
>>>> +{
>>>> +    int err;
>>>> +    u8 rate, lanes;
>>>> +
>>>> +    err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
>>>> +    if (err < 0)
>>>> +        return err;
>>>> +    data->link_rate = drm_dp_bw_code_to_link_rate(rate);
>>>> +
>>>> +    err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
>>>> +    if (err < 0)
>>>> +        return err;
>>>> +    data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
>>>> +
>>>> +    if (lanes & DP_ENHANCED_FRAME_CAP)
>>>> +        data->enahanced_frame_cap = true;
>>>> +
>>>> +    err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN,
>>>> &data->phy_pattern);
>>>> +    if (err < 0)
>>>> +        return err;
>>>> +
>>>> +    switch (data->phy_pattern) {
>>>> +    case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
>>>> +        err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
>>>> +                       &data->custom80, 10);
>>> Using sizeof(data->custom80) might be safer.
>>>
>>>> +        if (err < 0)
>>>> +            return err;
>>>> +
>>>> +        break;
>>>> +    case DP_PHY_TEST_PATTERN_CP2520:
>>>> +        err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
>>>> +                       &data->hbr2_reset, 2);
>>> Same here, using sizeof(data->hbr2_reset).
>>>
>>>> +        if (err < 0)
>>>> +            return err;
>>>> +    }
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
>>>> +
>>>> +/**
>>>> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
>>>> + * @aux: DisplayPort AUX channel
>>>> + * @data: DP phy compliance test parameters.
>>>> + *
>>>> + * Returns 0 on success or a negative error code on failure.
>>>> + */
>>>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>>>> +                struct drm_dp_phy_test_params *data, u8 dp_rev)
>>>> +{
>>>> +    int err, i;
>>>> +    u8 link_config[2];
>>>> +    u8 test_pattern;
>>>> +
>>>> +    link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
>>>> +    link_config[1] = data->num_lanes;
>>>> +    if (data->enahanced_frame_cap)
>>>> +        link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>>>> +    err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
>>>> +    if (err < 0)
>>>> +        return err;
>>>> +
>>>> +    test_pattern = data->phy_pattern;
>>>> +    if (dp_rev < 0x12) {
>>>> +        test_pattern = (test_pattern << 2) &
>>>> +                   DP_LINK_QUAL_PATTERN_11_MASK;
>>>> +        err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
>>>> +                     test_pattern);
>>>> +        if (err < 0)
>>>> +            return err;
>>>> +    } else {
>>>> +        for (i = 0; i < data->num_lanes; i++) {
>>>> +            err = drm_dp_dpcd_writeb(aux,
>>>> +                         DP_LINK_QUAL_LANE0_SET + i,
>>>> +                         test_pattern);
>>>> +            if (err < 0)
>>>> +                return err;
>>>> +        }
>>>> +    }
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
>>>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>>>> index d6e560870fb1..42a364748308 100644
>>>> --- a/include/drm/drm_dp_helper.h
>>>> +++ b/include/drm/drm_dp_helper.h
>>>> @@ -700,6 +700,15 @@
>>>>    # define DP_TEST_COUNT_MASK            0xf
>>>>      #define DP_PHY_TEST_PATTERN                 0x248
>>>> +# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
>>>> +# define DP_PHY_TEST_PATTERN_NONE           0x0
>>>> +# define DP_PHY_TEST_PATTERN_D10_2          0x1
>>>> +# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
>>>> +# define DP_PHY_TEST_PATTERN_PRBS7          0x3
>>>> +# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
>>>> +# define DP_PHY_TEST_PATTERN_CP2520         0x5
>>>> +
>>>> +#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
>>>>    #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
>>>>    #define    DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
>>>>    #define    DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
>>>> @@ -1570,4 +1579,26 @@ static inline void
>>>> drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>>>>      #endif
>>>>    +/**
>>>> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
>>>> + * @link: Link information.
>>> @link seems to be from a previous patch version. Please describe
>>> link_rate and num_lanes instead.
>>>
>>>> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
>>>> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
>>>> + *            0x24A and 0x24B (sink)
>>>> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
>>>> + *               through 0x259.
>>> Missing doc for enhanced_frame_cap.
>>>
>>>> + */
>>>> +struct drm_dp_phy_test_params {
>>>> +    int link_rate;
>>> Is there a reason you're not using u8 here? Would be nice to keep it
>>> consistent with num_lanes.
>> link_rate variable is used here to store actual clock value after
>> multiplying with 27000 (0.27 gbps) with link-code using
>> drm_dp_bw_code_to_link_rate().
>> Followed the same and u8 maybe not be sufficient. Added other
>> suggested changes. Thanks for review.
>>
> That makes sense. I missed that. In that case feel free to add my
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Sure will add your r-b in next version. Thanks.

Regards,
Animesh

>
> Harry
>
>> Regrads,
>> Animesh
>>
>>>> +    u8 num_lanes;
>>>> +    u8 phy_pattern;
>>>> +    u8 hbr2_reset[2];
>>>> +    u8 custom80[10];
>>>> +    bool enahanced_frame_cap;
>>> Typo. Should be enhanved_frame_cap.
>>>
>>> Harry
>>>
>>>> +};
>>>> +
>>>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>>>> +                struct drm_dp_phy_test_params *data);
>>>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>>>> +                struct drm_dp_phy_test_params *data, u8 dp_rev);
>>>>    #endif /* _DRM_DP_HELPER_H_ */
>>>>
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