From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BFC9C43603 for ; Wed, 18 Dec 2019 20:08:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E8BA82176D for ; Wed, 18 Dec 2019 20:08:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E8BA82176D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3FA6689DA2; Wed, 18 Dec 2019 20:08:34 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 23C3089DA2 for ; Wed, 18 Dec 2019 20:08:33 +0000 (UTC) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Dec 2019 12:08:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,330,1571727600"; d="scan'208";a="266982128" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by FMSMGA003.fm.intel.com with SMTP; 18 Dec 2019 12:08:30 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 18 Dec 2019 22:08:29 +0200 Date: Wed, 18 Dec 2019 22:08:29 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: =?iso-8859-1?Q?Jos=E9?= Roberto de Souza Message-ID: <20191218200829.GZ1208@intel.com> References: <20191218185910.303540-1-jose.souza@intel.com> <20191218185910.303540-4-jose.souza@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191218185910.303540-4-jose.souza@intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH v4 4/6] drm/i915/dp: Fix MST disable sequences X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Lucas De Marchi Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Dec 18, 2019 at 10:59:08AM -0800, Jos=E9 Roberto de Souza wrote: > The disable sequence after wait for transcoder off was not correctly > implemented. > The MST disable sequence is basically the same for HSW, SKL, ICL and > TGL, with just minor changes for TGL. > = > With this last patch we finally fixed the hotplugs triggered by MST > sinks during the disable/enable sequence, those were causing source > to try to do a link training while it was not ready causing CPU pipe > FIFO underrrus on TGL. > = > v2: Only unsetting TGL_TRANS_DDI_PORT_MASK for TGL on the post > disable sequence > = > v4: Rebased, moved MST sequences to intel_mst_post_disable_dp() > = > BSpec: 4231 > BSpec: 4163 > BSpec: 22243 > BSpec: 49190 > Cc: Ville Syrj=E4l=E4 > Cc: Lucas De Marchi > Signed-off-by: Jos=E9 Roberto de Souza > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 33 +++++++++++++++------ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 33 +++++++++++++-------- > 2 files changed, 44 insertions(+), 22 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i= 915/display/intel_ddi.c > index 9d99ec82d072..94ca26be2fee 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -34,6 +34,7 @@ > #include "intel_ddi.h" > #include "intel_display_types.h" > #include "intel_dp.h" > +#include "intel_dp_mst.h" > #include "intel_dp_link_training.h" > #include "intel_dpio_phy.h" > #include "intel_dsi.h" > @@ -1949,17 +1950,19 @@ void intel_ddi_disable_transcoder_func(const stru= ct intel_crtc_state *crtc_state > struct intel_crtc *crtc =3D to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv =3D to_i915(crtc->base.dev); > enum transcoder cpu_transcoder =3D crtc_state->cpu_transcoder; > - i915_reg_t reg =3D TRANS_DDI_FUNC_CTL(cpu_transcoder); > - u32 val =3D I915_READ(reg); > + u32 val; > + > + val =3D I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); > + val &=3D ~TRANS_DDI_FUNC_ENABLE; > = > if (INTEL_GEN(dev_priv) >=3D 12) { > - val &=3D ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK | > - TRANS_DDI_DP_VC_PAYLOAD_ALLOC); > + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || > + intel_dp_mst_is_slave_trans(crtc_state)) if (!intel_dp_mst_is_master_trans()) val &=3D ...; ? > + val &=3D ~TGL_TRANS_DDI_PORT_MASK; > } else { > - val &=3D ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | > - TRANS_DDI_DP_VC_PAYLOAD_ALLOC); > + val &=3D ~TRANS_DDI_PORT_MASK; > } > - I915_WRITE(reg, val); > + I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), val); > = > if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { > @@ -3808,8 +3811,20 @@ static void intel_ddi_post_disable_dp(struct intel= _encoder *encoder, > */ > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); > = > - if (INTEL_GEN(dev_priv) < 12 && !is_mst) > - intel_ddi_disable_pipe_clock(old_crtc_state); > + if (INTEL_GEN(dev_priv) >=3D 12) { > + if (is_mst) { if (intel_dp_mst_is_master_trans()) { ? > + enum transcoder cpu_transcoder; > + u32 val; > + > + cpu_transcoder =3D old_crtc_state->cpu_transcoder; Assignment can be done when declaring the variable. > + val =3D I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); > + val &=3D ~TGL_TRANS_DDI_PORT_MASK; > + I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), val); > + } > + } else { > + if (!is_mst) > + intel_ddi_disable_pipe_clock(old_crtc_state); > + } > = > intel_disable_ddi_buf(encoder, old_crtc_state); > = > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/dr= m/i915/display/intel_dp_mst.c > index 710137984c71..efd14b0b507b 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -347,6 +347,7 @@ static void intel_mst_post_disable_dp(struct intel_en= coder *encoder, > to_intel_connector(old_conn_state->connector); > struct drm_i915_private *dev_priv =3D to_i915(connector->base.dev); > bool last_mst_stream; > + u32 val; > = > intel_dp->active_mst_links--; > last_mst_stream =3D intel_dp->active_mst_links =3D=3D 0; > @@ -357,6 +358,19 @@ static void intel_mst_post_disable_dp(struct intel_e= ncoder *encoder, > = > intel_disable_pipe(old_crtc_state); > = > + drm_dp_update_payload_part2(&intel_dp->mst_mgr); Hmm. I'm having hard to figuring out what these things do. But from a cursory glance it almost looks like part1 is the one that does the AUX stuff to deallocate stuff. So feels like even that part should be here. > + > + val =3D I915_READ(TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder)); > + val &=3D ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; > + I915_WRITE(TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), val); > + > + if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > + DP_TP_STATUS_ACT_SENT, 1)) > + DRM_ERROR("Timed out waiting for ACT sent when disabling\n"); I guess we were missing this step entirely. Dunno if we want ERROR for this. Not sure how much noise it'll generate when someone forcefully yanks the cable... > + drm_dp_check_act_status(&intel_dp->mst_mgr); > + > + drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port); This seems to be pure sw stuff so not so critical where it is. Keeping it next to the hw payload deallocation seems like a good approach. > + > intel_ddi_disable_transcoder_func(old_crtc_state); > = > if (INTEL_GEN(dev_priv) >=3D 9) > @@ -364,6 +378,12 @@ static void intel_mst_post_disable_dp(struct intel_e= ncoder *encoder, > else > ironlake_pfit_disable(old_crtc_state); > = > + /* > + * Power down mst path before disabling the port, otherwise we end > + * up getting interrupts from the sink upon detecting link loss. > + */ > + drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, > + false); And I guess this was needed to avoid the link loss screams from the sink? Seems to match the spec better than before at least. Still a bit unsure about he part1/2 stuff for the deallocation. But if that should be changed we can do it as a followup. The code movement into .post_disable() really did make for a much nicer experience when comparing with the spec. Or at least I didn't lose as much hair as with the previous version :) Reviewed-by: Ville Syrj=E4l=E4 > /* > * From TGL spec: "If multi-stream slave transcoder: Configure > * Transcoder Clock Select to direct no clock to the transcoder" > @@ -374,19 +394,6 @@ static void intel_mst_post_disable_dp(struct intel_e= ncoder *encoder, > if (INTEL_GEN(dev_priv) < 12 || !last_mst_stream) > intel_ddi_disable_pipe_clock(old_crtc_state); > = > - /* this can fail */ > - drm_dp_check_act_status(&intel_dp->mst_mgr); > - /* and this can also fail */ > - drm_dp_update_payload_part2(&intel_dp->mst_mgr); > - > - drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port); > - > - /* > - * Power down mst path before disabling the port, otherwise we end > - * up getting interrupts from the sink upon detecting link loss. > - */ > - drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, > - false); > = > intel_mst->connector =3D NULL; > if (last_mst_stream) > -- = > 2.24.1 -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx