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Wed, 18 Dec 2019 15:57:53 -0800 (PST) Date: Wed, 18 Dec 2019 15:57:53 -0800 From: Sukadev Bhattiprolu To: Michael Ellerman Subject: Re: [PATCH 1/2] powerpc/pseries/svm: Don't access some SPRs Message-ID: <20191218235753.GA12285@us.ibm.com> References: <20191218043048.3400-1-sukadev@linux.ibm.com> <875zidoqok.fsf@mpe.ellerman.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <875zidoqok.fsf@mpe.ellerman.id.au> X-Operating-System: Linux 2.0.32 on an i486 User-Agent: Mutt/1.10.1 (2018-07-13) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-18_08:2019-12-17,2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 priorityscore=1501 adultscore=0 mlxlogscore=839 mlxscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180177 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andmike@linux.ibm.com, linuxram@us.ibm.com, kvm-ppc@vger.kernel.org, linuxppc-dev@ozlabs.org, Sukadev Bhattiprolu , bauerman@linux.ibm.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Michael Ellerman [mpe@ellerman.id.au] wrote: > > eg. here. > > This is the fast path of context switch. > > That expands to: > > if (!(mfmsr() & MSR_S)) > asm volatile("mfspr %0, SPRN_BESCR" : "=r" (rval)); > if (!(mfmsr() & MSR_S)) > asm volatile("mfspr %0, SPRN_EBBHR" : "=r" (rval)); > if (!(mfmsr() & MSR_S)) > asm volatile("mfspr %0, SPRN_EBBRR" : "=r" (rval)); > Yes, should have optimized this at least :-) > > If the Ultravisor is going to disable EBB and BHRB then we need new > CPU_FTR bits for those, and the code that accesses those registers > needs to be put behind cpu_has_feature(EBB) etc. Will try the cpu_has_feature(). Would it be ok to use a single feature bit, like UV or make it per-register group as that could need more feature bits? Thanks, Sukadev From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sukadev Bhattiprolu Date: Wed, 18 Dec 2019 23:57:53 +0000 Subject: Re: [PATCH 1/2] powerpc/pseries/svm: Don't access some SPRs Message-Id: <20191218235753.GA12285@us.ibm.com> List-Id: References: <20191218043048.3400-1-sukadev@linux.ibm.com> <875zidoqok.fsf@mpe.ellerman.id.au> In-Reply-To: <875zidoqok.fsf@mpe.ellerman.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Michael Ellerman Cc: andmike@linux.ibm.com, linuxram@us.ibm.com, kvm-ppc@vger.kernel.org, linuxppc-dev@ozlabs.org, Sukadev Bhattiprolu , bauerman@linux.ibm.com Michael Ellerman [mpe@ellerman.id.au] wrote: > > eg. here. > > This is the fast path of context switch. > > That expands to: > > if (!(mfmsr() & MSR_S)) > asm volatile("mfspr %0, SPRN_BESCR" : "=r" (rval)); > if (!(mfmsr() & MSR_S)) > asm volatile("mfspr %0, SPRN_EBBHR" : "=r" (rval)); > if (!(mfmsr() & MSR_S)) > asm volatile("mfspr %0, SPRN_EBBRR" : "=r" (rval)); > Yes, should have optimized this at least :-) > > If the Ultravisor is going to disable EBB and BHRB then we need new > CPU_FTR bits for those, and the code that accesses those registers > needs to be put behind cpu_has_feature(EBB) etc. Will try the cpu_has_feature(). Would it be ok to use a single feature bit, like UV or make it per-register group as that could need more feature bits? Thanks, Sukadev