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From: Lubomir Rintel <lkundrak@v3.sk>
To: Olof Johansson <olof@lixom.net>
Cc: Arnd Bergmann <arnd@arndb.de>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, soc@kernel.org,
	Lubomir Rintel <lkundrak@v3.sk>
Subject: [PATCH 2/5] clk: mmp2: Add HSIC clocks
Date: Fri, 20 Dec 2019 07:53:11 +0100	[thread overview]
Message-ID: <20191220065314.237624-3-lkundrak@v3.sk> (raw)
In-Reply-To: <20191220065314.237624-1-lkundrak@v3.sk>

There are two USB HSIC controllers on MMP2 and MMP3.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
 drivers/clk/mmp/clk-of-mmp2.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index a60a1be937ad6..05834953e1fd3 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -53,6 +53,8 @@
 #define APMU_DISP1	0x110
 #define APMU_CCIC0	0x50
 #define APMU_CCIC1	0xf4
+#define APMU_USBHSIC0	0xf8
+#define APMU_USBHSIC1	0xfc
 #define MPMU_UART_PLL	0x14
 
 struct mmp2_clk_unit {
@@ -194,6 +196,8 @@ static struct mmp_clk_mix_config sdh_mix_config = {
 };
 
 static DEFINE_SPINLOCK(usb_lock);
+static DEFINE_SPINLOCK(usbhsic0_lock);
+static DEFINE_SPINLOCK(usbhsic1_lock);
 
 static DEFINE_SPINLOCK(disp0_lock);
 static DEFINE_SPINLOCK(disp1_lock);
@@ -224,6 +228,8 @@ static struct mmp_param_div_clk apmu_div_clks[] = {
 
 static struct mmp_param_gate_clk apmu_gate_clks[] = {
 	{MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
+	{MMP2_CLK_USBHSIC0, "usbhsic0_clk", "usb_pll", 0, APMU_USBHSIC0, 0x1b, 0x1b, 0x0, 0, &usbhsic0_lock},
+	{MMP2_CLK_USBHSIC1, "usbhsic1_clk", "usb_pll", 0, APMU_USBHSIC1, 0x1b, 0x1b, 0x0, 0, &usbhsic1_lock},
 	/* The gate clocks has mux parent. */
 	{MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
 	{MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
-- 
2.24.1


  parent reply	other threads:[~2019-12-20  6:53 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-20  6:53 [PATCH 1/5] Enable HSIC on MMP3 SoC Lubomir Rintel
2019-12-20  6:53 ` [PATCH 1/5] dt-bindings: marvell,mmp2: Add clock ids for the HSIC clocks Lubomir Rintel
2019-12-23 19:32   ` Stephen Boyd
2019-12-20  6:53 ` Lubomir Rintel [this message]
2019-12-23 19:33   ` [PATCH 2/5] clk: mmp2: Add " Stephen Boyd
2019-12-20  6:53 ` [PATCH 3/5] dt-bindings: phy: Add binding for marvell,mmp3-hsic-phy Lubomir Rintel
2020-01-07 22:20   ` Rob Herring
2019-12-20  6:53 ` [PATCH 4/5] ARM: dts: mmp3: Add HSIC controllers Lubomir Rintel
2019-12-20  7:05   ` Lubomir Rintel
2020-01-06 19:22     ` Olof Johansson
2019-12-23  9:57   ` kbuild test robot
2019-12-23  9:57     ` kbuild test robot
2019-12-20  6:53 ` [PATCH 5/5] ARM: dts: mmp3-dell-ariel: Enable the HSIC Lubomir Rintel

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