[PATCH 2/2] net: AWS ENA: Flush WCBs before writing new SQ tail to doorbell

[Liran Alon <liran.alon@oracle.com>]

AWS ENA NIC supports Tx SQ in Low Latency Queue (LLQ) mode (Also
referred to as "push-mode"). In this mode, the driver pushes the
transmit descriptors and the first 128 bytes of the packet directly
to the ENA device memory space, while the rest of the packet payload
is fetched by the device from host memory. For this operation mode,
the driver uses a dedicated PCI BAR which is mapped as WC memory.

The function ena_com_write_bounce_buffer_to_dev() is responsible
to write to the above mentioned PCI BAR.

When the write of new SQ tail to doorbell is visible to device, device
expects to be able to read relevant transmit descriptors and packets
headers from device memory. Therefore, driver should ensure
write-combined buffers (WCBs) are flushed before the write to doorbell
is visible to the device.

For some CPUs, this will be taken care of by writel(). For example,
x86 Intel CPUs flushes write-combined buffers when a read or write
is done to UC memory (In our case, the doorbell). See Intel SDM section
11.3 METHODS OF CACHING AVAILABLE:
"If the WC buffer is partially filled, the writes may be delayed until
the next occurrence of a serializing event; such as, an SFENCE or MFENCE
instruction, CPUID execution, a read or write to uncached memory, an
interrupt occurrence, or a LOCK instruction execution.”

However, other CPUs do not provide this guarantee. For example, x86
AMD CPUs flush write-combined buffers only on a read from UC memory.
Not a write to UC memory. See AMD Software Optimisation Guide for AMD
Family 17h Processors section 2.13.3 Write-Combining Operations.

Therefore, modify ena_com_write_sq_doorbell() to flush write-combined
buffers with wmb() in case Tx SQ is in LLQ mode.

Note that this cause 2 theoretical unnecessary perf hits:
(1) On x86 Intel, this will execute unnecessary SFENCE.
But probably the perf impact is neglictable because it will also
cause the implciit SFENCE done internally by write to UC memory to do
less work.
(2) On ARM64 this will change from using dma_wmb() to using wmb()
which is more costly (Use DSB instead of DMB) even though DMB should be
sufficient to flush WCBs.

This patch will focus on making sure WCBs are flushed on all CPUs, and a
later future patch will be made to add a new macro to Linux such as
flush_wc_writeX() that does the right thing for all archs and CPU
vendors.

Reviewed-by: Håkon Bugge <haakon.bugge@oracle.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
---
 drivers/net/ethernet/amazon/ena/ena_eth_com.h | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/amazon/ena/ena_eth_com.h b/drivers/net/ethernet/amazon/ena/ena_eth_com.h
index 77986c0ea52c..f9bfaef08bfa 100644
--- a/drivers/net/ethernet/amazon/ena/ena_eth_com.h
+++ b/drivers/net/ethernet/amazon/ena/ena_eth_com.h
@@ -179,7 +179,22 @@ static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
 	pr_debug("write submission queue doorbell for queue: %d tail: %d\n",
 		 io_sq->qid, tail);
 
-	writel(tail, io_sq->db_addr);
+	/*
+	 * When Tx SQ is in LLQ mode, transmit descriptors and packet headers
+	 * are written to device-memory mapped as WC. Therefore, we need to
+	 * ensure write-combined buffers are flushed before writing new SQ
+	 * tail to doorbell.
+	 *
+	 * On some CPUs (E.g. x86 AMD) writel() doesn't guarantee this.
+	 * Therefore, prefer to explicitly flush write-combined buffers
+	 * with wmb() before writing to doorbell in case Tx SQ is in LLQ mode.
+	 */
+	if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
+		wmb();
+		writel_relaxed(tail, io_sq->db_addr);
+	} else {
+		writel(tail, io_sq->db_addr);
+	}
 
 	if (is_llq_max_tx_burst_exists(io_sq)) {
 		pr_debug("reset available entries in tx burst for queue %d to %d\n",
-- 
2.20.1