* [Intel-gfx] [PATCH i-g-t v2] i915/perf: Find the associated perf-type for a particular device
@ 2020-01-04 15:37 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-04 15:37 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Since with multiple devices, we may have multiple different perf_pmu
each with their own type, we want to find the right one for the job.
The tests are run with a specific fd, from which we can extract the
appropriate bus-id and find the associated perf-type. The performance
monitoring tools are a little more general and not yet ready to probe
all device or bind to one in particular, so we just assume the default
igfx for the time being.
v2: Extract the bus address from out of sysfs
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
benchmarks/gem_wsim.c | 4 +-
lib/igt_perf.c | 77 ++++++++++++++++++++++++++++---
lib/igt_perf.h | 13 ++++--
overlay/gem-interrupts.c | 2 +-
overlay/gpu-freq.c | 4 +-
overlay/gpu-top.c | 12 ++---
overlay/rc6.c | 2 +-
tests/i915/gem_ctx_freq.c | 2 +-
tests/i915/gem_ctx_sseu.c | 2 +-
tests/i915/gem_exec_balancer.c | 18 +++++---
tests/perf_pmu.c | 84 ++++++++++++++++++----------------
tools/intel_gpu_top.c | 2 +-
12 files changed, 152 insertions(+), 70 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 6305e0d7a..9156fdc90 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
for (d = &engines[0]; d->id != VCS; d++) {
int pfd;
- pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
- d->inst),
+ pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ d->inst),
bb->fd);
if (pfd < 0) {
if (d->id != VCS2)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index e3dec2cc2..1537faf80 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -4,17 +4,70 @@
#include <stdlib.h>
#include <string.h>
#include <errno.h>
+#include <sys/stat.h>
#include <sys/sysinfo.h>
+#include <sys/sysmacros.h>
#include "igt_perf.h"
-uint64_t i915_type_id(void)
+static char *bus_address(int i915, char *path, int pathlen)
+{
+ struct stat st;
+ int len = -1;
+ int dir;
+
+ if (fstat(i915, &st) || !S_ISCHR(st.st_mode))
+ return NULL;
+
+ snprintf(path, pathlen, "/sys/dev/char/%d:%d",
+ major(st.st_rdev), minor(st.st_rdev));
+
+ dir = open(path, O_RDONLY);
+ if (dir != -1) {
+ len = readlinkat(dir, "device", path, pathlen - 1);
+ close(dir);
+ }
+ if (len < 0)
+ return NULL;
+
+ path[len] = '\0';
+ return path;
+}
+
+const char *i915_perf_device(int i915, char *buf, int buflen)
+{
+#define prefix "i915-"
+#define plen strlen(prefix)
+
+ if (!buf || buflen < plen)
+ return "i915";
+
+ memcpy(buf, prefix, plen);
+
+ if (!bus_address(i915, buf + plen, buflen - plen) ||
+ strcmp(buf + plen, "0000:00:02.0") == 0) /* legacy name for igfx */
+ buf[plen - 1] = '\0';
+
+ return buf;
+}
+
+uint64_t i915_perf_type_id(int i915)
+{
+ char buf[80];
+
+ return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
+}
+
+uint64_t igt_perf_type_id(const char *device)
{
char buf[64];
ssize_t ret;
int fd;
- fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
+ snprintf(buf, sizeof(buf),
+ "/sys/bus/event_source/devices/%s/type", device);
+
+ fd = open(buf, O_RDONLY);
if (fd < 0)
return 0;
@@ -52,15 +105,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
return ret;
}
-int perf_i915_open(uint64_t config)
+int perf_igfx_open(uint64_t config)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
+
+int perf_igfx_open_group(uint64_t config, int group)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, group,
+ PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
+}
+
+int perf_i915_open(int i915, uint64_t config)
{
- return _perf_open(i915_type_id(), config, -1,
+ return _perf_open(i915_perf_type_id(i915), config, -1,
PERF_FORMAT_TOTAL_TIME_ENABLED);
}
-int perf_i915_open_group(uint64_t config, int group)
+int perf_i915_open_group(int i915, uint64_t config, int group)
{
- return _perf_open(i915_type_id(), config, group,
+ return _perf_open(i915_perf_type_id(i915), config, group,
PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index e00718f47..a8328c70c 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
}
-uint64_t i915_type_id(void);
-int perf_i915_open(uint64_t config);
-int perf_i915_open_group(uint64_t config, int group);
+uint64_t igt_perf_type_id(const char *device);
int igt_perf_open(uint64_t type, uint64_t config);
int igt_perf_open_group(uint64_t type, uint64_t config, int group);
+const char *i915_perf_device(int i915, char *buf, int buflen);
+uint64_t i915_perf_type_id(int i915);
+
+int perf_igfx_open(uint64_t config);
+int perf_igfx_open_group(uint64_t config, int group);
+
+int perf_i915_open(int i915, uint64_t config);
+int perf_i915_open_group(int i915, uint64_t config, int group);
+
#endif /* I915_PERF_H */
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index 0233fbb05..be73b6931 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
{
memset(irqs, 0, sizeof(*irqs));
- irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
+ irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
if (irqs->fd < 0 && interrupts_read() < 0)
irqs->error = ENODEV;
diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
index 0d8032592..b73157d39 100644
--- a/overlay/gpu-freq.c
+++ b/overlay/gpu-freq.c
@@ -37,8 +37,8 @@ static int perf_open(void)
{
int fd;
- fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
- if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
+ fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
+ if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
close(fd);
fd = -1;
}
diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 6cec2e943..32123abdd 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
d = &engines[0];
- gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
+ gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
-1);
if (gt->fd < 0)
return -1;
- if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
gt->fd) >= 0)
gt->have_wait = 1;
- if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
gt->fd) >= 0)
gt->have_sema = 1;
@@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
gt->num_rings = 1;
for (d++; d->name; d++) {
- if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
d->inst),
gt->fd) < 0)
continue;
if (gt->have_wait &&
- perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
d->inst),
gt->fd) < 0)
return -1;
if (gt->have_sema &&
- perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
d->inst),
gt->fd) < 0)
return -1;
diff --git a/overlay/rc6.c b/overlay/rc6.c
index b5286f0cf..69f95f288 100644
--- a/overlay/rc6.c
+++ b/overlay/rc6.c
@@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
{
memset(rc6, 0, sizeof(*rc6));
- rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
+ rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
if (rc6->fd < 0) {
struct stat st;
if (stat("/sys/class/drm/card0/power", &st) < 0)
diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
index 89f3d11ef..5d2d3ec31 100644
--- a/tests/i915/gem_ctx_freq.c
+++ b/tests/i915/gem_ctx_freq.c
@@ -136,7 +136,7 @@ static void sysfs_range(int i915)
triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
- pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+ pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
igt_require(pmu >= 0);
for (int outer = 0; outer <= 2*N_STEPS; outer++) {
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
index 48e4411c8..38dc584bc 100644
--- a/tests/i915/gem_ctx_sseu.c
+++ b/tests/i915/gem_ctx_sseu.c
@@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
static bool has_engine(int fd, unsigned int class, unsigned int instance)
{
- int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
if (pmu >= 0)
close(pmu);
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index f4909a978..cebcc39c7 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
{
int fd;
- fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
if (fd != -1) {
close(fd);
return true;
@@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
}
}
-static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
+static int
+add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
{
- return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
+ return perf_i915_open_group(i915,
+ I915_PMU_ENGINE_BUSY(ci->engine_class,
ci->engine_instance),
pmu);
}
@@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
double load;
int pmu;
- pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
+ pmu = perf_i915_open(i915,
+ I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
ci[idx].engine_instance));
spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
@@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
pmu[0] = -1;
for (int i = 0; i < limit; i++)
- pmu[i] = add_pmu(pmu[0], &siblings[i]);
- pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
+ pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
+ pmu[limit] = add_pmu(i915,
+ pmu[0], &master_engines[bond]);
igt_assert(siblings[bond].engine_class !=
master_engines[bond].engine_class);
@@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
for (unsigned int n = 0; n < count; n++) {
uint32_t ctx;
- pmu[n] = add_pmu(pmu[0], &ci[n]);
+ pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
if (flags & PULSE) {
struct drm_i915_gem_execbuffer2 eb = {
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index e1bbf2410..3e179daef 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
const double tolerance = 0.05f;
const unsigned long batch_duration_ns = 500e6;
-static int open_pmu(uint64_t config)
+static int open_pmu(int i915, uint64_t config)
{
int fd;
- fd = perf_i915_open(config);
+ fd = perf_i915_open(i915, config);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
return fd;
}
-static int open_group(uint64_t config, int group)
+static int open_group(int i915, uint64_t config, int group)
{
int fd;
- fd = perf_i915_open_group(config, group);
+ fd = perf_i915_open_group(i915, config, group);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
@@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
bool exists;
errno = 0;
- fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
+ fd = perf_i915_open(gem_fd,
+ __I915_PMU_ENGINE(e->class, e->instance, sample));
if (fd < 0)
err = errno;
@@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val;
int fd;
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
spin = __spin_sync(gem_fd, 0, e);
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
* Open PMU as fast as possible after the second spin batch in attempt
* to be faster than the driver handling lite-restore.
*/
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
if (e->class == e_->class && e->instance == e_->instance)
busy_idx = i;
- fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
+ fd[i++] = open_group(gem_fd,
+ I915_PMU_ENGINE_BUSY(e_->class,
e_->instance),
fd[0]);
}
@@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val[2][2];
int fd;
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
* to expected time spent in semaphore wait state.
*/
- fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -817,8 +820,9 @@ sema_busy(int gem_fd,
igt_require(gem_scheduler_has_semaphores(gem_fd));
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
__for_each_physical_engine(gem_fd, signal) {
if (e->class == signal->class &&
@@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
data.pipe = p;
prepare_crtc(&data, gem_fd, output);
- fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_WAIT(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
gem_quiescent_gpu(gem_fd);
- fd[0] = open_pmu(config);
+ fd[0] = open_pmu(gem_fd, config);
/*
* Second PMU client which is initialized after the first one,
* and exists before it, should not affect accounting as reported
* in the first client.
*/
- fd[1] = open_pmu(config);
+ fd[1] = open_pmu(gem_fd, config);
spin = spin_sync(gem_fd, 0, e);
@@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
* - cpu != 0 is not supported since i915 PMU only allows running on one cpu
* and that is normally CPU0.
*/
-static void invalid_init(void)
+static void invalid_init(int i915)
{
struct perf_event_attr attr;
@@ -1093,7 +1098,7 @@ static void invalid_init(void)
do { \
memset(&attr, 0, sizeof (attr)); \
attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
- attr.type = i915_type_id(); \
+ attr.type = i915_perf_type_id(i915); \
igt_assert(attr.type != 0); \
errno = 0; \
} while(0)
@@ -1112,11 +1117,11 @@ do { \
igt_assert_eq(errno, EINVAL);
}
-static void init_other(unsigned int i, bool valid)
+static void init_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
close(fd);
}
-static void read_other(unsigned int i, bool valid)
+static void read_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
igt_require(cpu0_hotplug_support());
- fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
/*
* Create two spinners so test can ensure shorter gaps in engine
@@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++) {
@@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++)
@@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
igt_require(max_freq > min_freq);
igt_require(boost_freq > min_freq);
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
/*
* Set GPU to min frequency and read PMU counters.
@@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
/* While parked, our convention is to report the GPU at 0Hz */
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
gem_quiescent_gpu(gem_fd); /* Be idle! */
measured_usleep(2000); /* Wait for timers to cease */
@@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_RC6_RESIDENCY);
+ fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
if (flags & TEST_RUNTIME_PM) {
drmModeRes *res;
@@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
usleep(500e3);
/* Enable the PMU. */
- fd = open_pmu(config);
+ fd = open_pmu(gem_fd, config);
/* Stop load and close the PMU. */
igt_stop_helper(&engine_load);
@@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
igt_spin_free(gem_fd, spin);
}
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
/* Let the child run. */
read(link[0], &expected, sizeof(expected));
@@ -1835,7 +1841,7 @@ igt_main
fd = drm_open_driver_master(DRIVER_INTEL);
igt_require_gem(fd);
- igt_require(i915_type_id() > 0);
+ igt_require(i915_perf_type_id(fd) > 0);
__for_each_physical_engine(fd, e)
num_engines++;
@@ -1845,7 +1851,7 @@ igt_main
* Test invalid access via perf API is rejected.
*/
igt_subtest("invalid-init")
- invalid_init();
+ invalid_init(fd);
__for_each_physical_engine(fd, e) {
const unsigned int pct[] = { 2, 50, 98 };
@@ -1996,10 +2002,10 @@ igt_main
*/
for (i = 0; i < num_other_metrics + 1; i++) {
igt_subtest_f("other-init-%u", i)
- init_other(i, i < num_other_metrics);
+ init_other(fd, i, i < num_other_metrics);
igt_subtest_f("other-read-%u", i)
- read_other(i, i < num_other_metrics);
+ read_other(fd, i, i < num_other_metrics);
}
/**
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index cc8db7c53..8197482dd 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
({ \
int fd__; \
\
- fd__ = perf_i915_open_group((pmu)->config, (fd)); \
+ fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
if (fd__ >= 0) { \
if ((fd) == -1) \
(fd) = fd__; \
--
2.25.0.rc0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t v2] i915/perf: Find the associated perf-type for a particular device
@ 2020-01-04 15:37 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-04 15:37 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
Since with multiple devices, we may have multiple different perf_pmu
each with their own type, we want to find the right one for the job.
The tests are run with a specific fd, from which we can extract the
appropriate bus-id and find the associated perf-type. The performance
monitoring tools are a little more general and not yet ready to probe
all device or bind to one in particular, so we just assume the default
igfx for the time being.
v2: Extract the bus address from out of sysfs
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
benchmarks/gem_wsim.c | 4 +-
lib/igt_perf.c | 77 ++++++++++++++++++++++++++++---
lib/igt_perf.h | 13 ++++--
overlay/gem-interrupts.c | 2 +-
overlay/gpu-freq.c | 4 +-
overlay/gpu-top.c | 12 ++---
overlay/rc6.c | 2 +-
tests/i915/gem_ctx_freq.c | 2 +-
tests/i915/gem_ctx_sseu.c | 2 +-
tests/i915/gem_exec_balancer.c | 18 +++++---
tests/perf_pmu.c | 84 ++++++++++++++++++----------------
tools/intel_gpu_top.c | 2 +-
12 files changed, 152 insertions(+), 70 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 6305e0d7a..9156fdc90 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
for (d = &engines[0]; d->id != VCS; d++) {
int pfd;
- pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
- d->inst),
+ pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ d->inst),
bb->fd);
if (pfd < 0) {
if (d->id != VCS2)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index e3dec2cc2..1537faf80 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -4,17 +4,70 @@
#include <stdlib.h>
#include <string.h>
#include <errno.h>
+#include <sys/stat.h>
#include <sys/sysinfo.h>
+#include <sys/sysmacros.h>
#include "igt_perf.h"
-uint64_t i915_type_id(void)
+static char *bus_address(int i915, char *path, int pathlen)
+{
+ struct stat st;
+ int len = -1;
+ int dir;
+
+ if (fstat(i915, &st) || !S_ISCHR(st.st_mode))
+ return NULL;
+
+ snprintf(path, pathlen, "/sys/dev/char/%d:%d",
+ major(st.st_rdev), minor(st.st_rdev));
+
+ dir = open(path, O_RDONLY);
+ if (dir != -1) {
+ len = readlinkat(dir, "device", path, pathlen - 1);
+ close(dir);
+ }
+ if (len < 0)
+ return NULL;
+
+ path[len] = '\0';
+ return path;
+}
+
+const char *i915_perf_device(int i915, char *buf, int buflen)
+{
+#define prefix "i915-"
+#define plen strlen(prefix)
+
+ if (!buf || buflen < plen)
+ return "i915";
+
+ memcpy(buf, prefix, plen);
+
+ if (!bus_address(i915, buf + plen, buflen - plen) ||
+ strcmp(buf + plen, "0000:00:02.0") == 0) /* legacy name for igfx */
+ buf[plen - 1] = '\0';
+
+ return buf;
+}
+
+uint64_t i915_perf_type_id(int i915)
+{
+ char buf[80];
+
+ return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
+}
+
+uint64_t igt_perf_type_id(const char *device)
{
char buf[64];
ssize_t ret;
int fd;
- fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
+ snprintf(buf, sizeof(buf),
+ "/sys/bus/event_source/devices/%s/type", device);
+
+ fd = open(buf, O_RDONLY);
if (fd < 0)
return 0;
@@ -52,15 +105,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
return ret;
}
-int perf_i915_open(uint64_t config)
+int perf_igfx_open(uint64_t config)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
+
+int perf_igfx_open_group(uint64_t config, int group)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, group,
+ PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
+}
+
+int perf_i915_open(int i915, uint64_t config)
{
- return _perf_open(i915_type_id(), config, -1,
+ return _perf_open(i915_perf_type_id(i915), config, -1,
PERF_FORMAT_TOTAL_TIME_ENABLED);
}
-int perf_i915_open_group(uint64_t config, int group)
+int perf_i915_open_group(int i915, uint64_t config, int group)
{
- return _perf_open(i915_type_id(), config, group,
+ return _perf_open(i915_perf_type_id(i915), config, group,
PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index e00718f47..a8328c70c 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
}
-uint64_t i915_type_id(void);
-int perf_i915_open(uint64_t config);
-int perf_i915_open_group(uint64_t config, int group);
+uint64_t igt_perf_type_id(const char *device);
int igt_perf_open(uint64_t type, uint64_t config);
int igt_perf_open_group(uint64_t type, uint64_t config, int group);
+const char *i915_perf_device(int i915, char *buf, int buflen);
+uint64_t i915_perf_type_id(int i915);
+
+int perf_igfx_open(uint64_t config);
+int perf_igfx_open_group(uint64_t config, int group);
+
+int perf_i915_open(int i915, uint64_t config);
+int perf_i915_open_group(int i915, uint64_t config, int group);
+
#endif /* I915_PERF_H */
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index 0233fbb05..be73b6931 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
{
memset(irqs, 0, sizeof(*irqs));
- irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
+ irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
if (irqs->fd < 0 && interrupts_read() < 0)
irqs->error = ENODEV;
diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
index 0d8032592..b73157d39 100644
--- a/overlay/gpu-freq.c
+++ b/overlay/gpu-freq.c
@@ -37,8 +37,8 @@ static int perf_open(void)
{
int fd;
- fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
- if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
+ fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
+ if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
close(fd);
fd = -1;
}
diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 6cec2e943..32123abdd 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
d = &engines[0];
- gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
+ gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
-1);
if (gt->fd < 0)
return -1;
- if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
gt->fd) >= 0)
gt->have_wait = 1;
- if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
gt->fd) >= 0)
gt->have_sema = 1;
@@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
gt->num_rings = 1;
for (d++; d->name; d++) {
- if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
d->inst),
gt->fd) < 0)
continue;
if (gt->have_wait &&
- perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
d->inst),
gt->fd) < 0)
return -1;
if (gt->have_sema &&
- perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
d->inst),
gt->fd) < 0)
return -1;
diff --git a/overlay/rc6.c b/overlay/rc6.c
index b5286f0cf..69f95f288 100644
--- a/overlay/rc6.c
+++ b/overlay/rc6.c
@@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
{
memset(rc6, 0, sizeof(*rc6));
- rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
+ rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
if (rc6->fd < 0) {
struct stat st;
if (stat("/sys/class/drm/card0/power", &st) < 0)
diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
index 89f3d11ef..5d2d3ec31 100644
--- a/tests/i915/gem_ctx_freq.c
+++ b/tests/i915/gem_ctx_freq.c
@@ -136,7 +136,7 @@ static void sysfs_range(int i915)
triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
- pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+ pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
igt_require(pmu >= 0);
for (int outer = 0; outer <= 2*N_STEPS; outer++) {
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
index 48e4411c8..38dc584bc 100644
--- a/tests/i915/gem_ctx_sseu.c
+++ b/tests/i915/gem_ctx_sseu.c
@@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
static bool has_engine(int fd, unsigned int class, unsigned int instance)
{
- int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
if (pmu >= 0)
close(pmu);
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index f4909a978..cebcc39c7 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
{
int fd;
- fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
if (fd != -1) {
close(fd);
return true;
@@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
}
}
-static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
+static int
+add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
{
- return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
+ return perf_i915_open_group(i915,
+ I915_PMU_ENGINE_BUSY(ci->engine_class,
ci->engine_instance),
pmu);
}
@@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
double load;
int pmu;
- pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
+ pmu = perf_i915_open(i915,
+ I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
ci[idx].engine_instance));
spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
@@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
pmu[0] = -1;
for (int i = 0; i < limit; i++)
- pmu[i] = add_pmu(pmu[0], &siblings[i]);
- pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
+ pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
+ pmu[limit] = add_pmu(i915,
+ pmu[0], &master_engines[bond]);
igt_assert(siblings[bond].engine_class !=
master_engines[bond].engine_class);
@@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
for (unsigned int n = 0; n < count; n++) {
uint32_t ctx;
- pmu[n] = add_pmu(pmu[0], &ci[n]);
+ pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
if (flags & PULSE) {
struct drm_i915_gem_execbuffer2 eb = {
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index e1bbf2410..3e179daef 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
const double tolerance = 0.05f;
const unsigned long batch_duration_ns = 500e6;
-static int open_pmu(uint64_t config)
+static int open_pmu(int i915, uint64_t config)
{
int fd;
- fd = perf_i915_open(config);
+ fd = perf_i915_open(i915, config);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
return fd;
}
-static int open_group(uint64_t config, int group)
+static int open_group(int i915, uint64_t config, int group)
{
int fd;
- fd = perf_i915_open_group(config, group);
+ fd = perf_i915_open_group(i915, config, group);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
@@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
bool exists;
errno = 0;
- fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
+ fd = perf_i915_open(gem_fd,
+ __I915_PMU_ENGINE(e->class, e->instance, sample));
if (fd < 0)
err = errno;
@@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val;
int fd;
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
spin = __spin_sync(gem_fd, 0, e);
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
* Open PMU as fast as possible after the second spin batch in attempt
* to be faster than the driver handling lite-restore.
*/
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
if (e->class == e_->class && e->instance == e_->instance)
busy_idx = i;
- fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
+ fd[i++] = open_group(gem_fd,
+ I915_PMU_ENGINE_BUSY(e_->class,
e_->instance),
fd[0]);
}
@@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val[2][2];
int fd;
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
* to expected time spent in semaphore wait state.
*/
- fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -817,8 +820,9 @@ sema_busy(int gem_fd,
igt_require(gem_scheduler_has_semaphores(gem_fd));
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
__for_each_physical_engine(gem_fd, signal) {
if (e->class == signal->class &&
@@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
data.pipe = p;
prepare_crtc(&data, gem_fd, output);
- fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_WAIT(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
gem_quiescent_gpu(gem_fd);
- fd[0] = open_pmu(config);
+ fd[0] = open_pmu(gem_fd, config);
/*
* Second PMU client which is initialized after the first one,
* and exists before it, should not affect accounting as reported
* in the first client.
*/
- fd[1] = open_pmu(config);
+ fd[1] = open_pmu(gem_fd, config);
spin = spin_sync(gem_fd, 0, e);
@@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
* - cpu != 0 is not supported since i915 PMU only allows running on one cpu
* and that is normally CPU0.
*/
-static void invalid_init(void)
+static void invalid_init(int i915)
{
struct perf_event_attr attr;
@@ -1093,7 +1098,7 @@ static void invalid_init(void)
do { \
memset(&attr, 0, sizeof (attr)); \
attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
- attr.type = i915_type_id(); \
+ attr.type = i915_perf_type_id(i915); \
igt_assert(attr.type != 0); \
errno = 0; \
} while(0)
@@ -1112,11 +1117,11 @@ do { \
igt_assert_eq(errno, EINVAL);
}
-static void init_other(unsigned int i, bool valid)
+static void init_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
close(fd);
}
-static void read_other(unsigned int i, bool valid)
+static void read_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
igt_require(cpu0_hotplug_support());
- fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
/*
* Create two spinners so test can ensure shorter gaps in engine
@@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++) {
@@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++)
@@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
igt_require(max_freq > min_freq);
igt_require(boost_freq > min_freq);
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
/*
* Set GPU to min frequency and read PMU counters.
@@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
/* While parked, our convention is to report the GPU at 0Hz */
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
gem_quiescent_gpu(gem_fd); /* Be idle! */
measured_usleep(2000); /* Wait for timers to cease */
@@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_RC6_RESIDENCY);
+ fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
if (flags & TEST_RUNTIME_PM) {
drmModeRes *res;
@@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
usleep(500e3);
/* Enable the PMU. */
- fd = open_pmu(config);
+ fd = open_pmu(gem_fd, config);
/* Stop load and close the PMU. */
igt_stop_helper(&engine_load);
@@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
igt_spin_free(gem_fd, spin);
}
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
/* Let the child run. */
read(link[0], &expected, sizeof(expected));
@@ -1835,7 +1841,7 @@ igt_main
fd = drm_open_driver_master(DRIVER_INTEL);
igt_require_gem(fd);
- igt_require(i915_type_id() > 0);
+ igt_require(i915_perf_type_id(fd) > 0);
__for_each_physical_engine(fd, e)
num_engines++;
@@ -1845,7 +1851,7 @@ igt_main
* Test invalid access via perf API is rejected.
*/
igt_subtest("invalid-init")
- invalid_init();
+ invalid_init(fd);
__for_each_physical_engine(fd, e) {
const unsigned int pct[] = { 2, 50, 98 };
@@ -1996,10 +2002,10 @@ igt_main
*/
for (i = 0; i < num_other_metrics + 1; i++) {
igt_subtest_f("other-init-%u", i)
- init_other(i, i < num_other_metrics);
+ init_other(fd, i, i < num_other_metrics);
igt_subtest_f("other-read-%u", i)
- read_other(i, i < num_other_metrics);
+ read_other(fd, i, i < num_other_metrics);
}
/**
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index cc8db7c53..8197482dd 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
({ \
int fd__; \
\
- fd__ = perf_i915_open_group((pmu)->config, (fd)); \
+ fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
if (fd__ >= 0) { \
if ((fd) == -1) \
(fd) = fd__; \
--
2.25.0.rc0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/perf: Find the associated perf-type for a particular device (rev2)
2020-01-04 15:37 ` [igt-dev] " Chris Wilson
(?)
@ 2020-01-04 17:00 ` Patchwork
-1 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2020-01-04 17:00 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: i915/perf: Find the associated perf-type for a particular device (rev2)
URL : https://patchwork.freedesktop.org/series/71609/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7677 -> IGTPW_3899
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/index.html
Known issues
------------
Here are the changes found in IGTPW_3899 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-skl-6770hq: [PASS][1] -> [INCOMPLETE][2] ([i915#671])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/fi-skl-6770hq/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/fi-skl-6770hq/igt@i915_module_load@reload-with-fault-injection.html
- fi-kbl-7500u: [PASS][3] -> [INCOMPLETE][4] ([i915#879])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/fi-kbl-7500u/igt@i915_module_load@reload-with-fault-injection.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/fi-kbl-7500u/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][5] -> [SKIP][6] ([fdo#109271])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_blt:
- fi-byt-j1900: [PASS][7] -> [DMESG-FAIL][8] ([i915#725])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/fi-byt-j1900/igt@i915_selftest@live_blt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/fi-byt-j1900/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-j1900: [PASS][9] -> [DMESG-FAIL][10] ([i915#722])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
#### Possible fixes ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111407]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Warnings ####
* igt@i915_selftest@live_blt:
- fi-hsw-4770: [DMESG-FAIL][13] ([i915#725]) -> [DMESG-FAIL][14] ([i915#553] / [i915#725])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/fi-hsw-4770/igt@i915_selftest@live_blt.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/fi-hsw-4770/igt@i915_selftest@live_blt.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671
[i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#879]: https://gitlab.freedesktop.org/drm/intel/issues/879
Participating hosts (49 -> 43)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-n2820 fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5357 -> IGTPW_3899
CI-20190529: 20190529
CI_DRM_7677: 7cbe8b273afa6b8112b3a3a6f477f981f7864dde @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3899: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/index.html
IGT_5357: a555a4b98f90dab655d24bb3d07e9291a8b8dac8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for i915/perf: Find the associated perf-type for a particular device (rev2)
2020-01-04 15:37 ` [igt-dev] " Chris Wilson
(?)
(?)
@ 2020-01-04 20:46 ` Patchwork
-1 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2020-01-04 20:46 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: i915/perf: Find the associated perf-type for a particular device (rev2)
URL : https://patchwork.freedesktop.org/series/71609/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7677_full -> IGTPW_3899_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_3899_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_3899_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_3899_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_balancer@bonded-cork:
- shard-tglb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-tglb1/igt@gem_exec_balancer@bonded-cork.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb3/igt@gem_exec_balancer@bonded-cork.html
* igt@gem_exec_balancer@full-late-pulse:
- shard-glk: [PASS][3] -> [FAIL][4] +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-glk7/igt@gem_exec_balancer@full-late-pulse.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-glk7/igt@gem_exec_balancer@full-late-pulse.html
* igt@gem_exec_balancer@full-pulse:
- shard-kbl: [PASS][5] -> [FAIL][6] +5 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl4/igt@gem_exec_balancer@full-pulse.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl4/igt@gem_exec_balancer@full-pulse.html
* igt@gem_exec_balancer@individual:
- shard-apl: [PASS][7] -> [FAIL][8] +5 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl6/igt@gem_exec_balancer@individual.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl1/igt@gem_exec_balancer@individual.html
- shard-iclb: [PASS][9] -> [FAIL][10] +5 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb7/igt@gem_exec_balancer@individual.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb5/igt@gem_exec_balancer@individual.html
* igt@gem_exec_balancer@semaphore:
- shard-tglb: NOTRUN -> [FAIL][11] +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb2/igt@gem_exec_balancer@semaphore.html
* igt@perf_pmu@busy-accuracy-2-bcs0:
- shard-iclb: [PASS][12] -> [TIMEOUT][13] +49 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb5/igt@perf_pmu@busy-accuracy-2-bcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb3/igt@perf_pmu@busy-accuracy-2-bcs0.html
* igt@perf_pmu@busy-start-vecs0:
- shard-iclb: [PASS][14] -> [SKIP][15] +8 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb4/igt@perf_pmu@busy-start-vecs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb7/igt@perf_pmu@busy-start-vecs0.html
* igt@perf_pmu@idle-no-semaphores-bcs0:
- shard-snb: NOTRUN -> [TIMEOUT][16]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb2/igt@perf_pmu@idle-no-semaphores-bcs0.html
* igt@perf_pmu@init-wait-vcs0:
- shard-glk: [PASS][17] -> [TIMEOUT][18] +36 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-glk6/igt@perf_pmu@init-wait-vcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-glk1/igt@perf_pmu@init-wait-vcs0.html
* igt@perf_pmu@interrupts:
- shard-iclb: NOTRUN -> [SKIP][19]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb6/igt@perf_pmu@interrupts.html
* igt@perf_pmu@most-busy-idle-check-all-bcs0:
- shard-hsw: [PASS][20] -> [TIMEOUT][21] +7 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-hsw5/igt@perf_pmu@most-busy-idle-check-all-bcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-hsw2/igt@perf_pmu@most-busy-idle-check-all-bcs0.html
* igt@perf_pmu@multi-client-bcs0:
- shard-snb: [PASS][22] -> [TIMEOUT][23] +31 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-snb2/igt@perf_pmu@multi-client-bcs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb6/igt@perf_pmu@multi-client-bcs0.html
* igt@perf_pmu@other-init-2:
- shard-hsw: NOTRUN -> [TIMEOUT][24] +9 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-hsw7/igt@perf_pmu@other-init-2.html
* igt@perf_pmu@rc6:
- shard-apl: [PASS][25] -> [TIMEOUT][26] +41 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl8/igt@perf_pmu@rc6.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl4/igt@perf_pmu@rc6.html
* igt@perf_pmu@render-node-busy-vcs1:
- shard-kbl: [PASS][27] -> [TIMEOUT][28] +56 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl2/igt@perf_pmu@render-node-busy-vcs1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl2/igt@perf_pmu@render-node-busy-vcs1.html
* igt@perf_pmu@semaphore-wait-idle-vcs2:
- shard-iclb: NOTRUN -> [TIMEOUT][29]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb6/igt@perf_pmu@semaphore-wait-idle-vcs2.html
* igt@perf_pmu@semaphore-wait-idle-vecs0:
- shard-tglb: [PASS][30] -> [SKIP][31] +3 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-tglb6/igt@perf_pmu@semaphore-wait-idle-vecs0.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb1/igt@perf_pmu@semaphore-wait-idle-vecs0.html
#### Warnings ####
* igt@perf_pmu@busy-accuracy-2-rcs0:
- shard-snb: [SKIP][32] ([fdo#109271]) -> [TIMEOUT][33] +15 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-snb2/igt@perf_pmu@busy-accuracy-2-rcs0.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb4/igt@perf_pmu@busy-accuracy-2-rcs0.html
* igt@perf_pmu@busy-accuracy-98-rcs0:
- shard-hsw: [SKIP][34] ([fdo#109271]) -> [TIMEOUT][35] +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-hsw1/igt@perf_pmu@busy-accuracy-98-rcs0.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-hsw7/igt@perf_pmu@busy-accuracy-98-rcs0.html
* igt@perf_pmu@busy-no-semaphores-vcs2:
- shard-iclb: [SKIP][36] ([fdo#112080]) -> [TIMEOUT][37] +11 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs2.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb5/igt@perf_pmu@busy-no-semaphores-vcs2.html
* igt@perf_pmu@busy-vcs1:
- shard-glk: [SKIP][38] ([fdo#109271] / [fdo#112080]) -> [TIMEOUT][39] +16 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-glk7/igt@perf_pmu@busy-vcs1.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-glk2/igt@perf_pmu@busy-vcs1.html
* igt@perf_pmu@init-sema-vcs2:
- shard-apl: [SKIP][40] ([fdo#109271] / [fdo#112080]) -> [TIMEOUT][41] +18 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl2/igt@perf_pmu@init-sema-vcs2.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl2/igt@perf_pmu@init-sema-vcs2.html
* igt@perf_pmu@render-node-busy-vcs2:
- shard-hsw: [SKIP][42] ([fdo#109271] / [fdo#112080]) -> [TIMEOUT][43] +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-hsw5/igt@perf_pmu@render-node-busy-vcs2.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-hsw7/igt@perf_pmu@render-node-busy-vcs2.html
* igt@perf_pmu@semaphore-wait-idle-vcs2:
- shard-kbl: [SKIP][44] ([fdo#109271] / [fdo#112080]) -> [TIMEOUT][45] +8 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl4/igt@perf_pmu@semaphore-wait-idle-vcs2.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl2/igt@perf_pmu@semaphore-wait-idle-vcs2.html
- shard-snb: [SKIP][46] ([fdo#109271] / [fdo#112080]) -> [TIMEOUT][47] +19 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-snb7/igt@perf_pmu@semaphore-wait-idle-vcs2.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb4/igt@perf_pmu@semaphore-wait-idle-vcs2.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_balancer@bonded-semaphore}:
- shard-apl: [PASS][48] -> [FAIL][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl6/igt@gem_exec_balancer@bonded-semaphore.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl6/igt@gem_exec_balancer@bonded-semaphore.html
Known issues
------------
Here are the changes found in IGTPW_3899_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][50] -> [SKIP][51] ([fdo#109276] / [fdo#112080]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb3/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_ctx_shared@q-smoketest-vebox:
- shard-tglb: [PASS][52] -> [INCOMPLETE][53] ([fdo#111735])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-tglb8/igt@gem_ctx_shared@q-smoketest-vebox.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb3/igt@gem_ctx_shared@q-smoketest-vebox.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [PASS][54] -> [SKIP][55] ([fdo#109276]) +9 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb2/igt@gem_exec_schedule@fifo-bsd1.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb8/igt@gem_exec_schedule@fifo-bsd1.html
* igt@gem_exec_schedule@preempt-queue-bsd:
- shard-iclb: [PASS][56] -> [SKIP][57] ([fdo#112146]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1:
- shard-tglb: [PASS][58] -> [INCOMPLETE][59] ([fdo#111677])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-tglb7/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb5/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-snb: [PASS][60] -> [DMESG-WARN][61] ([fdo#111870])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_wait@await-vcs1:
- shard-iclb: [PASS][62] -> [SKIP][63] ([fdo#112080]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb1/igt@gem_wait@await-vcs1.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb3/igt@gem_wait@await-vcs1.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][64] -> [DMESG-WARN][65] ([i915#180])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbc-tilingchange:
- shard-tglb: [PASS][66] -> [FAIL][67] ([i915#49]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [PASS][68] -> [DMESG-WARN][69] ([i915#180]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@perf_pmu@busy-accuracy-2-vcs1:
- shard-kbl: [PASS][70] -> [TIMEOUT][71] ([fdo#112271]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl3/igt@perf_pmu@busy-accuracy-2-vcs1.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl6/igt@perf_pmu@busy-accuracy-2-vcs1.html
* igt@perf_pmu@busy-accuracy-50-vcs0:
- shard-iclb: [PASS][72] -> [TIMEOUT][73] ([fdo#112271]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb6/igt@perf_pmu@busy-accuracy-50-vcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb1/igt@perf_pmu@busy-accuracy-50-vcs0.html
- shard-glk: [PASS][74] -> [TIMEOUT][75] ([fdo#112271])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-glk4/igt@perf_pmu@busy-accuracy-50-vcs0.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-glk2/igt@perf_pmu@busy-accuracy-50-vcs0.html
- shard-apl: [PASS][76] -> [TIMEOUT][77] ([fdo#112271]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl4/igt@perf_pmu@busy-accuracy-50-vcs0.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl8/igt@perf_pmu@busy-accuracy-50-vcs0.html
- shard-tglb: [PASS][78] -> [TIMEOUT][79] ([fdo#112271] / [i915#923]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-tglb2/igt@perf_pmu@busy-accuracy-50-vcs0.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb1/igt@perf_pmu@busy-accuracy-50-vcs0.html
* igt@perf_pmu@busy-hang-vecs0:
- shard-apl: [PASS][80] -> [SKIP][81] ([fdo#109271]) +12 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl4/igt@perf_pmu@busy-hang-vecs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl4/igt@perf_pmu@busy-hang-vecs0.html
* igt@perf_pmu@busy-idle-check-all-vcs0:
- shard-glk: [PASS][82] -> [SKIP][83] ([fdo#109271]) +6 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-glk2/igt@perf_pmu@busy-idle-check-all-vcs0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-glk8/igt@perf_pmu@busy-idle-check-all-vcs0.html
* igt@perf_pmu@cpu-hotplug:
- shard-apl: [PASS][84] -> [TIMEOUT][85] ([fdo#111546])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl1/igt@perf_pmu@cpu-hotplug.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl1/igt@perf_pmu@cpu-hotplug.html
- shard-kbl: [PASS][86] -> [TIMEOUT][87] ([fdo#111546])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl1/igt@perf_pmu@cpu-hotplug.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl7/igt@perf_pmu@cpu-hotplug.html
- shard-snb: [PASS][88] -> [TIMEOUT][89] ([fdo#111546])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-snb7/igt@perf_pmu@cpu-hotplug.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb5/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@init-busy-vcs1:
- shard-kbl: [PASS][90] -> [SKIP][91] ([fdo#109271] / [fdo#112080])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl7/igt@perf_pmu@init-busy-vcs1.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl2/igt@perf_pmu@init-busy-vcs1.html
* igt@perf_pmu@interrupts:
- shard-snb: [PASS][92] -> [SKIP][93] ([fdo#109271])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-snb7/igt@perf_pmu@interrupts.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb4/igt@perf_pmu@interrupts.html
- shard-kbl: [PASS][94] -> [SKIP][95] ([fdo#109271]) +4 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl4/igt@perf_pmu@interrupts.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl2/igt@perf_pmu@interrupts.html
* igt@perf_pmu@multi-client-vecs0:
- shard-hsw: [PASS][96] -> [SKIP][97] ([fdo#109271])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-hsw5/igt@perf_pmu@multi-client-vecs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-hsw5/igt@perf_pmu@multi-client-vecs0.html
* igt@perf_pmu@other-init-0:
- shard-tglb: [PASS][98] -> [TIMEOUT][99] ([i915#923]) +29 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-tglb6/igt@perf_pmu@other-init-0.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb6/igt@perf_pmu@other-init-0.html
* igt@perf_pmu@render-node-busy-bcs0:
- shard-apl: [PASS][100] -> [INCOMPLETE][101] ([fdo#103927])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl6/igt@perf_pmu@render-node-busy-bcs0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl6/igt@perf_pmu@render-node-busy-bcs0.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-s3:
- shard-iclb: [SKIP][102] ([fdo#109276] / [fdo#112080]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb5/igt@gem_ctx_isolation@vcs1-s3.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb4/igt@gem_ctx_isolation@vcs1-s3.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [SKIP][104] ([fdo#112146]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb1/igt@gem_exec_async@concurrent-writes-bsd.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb6/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_parallel@vcs1:
- shard-iclb: [SKIP][106] ([fdo#112080]) -> [PASS][107] +2 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb7/igt@gem_exec_parallel@vcs1.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb1/igt@gem_exec_parallel@vcs1.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][108] ([i915#180]) -> [PASS][109] +2 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_rpm@modeset-stress-extra-wait:
- shard-glk: [DMESG-WARN][110] ([i915#118] / [i915#95]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-glk8/igt@i915_pm_rpm@modeset-stress-extra-wait.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-glk9/igt@i915_pm_rpm@modeset-stress-extra-wait.html
* igt@i915_suspend@forcewake:
- shard-apl: [DMESG-WARN][112] ([i915#180]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl1/igt@i915_suspend@forcewake.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl1/igt@i915_suspend@forcewake.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
- shard-apl: [FAIL][114] ([i915#54]) -> [PASS][115] +2 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
- shard-kbl: [FAIL][116] ([i915#54]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-glk: [FAIL][118] ([i915#54]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-glk4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-glk4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][120] ([fdo#109441]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb4/igt@kms_psr@psr2_basic.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][122] ([fdo#109276]) -> [PASS][123] +9 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-tglb: [INCOMPLETE][124] ([i915#470] / [i915#475]) -> [INCOMPLETE][125] ([i915#470])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-tglb1/igt@gem_ppgtt@blt-vs-render-ctxn.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb9/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [DMESG-WARN][126] ([fdo#111870]) -> [DMESG-WARN][127] ([fdo#110789] / [fdo#111870]) +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-snb7/igt@gem_userptr_blits@sync-unmap-cycles.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing:
- shard-tglb: [SKIP][128] ([fdo#112016] / [fdo#112021]) -> [SKIP][129] ([fdo#112021])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-tglb6/igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb9/igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [FAIL][130] ([i915#54]) -> [DMESG-WARN][131] ([i915#180])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][132] ([fdo#107724]) -> [SKIP][133] ([fdo#109349])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@perf_pmu@busy-accuracy-2-vcs1:
- shard-glk: [SKIP][134] ([fdo#109271] / [fdo#112080]) -> [TIMEOUT][135] ([fdo#112271])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-glk4/igt@perf_pmu@busy-accuracy-2-vcs1.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-glk9/igt@perf_pmu@busy-accuracy-2-vcs1.html
- shard-iclb: [SKIP][136] ([fdo#112080]) -> [TIMEOUT][137] ([fdo#112271])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb6/igt@perf_pmu@busy-accuracy-2-vcs1.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb4/igt@perf_pmu@busy-accuracy-2-vcs1.html
- shard-apl: [SKIP][138] ([fdo#109271] / [fdo#112080]) -> [TIMEOUT][139] ([fdo#112271])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl4/igt@perf_pmu@busy-accuracy-2-vcs1.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl6/igt@perf_pmu@busy-accuracy-2-vcs1.html
- shard-hsw: [SKIP][140] ([fdo#109271] / [fdo#112080]) -> [TIMEOUT][141] ([fdo#112271])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-hsw7/igt@perf_pmu@busy-accuracy-2-vcs1.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-hsw2/igt@perf_pmu@busy-accuracy-2-vcs1.html
- shard-snb: [SKIP][142] ([fdo#109271] / [fdo#112080]) -> [TIMEOUT][143] ([fdo#112271])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-snb2/igt@perf_pmu@busy-accuracy-2-vcs1.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb4/igt@perf_pmu@busy-accuracy-2-vcs1.html
* igt@perf_pmu@busy-accuracy-50-vcs0:
- shard-snb: [SKIP][144] ([fdo#109271]) -> [TIMEOUT][145] ([fdo#112271]) +1 similar issue
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-snb2/igt@perf_pmu@busy-accuracy-50-vcs0.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb7/igt@perf_pmu@busy-accuracy-50-vcs0.html
* igt@perf_pmu@busy-accuracy-50-vcs2:
- shard-tglb: [SKIP][146] ([fdo#112080]) -> [TIMEOUT][147] ([i915#923]) +2 similar issues
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-tglb2/igt@perf_pmu@busy-accuracy-50-vcs2.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb6/igt@perf_pmu@busy-accuracy-50-vcs2.html
* igt@perf_pmu@busy-accuracy-98-vcs1:
- shard-apl: [SKIP][148] ([fdo#109271] / [fdo#112080]) -> [INCOMPLETE][149] ([fdo#103927]) +3 similar issues
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-apl1/igt@perf_pmu@busy-accuracy-98-vcs1.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-apl3/igt@perf_pmu@busy-accuracy-98-vcs1.html
* igt@perf_pmu@busy-idle-check-all-vcs1:
- shard-iclb: [SKIP][150] ([fdo#112080]) -> [SKIP][151] ([fdo#109276] / [fdo#112080])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb7/igt@perf_pmu@busy-idle-check-all-vcs1.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb2/igt@perf_pmu@busy-idle-check-all-vcs1.html
* igt@perf_pmu@init-busy-vcs1:
- shard-iclb: [SKIP][152] ([fdo#112080]) -> [INCOMPLETE][153] ([i915#140]) +4 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-iclb7/igt@perf_pmu@init-busy-vcs1.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-iclb6/igt@perf_pmu@init-busy-vcs1.html
* igt@perf_pmu@init-busy-vcs2:
- shard-glk: [SKIP][154] ([fdo#109271] / [fdo#112080]) -> [INCOMPLETE][155] ([i915#58] / [k.org#198133])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-glk3/igt@perf_pmu@init-busy-vcs2.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-glk1/igt@perf_pmu@init-busy-vcs2.html
- shard-snb: [SKIP][156] ([fdo#109271] / [fdo#112080]) -> [INCOMPLETE][157] ([i915#82]) +4 similar issues
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-snb6/igt@perf_pmu@init-busy-vcs2.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb7/igt@perf_pmu@init-busy-vcs2.html
* igt@perf_pmu@most-busy-check-all-vcs2:
- shard-kbl: [SKIP][158] ([fdo#109271] / [fdo#112080]) -> [INCOMPLETE][159] ([fdo#103665]) +2 similar issues
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-kbl6/igt@perf_pmu@most-busy-check-all-vcs2.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-kbl3/igt@perf_pmu@most-busy-check-all-vcs2.html
* igt@perf_pmu@multi-client-vcs2:
- shard-tglb: [SKIP][160] ([fdo#112080]) -> [INCOMPLETE][161] ([i915#923])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-tglb1/igt@perf_pmu@multi-client-vcs2.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-tglb9/igt@perf_pmu@multi-client-vcs2.html
* igt@perf_pmu@semaphore-wait-idle-vecs0:
- shard-snb: [SKIP][162] ([fdo#109271]) -> [INCOMPLETE][163] ([i915#82]) +2 similar issues
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7677/shard-snb6/igt@perf_pmu@semaphore-wait-idle-vecs0.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/shard-snb5/igt@perf_pmu@semaphore-wait-idle-vecs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3899/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
2020-01-04 15:37 ` [igt-dev] " Chris Wilson
@ 2020-01-05 1:06 ` Chris Wilson
-1 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-05 1:06 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Since with multiple devices, we may have multiple different perf_pmu
each with their own type, we want to find the right one for the job.
The tests are run with a specific fd, from which we can extract the
appropriate bus-id and find the associated perf-type. The performance
monitoring tools are a little more general and not yet ready to probe
all device or bind to one in particular, so we just assume the default
igfx for the time being.
v2: Extract the bus address from out of sysfs
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
benchmarks/gem_wsim.c | 4 +-
lib/igt_perf.c | 84 +++++++++++++++++++++++++++++++---
lib/igt_perf.h | 13 ++++--
overlay/gem-interrupts.c | 2 +-
overlay/gpu-freq.c | 4 +-
overlay/gpu-top.c | 12 ++---
overlay/rc6.c | 2 +-
tests/i915/gem_ctx_freq.c | 2 +-
tests/i915/gem_ctx_sseu.c | 2 +-
tests/i915/gem_exec_balancer.c | 18 +++++---
tests/perf_pmu.c | 84 ++++++++++++++++++----------------
tools/intel_gpu_top.c | 2 +-
12 files changed, 159 insertions(+), 70 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 6305e0d7a..9156fdc90 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
for (d = &engines[0]; d->id != VCS; d++) {
int pfd;
- pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
- d->inst),
+ pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ d->inst),
bb->fd);
if (pfd < 0) {
if (d->id != VCS2)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index e3dec2cc2..840add043 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -4,17 +4,77 @@
#include <stdlib.h>
#include <string.h>
#include <errno.h>
+#include <sys/stat.h>
#include <sys/sysinfo.h>
+#include <sys/sysmacros.h>
#include "igt_perf.h"
-uint64_t i915_type_id(void)
+static char *bus_address(int i915, char *path, int pathlen)
+{
+ struct stat st;
+ int len = -1;
+ int dir;
+ char *s;
+
+ if (fstat(i915, &st) || !S_ISCHR(st.st_mode))
+ return NULL;
+
+ snprintf(path, pathlen, "/sys/dev/char/%d:%d",
+ major(st.st_rdev), minor(st.st_rdev));
+
+ dir = open(path, O_RDONLY);
+ if (dir != -1) {
+ len = readlinkat(dir, "device", path, pathlen - 1);
+ close(dir);
+ }
+ if (len < 0)
+ return NULL;
+
+ path[len] = '\0';
+
+ /* strip off the relative path */
+ s = strrchr(path, '/');
+ if (s)
+ memmove(path, s + 1, len - (s - path) + 1);
+
+ return path;
+}
+
+const char *i915_perf_device(int i915, char *buf, int buflen)
+{
+#define prefix "i915-"
+#define plen strlen(prefix)
+
+ if (!buf || buflen < plen)
+ return "i915";
+
+ memcpy(buf, prefix, plen);
+
+ if (!bus_address(i915, buf + plen, buflen - plen) ||
+ strcmp(buf + plen, "0000:00:02.0") == 0) /* legacy name for igfx */
+ buf[plen - 1] = '\0';
+
+ return buf;
+}
+
+uint64_t i915_perf_type_id(int i915)
+{
+ char buf[80];
+
+ return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
+}
+
+uint64_t igt_perf_type_id(const char *device)
{
char buf[64];
ssize_t ret;
int fd;
- fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
+ snprintf(buf, sizeof(buf),
+ "/sys/bus/event_source/devices/%s/type", device);
+
+ fd = open(buf, O_RDONLY);
if (fd < 0)
return 0;
@@ -52,15 +112,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
return ret;
}
-int perf_i915_open(uint64_t config)
+int perf_igfx_open(uint64_t config)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
+
+int perf_igfx_open_group(uint64_t config, int group)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, group,
+ PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
+}
+
+int perf_i915_open(int i915, uint64_t config)
{
- return _perf_open(i915_type_id(), config, -1,
+ return _perf_open(i915_perf_type_id(i915), config, -1,
PERF_FORMAT_TOTAL_TIME_ENABLED);
}
-int perf_i915_open_group(uint64_t config, int group)
+int perf_i915_open_group(int i915, uint64_t config, int group)
{
- return _perf_open(i915_type_id(), config, group,
+ return _perf_open(i915_perf_type_id(i915), config, group,
PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index e00718f47..a8328c70c 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
}
-uint64_t i915_type_id(void);
-int perf_i915_open(uint64_t config);
-int perf_i915_open_group(uint64_t config, int group);
+uint64_t igt_perf_type_id(const char *device);
int igt_perf_open(uint64_t type, uint64_t config);
int igt_perf_open_group(uint64_t type, uint64_t config, int group);
+const char *i915_perf_device(int i915, char *buf, int buflen);
+uint64_t i915_perf_type_id(int i915);
+
+int perf_igfx_open(uint64_t config);
+int perf_igfx_open_group(uint64_t config, int group);
+
+int perf_i915_open(int i915, uint64_t config);
+int perf_i915_open_group(int i915, uint64_t config, int group);
+
#endif /* I915_PERF_H */
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index 0233fbb05..be73b6931 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
{
memset(irqs, 0, sizeof(*irqs));
- irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
+ irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
if (irqs->fd < 0 && interrupts_read() < 0)
irqs->error = ENODEV;
diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
index 0d8032592..b73157d39 100644
--- a/overlay/gpu-freq.c
+++ b/overlay/gpu-freq.c
@@ -37,8 +37,8 @@ static int perf_open(void)
{
int fd;
- fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
- if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
+ fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
+ if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
close(fd);
fd = -1;
}
diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 6cec2e943..32123abdd 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
d = &engines[0];
- gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
+ gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
-1);
if (gt->fd < 0)
return -1;
- if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
gt->fd) >= 0)
gt->have_wait = 1;
- if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
gt->fd) >= 0)
gt->have_sema = 1;
@@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
gt->num_rings = 1;
for (d++; d->name; d++) {
- if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
d->inst),
gt->fd) < 0)
continue;
if (gt->have_wait &&
- perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
d->inst),
gt->fd) < 0)
return -1;
if (gt->have_sema &&
- perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
d->inst),
gt->fd) < 0)
return -1;
diff --git a/overlay/rc6.c b/overlay/rc6.c
index b5286f0cf..69f95f288 100644
--- a/overlay/rc6.c
+++ b/overlay/rc6.c
@@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
{
memset(rc6, 0, sizeof(*rc6));
- rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
+ rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
if (rc6->fd < 0) {
struct stat st;
if (stat("/sys/class/drm/card0/power", &st) < 0)
diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
index 89f3d11ef..5d2d3ec31 100644
--- a/tests/i915/gem_ctx_freq.c
+++ b/tests/i915/gem_ctx_freq.c
@@ -136,7 +136,7 @@ static void sysfs_range(int i915)
triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
- pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+ pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
igt_require(pmu >= 0);
for (int outer = 0; outer <= 2*N_STEPS; outer++) {
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
index 48e4411c8..38dc584bc 100644
--- a/tests/i915/gem_ctx_sseu.c
+++ b/tests/i915/gem_ctx_sseu.c
@@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
static bool has_engine(int fd, unsigned int class, unsigned int instance)
{
- int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
if (pmu >= 0)
close(pmu);
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index f4909a978..cebcc39c7 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
{
int fd;
- fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
if (fd != -1) {
close(fd);
return true;
@@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
}
}
-static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
+static int
+add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
{
- return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
+ return perf_i915_open_group(i915,
+ I915_PMU_ENGINE_BUSY(ci->engine_class,
ci->engine_instance),
pmu);
}
@@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
double load;
int pmu;
- pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
+ pmu = perf_i915_open(i915,
+ I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
ci[idx].engine_instance));
spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
@@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
pmu[0] = -1;
for (int i = 0; i < limit; i++)
- pmu[i] = add_pmu(pmu[0], &siblings[i]);
- pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
+ pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
+ pmu[limit] = add_pmu(i915,
+ pmu[0], &master_engines[bond]);
igt_assert(siblings[bond].engine_class !=
master_engines[bond].engine_class);
@@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
for (unsigned int n = 0; n < count; n++) {
uint32_t ctx;
- pmu[n] = add_pmu(pmu[0], &ci[n]);
+ pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
if (flags & PULSE) {
struct drm_i915_gem_execbuffer2 eb = {
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index e1bbf2410..3e179daef 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
const double tolerance = 0.05f;
const unsigned long batch_duration_ns = 500e6;
-static int open_pmu(uint64_t config)
+static int open_pmu(int i915, uint64_t config)
{
int fd;
- fd = perf_i915_open(config);
+ fd = perf_i915_open(i915, config);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
return fd;
}
-static int open_group(uint64_t config, int group)
+static int open_group(int i915, uint64_t config, int group)
{
int fd;
- fd = perf_i915_open_group(config, group);
+ fd = perf_i915_open_group(i915, config, group);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
@@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
bool exists;
errno = 0;
- fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
+ fd = perf_i915_open(gem_fd,
+ __I915_PMU_ENGINE(e->class, e->instance, sample));
if (fd < 0)
err = errno;
@@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val;
int fd;
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
spin = __spin_sync(gem_fd, 0, e);
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
* Open PMU as fast as possible after the second spin batch in attempt
* to be faster than the driver handling lite-restore.
*/
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
if (e->class == e_->class && e->instance == e_->instance)
busy_idx = i;
- fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
+ fd[i++] = open_group(gem_fd,
+ I915_PMU_ENGINE_BUSY(e_->class,
e_->instance),
fd[0]);
}
@@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val[2][2];
int fd;
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
* to expected time spent in semaphore wait state.
*/
- fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -817,8 +820,9 @@ sema_busy(int gem_fd,
igt_require(gem_scheduler_has_semaphores(gem_fd));
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
__for_each_physical_engine(gem_fd, signal) {
if (e->class == signal->class &&
@@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
data.pipe = p;
prepare_crtc(&data, gem_fd, output);
- fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_WAIT(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
gem_quiescent_gpu(gem_fd);
- fd[0] = open_pmu(config);
+ fd[0] = open_pmu(gem_fd, config);
/*
* Second PMU client which is initialized after the first one,
* and exists before it, should not affect accounting as reported
* in the first client.
*/
- fd[1] = open_pmu(config);
+ fd[1] = open_pmu(gem_fd, config);
spin = spin_sync(gem_fd, 0, e);
@@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
* - cpu != 0 is not supported since i915 PMU only allows running on one cpu
* and that is normally CPU0.
*/
-static void invalid_init(void)
+static void invalid_init(int i915)
{
struct perf_event_attr attr;
@@ -1093,7 +1098,7 @@ static void invalid_init(void)
do { \
memset(&attr, 0, sizeof (attr)); \
attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
- attr.type = i915_type_id(); \
+ attr.type = i915_perf_type_id(i915); \
igt_assert(attr.type != 0); \
errno = 0; \
} while(0)
@@ -1112,11 +1117,11 @@ do { \
igt_assert_eq(errno, EINVAL);
}
-static void init_other(unsigned int i, bool valid)
+static void init_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
close(fd);
}
-static void read_other(unsigned int i, bool valid)
+static void read_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
igt_require(cpu0_hotplug_support());
- fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
/*
* Create two spinners so test can ensure shorter gaps in engine
@@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++) {
@@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++)
@@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
igt_require(max_freq > min_freq);
igt_require(boost_freq > min_freq);
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
/*
* Set GPU to min frequency and read PMU counters.
@@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
/* While parked, our convention is to report the GPU at 0Hz */
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
gem_quiescent_gpu(gem_fd); /* Be idle! */
measured_usleep(2000); /* Wait for timers to cease */
@@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_RC6_RESIDENCY);
+ fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
if (flags & TEST_RUNTIME_PM) {
drmModeRes *res;
@@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
usleep(500e3);
/* Enable the PMU. */
- fd = open_pmu(config);
+ fd = open_pmu(gem_fd, config);
/* Stop load and close the PMU. */
igt_stop_helper(&engine_load);
@@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
igt_spin_free(gem_fd, spin);
}
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
/* Let the child run. */
read(link[0], &expected, sizeof(expected));
@@ -1835,7 +1841,7 @@ igt_main
fd = drm_open_driver_master(DRIVER_INTEL);
igt_require_gem(fd);
- igt_require(i915_type_id() > 0);
+ igt_require(i915_perf_type_id(fd) > 0);
__for_each_physical_engine(fd, e)
num_engines++;
@@ -1845,7 +1851,7 @@ igt_main
* Test invalid access via perf API is rejected.
*/
igt_subtest("invalid-init")
- invalid_init();
+ invalid_init(fd);
__for_each_physical_engine(fd, e) {
const unsigned int pct[] = { 2, 50, 98 };
@@ -1996,10 +2002,10 @@ igt_main
*/
for (i = 0; i < num_other_metrics + 1; i++) {
igt_subtest_f("other-init-%u", i)
- init_other(i, i < num_other_metrics);
+ init_other(fd, i, i < num_other_metrics);
igt_subtest_f("other-read-%u", i)
- read_other(i, i < num_other_metrics);
+ read_other(fd, i, i < num_other_metrics);
}
/**
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index cc8db7c53..8197482dd 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
({ \
int fd__; \
\
- fd__ = perf_i915_open_group((pmu)->config, (fd)); \
+ fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
if (fd__ >= 0) { \
if ((fd) == -1) \
(fd) = fd__; \
--
2.25.0.rc0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
@ 2020-01-05 1:06 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-05 1:06 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
Since with multiple devices, we may have multiple different perf_pmu
each with their own type, we want to find the right one for the job.
The tests are run with a specific fd, from which we can extract the
appropriate bus-id and find the associated perf-type. The performance
monitoring tools are a little more general and not yet ready to probe
all device or bind to one in particular, so we just assume the default
igfx for the time being.
v2: Extract the bus address from out of sysfs
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
benchmarks/gem_wsim.c | 4 +-
lib/igt_perf.c | 84 +++++++++++++++++++++++++++++++---
lib/igt_perf.h | 13 ++++--
overlay/gem-interrupts.c | 2 +-
overlay/gpu-freq.c | 4 +-
overlay/gpu-top.c | 12 ++---
overlay/rc6.c | 2 +-
tests/i915/gem_ctx_freq.c | 2 +-
tests/i915/gem_ctx_sseu.c | 2 +-
tests/i915/gem_exec_balancer.c | 18 +++++---
tests/perf_pmu.c | 84 ++++++++++++++++++----------------
tools/intel_gpu_top.c | 2 +-
12 files changed, 159 insertions(+), 70 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 6305e0d7a..9156fdc90 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
for (d = &engines[0]; d->id != VCS; d++) {
int pfd;
- pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
- d->inst),
+ pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ d->inst),
bb->fd);
if (pfd < 0) {
if (d->id != VCS2)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index e3dec2cc2..840add043 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -4,17 +4,77 @@
#include <stdlib.h>
#include <string.h>
#include <errno.h>
+#include <sys/stat.h>
#include <sys/sysinfo.h>
+#include <sys/sysmacros.h>
#include "igt_perf.h"
-uint64_t i915_type_id(void)
+static char *bus_address(int i915, char *path, int pathlen)
+{
+ struct stat st;
+ int len = -1;
+ int dir;
+ char *s;
+
+ if (fstat(i915, &st) || !S_ISCHR(st.st_mode))
+ return NULL;
+
+ snprintf(path, pathlen, "/sys/dev/char/%d:%d",
+ major(st.st_rdev), minor(st.st_rdev));
+
+ dir = open(path, O_RDONLY);
+ if (dir != -1) {
+ len = readlinkat(dir, "device", path, pathlen - 1);
+ close(dir);
+ }
+ if (len < 0)
+ return NULL;
+
+ path[len] = '\0';
+
+ /* strip off the relative path */
+ s = strrchr(path, '/');
+ if (s)
+ memmove(path, s + 1, len - (s - path) + 1);
+
+ return path;
+}
+
+const char *i915_perf_device(int i915, char *buf, int buflen)
+{
+#define prefix "i915-"
+#define plen strlen(prefix)
+
+ if (!buf || buflen < plen)
+ return "i915";
+
+ memcpy(buf, prefix, plen);
+
+ if (!bus_address(i915, buf + plen, buflen - plen) ||
+ strcmp(buf + plen, "0000:00:02.0") == 0) /* legacy name for igfx */
+ buf[plen - 1] = '\0';
+
+ return buf;
+}
+
+uint64_t i915_perf_type_id(int i915)
+{
+ char buf[80];
+
+ return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
+}
+
+uint64_t igt_perf_type_id(const char *device)
{
char buf[64];
ssize_t ret;
int fd;
- fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
+ snprintf(buf, sizeof(buf),
+ "/sys/bus/event_source/devices/%s/type", device);
+
+ fd = open(buf, O_RDONLY);
if (fd < 0)
return 0;
@@ -52,15 +112,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
return ret;
}
-int perf_i915_open(uint64_t config)
+int perf_igfx_open(uint64_t config)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
+
+int perf_igfx_open_group(uint64_t config, int group)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, group,
+ PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
+}
+
+int perf_i915_open(int i915, uint64_t config)
{
- return _perf_open(i915_type_id(), config, -1,
+ return _perf_open(i915_perf_type_id(i915), config, -1,
PERF_FORMAT_TOTAL_TIME_ENABLED);
}
-int perf_i915_open_group(uint64_t config, int group)
+int perf_i915_open_group(int i915, uint64_t config, int group)
{
- return _perf_open(i915_type_id(), config, group,
+ return _perf_open(i915_perf_type_id(i915), config, group,
PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index e00718f47..a8328c70c 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
}
-uint64_t i915_type_id(void);
-int perf_i915_open(uint64_t config);
-int perf_i915_open_group(uint64_t config, int group);
+uint64_t igt_perf_type_id(const char *device);
int igt_perf_open(uint64_t type, uint64_t config);
int igt_perf_open_group(uint64_t type, uint64_t config, int group);
+const char *i915_perf_device(int i915, char *buf, int buflen);
+uint64_t i915_perf_type_id(int i915);
+
+int perf_igfx_open(uint64_t config);
+int perf_igfx_open_group(uint64_t config, int group);
+
+int perf_i915_open(int i915, uint64_t config);
+int perf_i915_open_group(int i915, uint64_t config, int group);
+
#endif /* I915_PERF_H */
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index 0233fbb05..be73b6931 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
{
memset(irqs, 0, sizeof(*irqs));
- irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
+ irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
if (irqs->fd < 0 && interrupts_read() < 0)
irqs->error = ENODEV;
diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
index 0d8032592..b73157d39 100644
--- a/overlay/gpu-freq.c
+++ b/overlay/gpu-freq.c
@@ -37,8 +37,8 @@ static int perf_open(void)
{
int fd;
- fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
- if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
+ fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
+ if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
close(fd);
fd = -1;
}
diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 6cec2e943..32123abdd 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
d = &engines[0];
- gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
+ gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
-1);
if (gt->fd < 0)
return -1;
- if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
gt->fd) >= 0)
gt->have_wait = 1;
- if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
gt->fd) >= 0)
gt->have_sema = 1;
@@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
gt->num_rings = 1;
for (d++; d->name; d++) {
- if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
d->inst),
gt->fd) < 0)
continue;
if (gt->have_wait &&
- perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
d->inst),
gt->fd) < 0)
return -1;
if (gt->have_sema &&
- perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
d->inst),
gt->fd) < 0)
return -1;
diff --git a/overlay/rc6.c b/overlay/rc6.c
index b5286f0cf..69f95f288 100644
--- a/overlay/rc6.c
+++ b/overlay/rc6.c
@@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
{
memset(rc6, 0, sizeof(*rc6));
- rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
+ rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
if (rc6->fd < 0) {
struct stat st;
if (stat("/sys/class/drm/card0/power", &st) < 0)
diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
index 89f3d11ef..5d2d3ec31 100644
--- a/tests/i915/gem_ctx_freq.c
+++ b/tests/i915/gem_ctx_freq.c
@@ -136,7 +136,7 @@ static void sysfs_range(int i915)
triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
- pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+ pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
igt_require(pmu >= 0);
for (int outer = 0; outer <= 2*N_STEPS; outer++) {
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
index 48e4411c8..38dc584bc 100644
--- a/tests/i915/gem_ctx_sseu.c
+++ b/tests/i915/gem_ctx_sseu.c
@@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
static bool has_engine(int fd, unsigned int class, unsigned int instance)
{
- int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
if (pmu >= 0)
close(pmu);
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index f4909a978..cebcc39c7 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
{
int fd;
- fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
if (fd != -1) {
close(fd);
return true;
@@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
}
}
-static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
+static int
+add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
{
- return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
+ return perf_i915_open_group(i915,
+ I915_PMU_ENGINE_BUSY(ci->engine_class,
ci->engine_instance),
pmu);
}
@@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
double load;
int pmu;
- pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
+ pmu = perf_i915_open(i915,
+ I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
ci[idx].engine_instance));
spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
@@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
pmu[0] = -1;
for (int i = 0; i < limit; i++)
- pmu[i] = add_pmu(pmu[0], &siblings[i]);
- pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
+ pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
+ pmu[limit] = add_pmu(i915,
+ pmu[0], &master_engines[bond]);
igt_assert(siblings[bond].engine_class !=
master_engines[bond].engine_class);
@@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
for (unsigned int n = 0; n < count; n++) {
uint32_t ctx;
- pmu[n] = add_pmu(pmu[0], &ci[n]);
+ pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
if (flags & PULSE) {
struct drm_i915_gem_execbuffer2 eb = {
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index e1bbf2410..3e179daef 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
const double tolerance = 0.05f;
const unsigned long batch_duration_ns = 500e6;
-static int open_pmu(uint64_t config)
+static int open_pmu(int i915, uint64_t config)
{
int fd;
- fd = perf_i915_open(config);
+ fd = perf_i915_open(i915, config);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
return fd;
}
-static int open_group(uint64_t config, int group)
+static int open_group(int i915, uint64_t config, int group)
{
int fd;
- fd = perf_i915_open_group(config, group);
+ fd = perf_i915_open_group(i915, config, group);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
@@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
bool exists;
errno = 0;
- fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
+ fd = perf_i915_open(gem_fd,
+ __I915_PMU_ENGINE(e->class, e->instance, sample));
if (fd < 0)
err = errno;
@@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val;
int fd;
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
spin = __spin_sync(gem_fd, 0, e);
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
* Open PMU as fast as possible after the second spin batch in attempt
* to be faster than the driver handling lite-restore.
*/
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
if (e->class == e_->class && e->instance == e_->instance)
busy_idx = i;
- fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
+ fd[i++] = open_group(gem_fd,
+ I915_PMU_ENGINE_BUSY(e_->class,
e_->instance),
fd[0]);
}
@@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val[2][2];
int fd;
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
* to expected time spent in semaphore wait state.
*/
- fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -817,8 +820,9 @@ sema_busy(int gem_fd,
igt_require(gem_scheduler_has_semaphores(gem_fd));
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
__for_each_physical_engine(gem_fd, signal) {
if (e->class == signal->class &&
@@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
data.pipe = p;
prepare_crtc(&data, gem_fd, output);
- fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_WAIT(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
gem_quiescent_gpu(gem_fd);
- fd[0] = open_pmu(config);
+ fd[0] = open_pmu(gem_fd, config);
/*
* Second PMU client which is initialized after the first one,
* and exists before it, should not affect accounting as reported
* in the first client.
*/
- fd[1] = open_pmu(config);
+ fd[1] = open_pmu(gem_fd, config);
spin = spin_sync(gem_fd, 0, e);
@@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
* - cpu != 0 is not supported since i915 PMU only allows running on one cpu
* and that is normally CPU0.
*/
-static void invalid_init(void)
+static void invalid_init(int i915)
{
struct perf_event_attr attr;
@@ -1093,7 +1098,7 @@ static void invalid_init(void)
do { \
memset(&attr, 0, sizeof (attr)); \
attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
- attr.type = i915_type_id(); \
+ attr.type = i915_perf_type_id(i915); \
igt_assert(attr.type != 0); \
errno = 0; \
} while(0)
@@ -1112,11 +1117,11 @@ do { \
igt_assert_eq(errno, EINVAL);
}
-static void init_other(unsigned int i, bool valid)
+static void init_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
close(fd);
}
-static void read_other(unsigned int i, bool valid)
+static void read_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
igt_require(cpu0_hotplug_support());
- fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
/*
* Create two spinners so test can ensure shorter gaps in engine
@@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++) {
@@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++)
@@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
igt_require(max_freq > min_freq);
igt_require(boost_freq > min_freq);
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
/*
* Set GPU to min frequency and read PMU counters.
@@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
/* While parked, our convention is to report the GPU at 0Hz */
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
gem_quiescent_gpu(gem_fd); /* Be idle! */
measured_usleep(2000); /* Wait for timers to cease */
@@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_RC6_RESIDENCY);
+ fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
if (flags & TEST_RUNTIME_PM) {
drmModeRes *res;
@@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
usleep(500e3);
/* Enable the PMU. */
- fd = open_pmu(config);
+ fd = open_pmu(gem_fd, config);
/* Stop load and close the PMU. */
igt_stop_helper(&engine_load);
@@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
igt_spin_free(gem_fd, spin);
}
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
/* Let the child run. */
read(link[0], &expected, sizeof(expected));
@@ -1835,7 +1841,7 @@ igt_main
fd = drm_open_driver_master(DRIVER_INTEL);
igt_require_gem(fd);
- igt_require(i915_type_id() > 0);
+ igt_require(i915_perf_type_id(fd) > 0);
__for_each_physical_engine(fd, e)
num_engines++;
@@ -1845,7 +1851,7 @@ igt_main
* Test invalid access via perf API is rejected.
*/
igt_subtest("invalid-init")
- invalid_init();
+ invalid_init(fd);
__for_each_physical_engine(fd, e) {
const unsigned int pct[] = { 2, 50, 98 };
@@ -1996,10 +2002,10 @@ igt_main
*/
for (i = 0; i < num_other_metrics + 1; i++) {
igt_subtest_f("other-init-%u", i)
- init_other(i, i < num_other_metrics);
+ init_other(fd, i, i < num_other_metrics);
igt_subtest_f("other-read-%u", i)
- read_other(i, i < num_other_metrics);
+ read_other(fd, i, i < num_other_metrics);
}
/**
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index cc8db7c53..8197482dd 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
({ \
int fd__; \
\
- fd__ = perf_i915_open_group((pmu)->config, (fd)); \
+ fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
if (fd__ >= 0) { \
if ((fd) == -1) \
(fd) = fd__; \
--
2.25.0.rc0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/perf: Find the associated perf-type for a particular device (rev3)
2020-01-04 15:37 ` [igt-dev] " Chris Wilson
` (3 preceding siblings ...)
(?)
@ 2020-01-05 1:40 ` Patchwork
-1 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2020-01-05 1:40 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: i915/perf: Find the associated perf-type for a particular device (rev3)
URL : https://patchwork.freedesktop.org/series/71609/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7678 -> IGTPW_3900
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/index.html
Known issues
------------
Here are the changes found in IGTPW_3900 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [PASS][1] -> [DMESG-WARN][2] ([i915#889]) +23 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_execlists:
- fi-kbl-guc: [PASS][3] -> [INCOMPLETE][4] ([fdo#112175] / [fdo#112259])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/fi-kbl-guc/igt@i915_selftest@live_execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/fi-kbl-guc/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gt_lrc:
- fi-skl-6600u: [PASS][5] -> [DMESG-FAIL][6] ([i915#889]) +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#109635])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#263])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
#### Possible fixes ####
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [TIMEOUT][11] ([i915#816]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/fi-byt-j1900/igt@gem_close_race@basic-threads.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/fi-byt-j1900/igt@gem_close_race@basic-threads.html
* igt@i915_module_load@reload:
- fi-icl-u2: [DMESG-WARN][13] ([i915#289]) -> [PASS][14] +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/fi-icl-u2/igt@i915_module_load@reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/fi-icl-u2/igt@i915_module_load@reload.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-cfl-8700k: [DMESG-WARN][15] ([i915#889]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/fi-cfl-8700k/igt@i915_module_load@reload-with-fault-injection.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/fi-cfl-8700k/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [DMESG-FAIL][17] ([i915#419]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
#### Warnings ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][19] ([IGT#4] / [i915#263]) -> [FAIL][20] ([i915#323])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
[fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#112175]: https://bugs.freedesktop.org/show_bug.cgi?id=112175
[fdo#112259]: https://bugs.freedesktop.org/show_bug.cgi?id=112259
[i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#419]: https://gitlab.freedesktop.org/drm/intel/issues/419
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
[i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889
Participating hosts (51 -> 37)
------------------------------
Missing (14): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-skl-lmem fi-byt-clapper fi-bdw-samus fi-snb-2600
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5357 -> IGTPW_3900
CI-20190529: 20190529
CI_DRM_7678: e554efffc6ca410bae6c5b3f310dea22f597487c @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3900: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/index.html
IGT_5357: a555a4b98f90dab655d24bb3d07e9291a8b8dac8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for i915/perf: Find the associated perf-type for a particular device (rev3)
2020-01-04 15:37 ` [igt-dev] " Chris Wilson
` (4 preceding siblings ...)
(?)
@ 2020-01-05 3:04 ` Patchwork
-1 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2020-01-05 3:04 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: i915/perf: Find the associated perf-type for a particular device (rev3)
URL : https://patchwork.freedesktop.org/series/71609/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7678_full -> IGTPW_3900_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_3900_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_3900_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_3900_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_linear_blits@interruptible:
- shard-glk: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-glk1/igt@gem_linear_blits@interruptible.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-glk4/igt@gem_linear_blits@interruptible.html
* igt@runner@aborted:
- shard-snb: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-snb6/igt@runner@aborted.html
Known issues
------------
Here are the changes found in IGTPW_3900_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#109276] / [fdo#112080]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb8/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_ctx_persistence@bcs0-mixed-process:
- shard-iclb: [PASS][6] -> [FAIL][7] ([i915#679])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb5/igt@gem_ctx_persistence@bcs0-mixed-process.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb1/igt@gem_ctx_persistence@bcs0-mixed-process.html
* igt@gem_ctx_shared@q-smoketest-blt:
- shard-tglb: [PASS][8] -> [INCOMPLETE][9] ([fdo#111735])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb7/igt@gem_ctx_shared@q-smoketest-blt.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb6/igt@gem_ctx_shared@q-smoketest-blt.html
* igt@gem_eio@kms:
- shard-tglb: [PASS][10] -> [INCOMPLETE][11] ([i915#476])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb9/igt@gem_eio@kms.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb8/igt@gem_eio@kms.html
* igt@gem_exec_balancer@nop:
- shard-tglb: [PASS][12] -> [INCOMPLETE][13] ([fdo#111736])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb6/igt@gem_exec_balancer@nop.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb1/igt@gem_exec_balancer@nop.html
* igt@gem_exec_nop@basic-series:
- shard-tglb: [PASS][14] -> [INCOMPLETE][15] ([i915#435]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb7/igt@gem_exec_nop@basic-series.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb9/igt@gem_exec_nop@basic-series.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#112146]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb6/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_schedule@smoketest-bsd2:
- shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#707]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb7/igt@gem_exec_schedule@smoketest-bsd2.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb6/igt@gem_exec_schedule@smoketest-bsd2.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-tglb: [PASS][20] -> [TIMEOUT][21] ([fdo#112126] / [i915#530])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb5/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_sync@basic-many-each:
- shard-tglb: [PASS][22] -> [INCOMPLETE][23] ([i915#472] / [i915#707])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb1/igt@gem_sync@basic-many-each.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb6/igt@gem_sync@basic-many-each.html
* igt@gem_sync@basic-store-all:
- shard-tglb: [PASS][24] -> [INCOMPLETE][25] ([i915#472])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb2/igt@gem_sync@basic-store-all.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb3/igt@gem_sync@basic-store-all.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [PASS][26] -> [DMESG-WARN][27] ([fdo#111870]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@i915_pm_rps@reset:
- shard-iclb: [PASS][28] -> [FAIL][29] ([i915#413])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb1/igt@i915_pm_rps@reset.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb7/igt@i915_pm_rps@reset.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [PASS][30] -> [INCOMPLETE][31] ([fdo#103665])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-kbl4/igt@i915_suspend@debugfs-reader.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-kbl2/igt@i915_suspend@debugfs-reader.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][32] -> [DMESG-WARN][33] ([i915#180]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-iclb: [PASS][34] -> [DMESG-WARN][35] ([fdo#111764])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb2/igt@kms_fbcon_fbt@fbc-suspend.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [PASS][36] -> [DMESG-WARN][37] ([i915#391])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [PASS][38] -> [DMESG-WARN][39] ([i915#180])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][40] -> [SKIP][41] ([fdo#109441]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb4/igt@kms_psr@psr2_no_drrs.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-snb: [PASS][42] -> [DMESG-WARN][43] ([i915#473])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-snb5/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-snb6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@perf_pmu@busy-accuracy-98-vecs0:
- shard-tglb: [PASS][44] -> [INCOMPLETE][45] ([i915#435] / [i915#923])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb2/igt@perf_pmu@busy-accuracy-98-vecs0.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb2/igt@perf_pmu@busy-accuracy-98-vecs0.html
* igt@perf_pmu@init-busy-vcs1:
- shard-iclb: [PASS][46] -> [SKIP][47] ([fdo#112080]) +10 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb2/igt@perf_pmu@init-busy-vcs1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb6/igt@perf_pmu@init-busy-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][48] -> [SKIP][49] ([fdo#109276]) +13 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-iclb: [DMESG-WARN][50] ([fdo#111764]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb7/igt@gem_ctx_isolation@rcs0-s3.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb6/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_isolation@vcs1-clean:
- shard-iclb: [SKIP][52] ([fdo#109276] / [fdo#112080]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb7/igt@gem_ctx_isolation@vcs1-clean.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb1/igt@gem_ctx_isolation@vcs1-clean.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][54] ([fdo#110841]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][56] ([fdo#110854]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb8/igt@gem_exec_balancer@smoke.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb1/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_basic@basic-vcs1:
- shard-iclb: [SKIP][58] ([fdo#112080]) -> [PASS][59] +7 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb5/igt@gem_exec_basic@basic-vcs1.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb2/igt@gem_exec_basic@basic-vcs1.html
* igt@gem_exec_parallel@fds:
- shard-tglb: [INCOMPLETE][60] ([i915#470]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb3/igt@gem_exec_parallel@fds.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb5/igt@gem_exec_parallel@fds.html
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-iclb: [SKIP][62] ([fdo#112146]) -> [PASS][63] +3 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb2/igt@gem_exec_schedule@pi-ringfull-bsd.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb5/igt@gem_exec_schedule@pi-ringfull-bsd.html
* igt@gem_ringfill@basic-default:
- shard-tglb: [INCOMPLETE][64] -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb5/igt@gem_ringfill@basic-default.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb5/igt@gem_ringfill@basic-default.html
* {igt@gen9_exec_parse@allowed-all}:
- shard-glk: [DMESG-WARN][66] ([i915#716]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-glk7/igt@gen9_exec_parse@allowed-all.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-glk2/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][68] ([i915#454]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: [DMESG-WARN][70] ([i915#180]) -> [PASS][71] +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-apl6/igt@i915_suspend@fence-restore-untiled.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-apl2/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
- shard-apl: [FAIL][72] ([i915#54]) -> [PASS][73] +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-apl8/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [FAIL][74] ([i915#54]) -> [PASS][75] +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
- shard-glk: [FAIL][76] ([i915#54]) -> [PASS][77] +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-glk2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-glk4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][78] ([i915#79]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [INCOMPLETE][80] ([fdo#103665] / [i915#600]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-kbl6/igt@kms_flip@flip-vs-suspend.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-kbl4/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- shard-tglb: [FAIL][82] ([i915#49]) -> [PASS][83] +3 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [DMESG-WARN][84] ([i915#180]) -> [PASS][85] +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][86] ([fdo#109441]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][88] ([fdo#109276]) -> [PASS][89] +16 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb7/igt@prime_busy@hang-bsd2.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb4/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][90] ([fdo#109276] / [fdo#112080]) -> [FAIL][91] ([IGT#28])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb7/igt@gem_ctx_isolation@vcs1-nonpriv.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_eio@kms:
- shard-snb: [INCOMPLETE][92] ([i915#82]) -> [DMESG-WARN][93] ([i915#444])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-snb7/igt@gem_eio@kms.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-snb6/igt@gem_eio@kms.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [DMESG-WARN][94] ([fdo#111870]) -> [DMESG-WARN][95] ([fdo#110789] / [fdo#111870])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-snb6/igt@gem_userptr_blits@sync-unmap-cycles.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-snb2/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [SKIP][96] ([i915#468]) -> [FAIL][97] ([i915#454])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb3/igt@i915_pm_dc@dc6-dpms.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb7/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing:
- shard-tglb: [SKIP][98] ([fdo#112021]) -> [SKIP][99] ([fdo#112016] / [fdo#112021])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-tglb9/igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-tglb1/igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][100] ([fdo#107724]) -> [SKIP][101] ([fdo#109349])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-iclb1/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: [INCOMPLETE][102] ([fdo#103665]) -> [DMESG-WARN][103] ([i915#180])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7678/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112016]: https://bugs.freedesktop.org/show_bug.cgi?id=112016
[fdo#112021]: https://bugs.freedesktop.org/show_bug.cgi?id=112021
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112126]: https://bugs.freedesktop.org/show_bug.cgi?id=112126
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#391]: https://gitlab.freedesktop.org/drm/intel/issues/391
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
[i915#444]: https://gitlab.freedesktop.org/drm/intel/issues/444
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#473]: https://gitlab.freedesktop.org/drm/intel/issues/473
[i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#600]: https://gitlab.freedesktop.org/drm/intel/issues/600
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
[i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#923]: https://gitlab.freedesktop.org/drm/intel/issues/923
Participating hosts (11 -> 8)
------------------------------
Missing (3): pig-skl-6260u pig-glk-j5005 pig-hsw-4770r
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5357 -> IGTPW_3900
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_7678: e554efffc6ca410bae6c5b3f310dea22f597487c @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3900: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/index.html
IGT_5357: a555a4b98f90dab655d24bb3d07e9291a8b8dac8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3900/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
2020-01-05 1:06 ` [igt-dev] " Chris Wilson
@ 2020-01-07 9:53 ` Tvrtko Ursulin
-1 siblings, 0 replies; 16+ messages in thread
From: Tvrtko Ursulin @ 2020-01-07 9:53 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, saurabhg.gupta
+Arek, Saurabhg
On 05/01/2020 01:06, Chris Wilson wrote:
> Since with multiple devices, we may have multiple different perf_pmu
> each with their own type, we want to find the right one for the job.
>
> The tests are run with a specific fd, from which we can extract the
> appropriate bus-id and find the associated perf-type. The performance
> monitoring tools are a little more general and not yet ready to probe
> all device or bind to one in particular, so we just assume the default
> igfx for the time being.
>
> v2: Extract the bus address from out of sysfs
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
> benchmarks/gem_wsim.c | 4 +-
> lib/igt_perf.c | 84 +++++++++++++++++++++++++++++++---
> lib/igt_perf.h | 13 ++++--
> overlay/gem-interrupts.c | 2 +-
> overlay/gpu-freq.c | 4 +-
> overlay/gpu-top.c | 12 ++---
> overlay/rc6.c | 2 +-
> tests/i915/gem_ctx_freq.c | 2 +-
> tests/i915/gem_ctx_sseu.c | 2 +-
> tests/i915/gem_exec_balancer.c | 18 +++++---
> tests/perf_pmu.c | 84 ++++++++++++++++++----------------
> tools/intel_gpu_top.c | 2 +-
> 12 files changed, 159 insertions(+), 70 deletions(-)
>
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index 6305e0d7a..9156fdc90 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
> for (d = &engines[0]; d->id != VCS; d++) {
> int pfd;
>
> - pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> - d->inst),
> + pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> + d->inst),
> bb->fd);
> if (pfd < 0) {
> if (d->id != VCS2)
> diff --git a/lib/igt_perf.c b/lib/igt_perf.c
> index e3dec2cc2..840add043 100644
> --- a/lib/igt_perf.c
> +++ b/lib/igt_perf.c
> @@ -4,17 +4,77 @@
> #include <stdlib.h>
> #include <string.h>
> #include <errno.h>
> +#include <sys/stat.h>
> #include <sys/sysinfo.h>
> +#include <sys/sysmacros.h>
>
> #include "igt_perf.h"
>
> -uint64_t i915_type_id(void)
> +static char *bus_address(int i915, char *path, int pathlen)
> +{
> + struct stat st;
> + int len = -1;
> + int dir;
> + char *s;
> +
> + if (fstat(i915, &st) || !S_ISCHR(st.st_mode))
> + return NULL;
> +
> + snprintf(path, pathlen, "/sys/dev/char/%d:%d",
> + major(st.st_rdev), minor(st.st_rdev));
> +
> + dir = open(path, O_RDONLY);
> + if (dir != -1) {
> + len = readlinkat(dir, "device", path, pathlen - 1);
> + close(dir);
> + }
> + if (len < 0)
> + return NULL;
> +
> + path[len] = '\0';
> +
> + /* strip off the relative path */
> + s = strrchr(path, '/');
> + if (s)
> + memmove(path, s + 1, len - (s - path) + 1);
> +
> + return path;
> +}
> +
> +const char *i915_perf_device(int i915, char *buf, int buflen)
> +{
> +#define prefix "i915-"
> +#define plen strlen(prefix)
> +
> + if (!buf || buflen < plen)
> + return "i915";
> +
> + memcpy(buf, prefix, plen);
> +
> + if (!bus_address(i915, buf + plen, buflen - plen) ||
> + strcmp(buf + plen, "0000:00:02.0") == 0) /* legacy name for igfx */
> + buf[plen - 1] = '\0';
> +
> + return buf;
> +}
So DRM fd -> PCI string conversion, yes? On a glance it looks okay.
However Arek probably has this data as part of "[PATCH i-g-t 0/4] device
selection && lsgpu" (https://patchwork.freedesktop.org/series/70285/).
Also:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/52
https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/51
And VLK-5588.
This patch is overlap with #52 and then #51/VLK-5588 is about allowing
card selection for tools.
How to meld the two with minimum effort? We could put this in and then
later replace the PCI name resolve with a library routine and re-adjust
tools to allow card selection via some mechanism.
Regards,
Tvrtko
> +
> +uint64_t i915_perf_type_id(int i915)
> +{
> + char buf[80];
> +
> + return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
> +}
> +
> +uint64_t igt_perf_type_id(const char *device)
> {
> char buf[64];
> ssize_t ret;
> int fd;
>
> - fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
> + snprintf(buf, sizeof(buf),
> + "/sys/bus/event_source/devices/%s/type", device);
> +
> + fd = open(buf, O_RDONLY);
> if (fd < 0)
> return 0;
>
> @@ -52,15 +112,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
> return ret;
> }
>
> -int perf_i915_open(uint64_t config)
> +int perf_igfx_open(uint64_t config)
> +{
> + return _perf_open(igt_perf_type_id("i915"), config, -1,
> + PERF_FORMAT_TOTAL_TIME_ENABLED);
> +}
> +
> +int perf_igfx_open_group(uint64_t config, int group)
> +{
> + return _perf_open(igt_perf_type_id("i915"), config, group,
> + PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
> +}
> +
> +int perf_i915_open(int i915, uint64_t config)
> {
> - return _perf_open(i915_type_id(), config, -1,
> + return _perf_open(i915_perf_type_id(i915), config, -1,
> PERF_FORMAT_TOTAL_TIME_ENABLED);
> }
>
> -int perf_i915_open_group(uint64_t config, int group)
> +int perf_i915_open_group(int i915, uint64_t config, int group)
> {
> - return _perf_open(i915_type_id(), config, group,
> + return _perf_open(i915_perf_type_id(i915), config, group,
> PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
> }
>
> diff --git a/lib/igt_perf.h b/lib/igt_perf.h
> index e00718f47..a8328c70c 100644
> --- a/lib/igt_perf.h
> +++ b/lib/igt_perf.h
> @@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
> return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
> }
>
> -uint64_t i915_type_id(void);
> -int perf_i915_open(uint64_t config);
> -int perf_i915_open_group(uint64_t config, int group);
> +uint64_t igt_perf_type_id(const char *device);
> int igt_perf_open(uint64_t type, uint64_t config);
> int igt_perf_open_group(uint64_t type, uint64_t config, int group);
>
> +const char *i915_perf_device(int i915, char *buf, int buflen);
> +uint64_t i915_perf_type_id(int i915);
> +
> +int perf_igfx_open(uint64_t config);
> +int perf_igfx_open_group(uint64_t config, int group);
> +
> +int perf_i915_open(int i915, uint64_t config);
> +int perf_i915_open_group(int i915, uint64_t config, int group);
> +
> #endif /* I915_PERF_H */
> diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
> index 0233fbb05..be73b6931 100644
> --- a/overlay/gem-interrupts.c
> +++ b/overlay/gem-interrupts.c
> @@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
> {
> memset(irqs, 0, sizeof(*irqs));
>
> - irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
> + irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
> if (irqs->fd < 0 && interrupts_read() < 0)
> irqs->error = ENODEV;
>
> diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
> index 0d8032592..b73157d39 100644
> --- a/overlay/gpu-freq.c
> +++ b/overlay/gpu-freq.c
> @@ -37,8 +37,8 @@ static int perf_open(void)
> {
> int fd;
>
> - fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
> - if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
> + fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
> + if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
> close(fd);
> fd = -1;
> }
> diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
> index 6cec2e943..32123abdd 100644
> --- a/overlay/gpu-top.c
> +++ b/overlay/gpu-top.c
> @@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
>
> d = &engines[0];
>
> - gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
> + gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
> -1);
> if (gt->fd < 0)
> return -1;
>
> - if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
> + if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
> gt->fd) >= 0)
> gt->have_wait = 1;
>
> - if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
> + if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
> gt->fd) >= 0)
> gt->have_sema = 1;
>
> @@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
> gt->num_rings = 1;
>
> for (d++; d->name; d++) {
> - if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> + if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> d->inst),
> gt->fd) < 0)
> continue;
>
> if (gt->have_wait &&
> - perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
> + perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
> d->inst),
> gt->fd) < 0)
> return -1;
>
> if (gt->have_sema &&
> - perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
> + perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
> d->inst),
> gt->fd) < 0)
> return -1;
> diff --git a/overlay/rc6.c b/overlay/rc6.c
> index b5286f0cf..69f95f288 100644
> --- a/overlay/rc6.c
> +++ b/overlay/rc6.c
> @@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
> {
> memset(rc6, 0, sizeof(*rc6));
>
> - rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
> + rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
> if (rc6->fd < 0) {
> struct stat st;
> if (stat("/sys/class/drm/card0/power", &st) < 0)
> diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
> index 89f3d11ef..5d2d3ec31 100644
> --- a/tests/i915/gem_ctx_freq.c
> +++ b/tests/i915/gem_ctx_freq.c
> @@ -136,7 +136,7 @@ static void sysfs_range(int i915)
>
> triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
>
> - pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
> + pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
> igt_require(pmu >= 0);
>
> for (int outer = 0; outer <= 2*N_STEPS; outer++) {
> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
> index 48e4411c8..38dc584bc 100644
> --- a/tests/i915/gem_ctx_sseu.c
> +++ b/tests/i915/gem_ctx_sseu.c
> @@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
>
> static bool has_engine(int fd, unsigned int class, unsigned int instance)
> {
> - int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
> + int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
>
> if (pmu >= 0)
> close(pmu);
> diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
> index f4909a978..cebcc39c7 100644
> --- a/tests/i915/gem_exec_balancer.c
> +++ b/tests/i915/gem_exec_balancer.c
> @@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
> {
> int fd;
>
> - fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
> + fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
> if (fd != -1) {
> close(fd);
> return true;
> @@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
> }
> }
>
> -static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
> +static int
> +add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
> {
> - return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
> + return perf_i915_open_group(i915,
> + I915_PMU_ENGINE_BUSY(ci->engine_class,
> ci->engine_instance),
> pmu);
> }
> @@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
> double load;
> int pmu;
>
> - pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
> + pmu = perf_i915_open(i915,
> + I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
> ci[idx].engine_instance));
>
> spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
> @@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
>
> pmu[0] = -1;
> for (int i = 0; i < limit; i++)
> - pmu[i] = add_pmu(pmu[0], &siblings[i]);
> - pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
> + pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
> + pmu[limit] = add_pmu(i915,
> + pmu[0], &master_engines[bond]);
>
> igt_assert(siblings[bond].engine_class !=
> master_engines[bond].engine_class);
> @@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
> for (unsigned int n = 0; n < count; n++) {
> uint32_t ctx;
>
> - pmu[n] = add_pmu(pmu[0], &ci[n]);
> + pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
>
> if (flags & PULSE) {
> struct drm_i915_gem_execbuffer2 eb = {
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index e1bbf2410..3e179daef 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
> const double tolerance = 0.05f;
> const unsigned long batch_duration_ns = 500e6;
>
> -static int open_pmu(uint64_t config)
> +static int open_pmu(int i915, uint64_t config)
> {
> int fd;
>
> - fd = perf_i915_open(config);
> + fd = perf_i915_open(i915, config);
> igt_skip_on(fd < 0 && errno == ENODEV);
> igt_assert(fd >= 0);
>
> return fd;
> }
>
> -static int open_group(uint64_t config, int group)
> +static int open_group(int i915, uint64_t config, int group)
> {
> int fd;
>
> - fd = perf_i915_open_group(config, group);
> + fd = perf_i915_open_group(i915, config, group);
> igt_skip_on(fd < 0 && errno == ENODEV);
> igt_assert(fd >= 0);
>
> @@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
> bool exists;
>
> errno = 0;
> - fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
> + fd = perf_i915_open(gem_fd,
> + __I915_PMU_ENGINE(e->class, e->instance, sample));
> if (fd < 0)
> err = errno;
>
> @@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
> uint64_t val;
> int fd;
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> if (flags & TEST_BUSY)
> spin = spin_sync(gem_fd, 0, e);
> @@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
>
> spin = __spin_sync(gem_fd, 0, e);
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> val = __pmu_read_single(fd, &ts[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
> * Open PMU as fast as possible after the second spin batch in attempt
> * to be faster than the driver handling lite-restore.
> */
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> val = __pmu_read_single(fd, &ts[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> if (e->class == e_->class && e->instance == e_->instance)
> busy_idx = i;
>
> - fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
> + fd[i++] = open_group(gem_fd,
> + I915_PMU_ENGINE_BUSY(e_->class,
> e_->instance),
> fd[0]);
> }
> @@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>
> fd[0] = -1;
> for (i = 0; i < num_engines; i++)
> - fd[i] = open_group(val[i], fd[0]);
> + fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> @@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>
> fd[0] = -1;
> for (i = 0; i < num_engines; i++)
> - fd[i] = open_group(val[i], fd[0]);
> + fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> @@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
> uint64_t val[2][2];
> int fd;
>
> - fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> - open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
> + fd = open_group(gem_fd,
> + I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> + open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
>
> if (flags & TEST_BUSY)
> spin = spin_sync(gem_fd, 0, e);
> @@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
> * to expected time spent in semaphore wait state.
> */
>
> - fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
>
> val[0] = pmu_read_single(fd);
>
> @@ -817,8 +820,9 @@ sema_busy(int gem_fd,
>
> igt_require(gem_scheduler_has_semaphores(gem_fd));
>
> - fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> - open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
> + fd = open_group(gem_fd,
> + I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> + open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
>
> __for_each_physical_engine(gem_fd, signal) {
> if (e->class == signal->class &&
> @@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
> data.pipe = p;
> prepare_crtc(&data, gem_fd, output);
>
> - fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
> + fd = open_pmu(gem_fd,
> + I915_PMU_ENGINE_WAIT(e->class, e->instance));
>
> val[0] = pmu_read_single(fd);
>
> @@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd[0] = open_pmu(config);
> + fd[0] = open_pmu(gem_fd, config);
>
> /*
> * Second PMU client which is initialized after the first one,
> * and exists before it, should not affect accounting as reported
> * in the first client.
> */
> - fd[1] = open_pmu(config);
> + fd[1] = open_pmu(gem_fd, config);
>
> spin = spin_sync(gem_fd, 0, e);
>
> @@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
> * - cpu != 0 is not supported since i915 PMU only allows running on one cpu
> * and that is normally CPU0.
> */
> -static void invalid_init(void)
> +static void invalid_init(int i915)
> {
> struct perf_event_attr attr;
>
> @@ -1093,7 +1098,7 @@ static void invalid_init(void)
> do { \
> memset(&attr, 0, sizeof (attr)); \
> attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
> - attr.type = i915_type_id(); \
> + attr.type = i915_perf_type_id(i915); \
> igt_assert(attr.type != 0); \
> errno = 0; \
> } while(0)
> @@ -1112,11 +1117,11 @@ do { \
> igt_assert_eq(errno, EINVAL);
> }
>
> -static void init_other(unsigned int i, bool valid)
> +static void init_other(int i915, unsigned int i, bool valid)
> {
> int fd;
>
> - fd = perf_i915_open(__I915_PMU_OTHER(i));
> + fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
> igt_require(!(fd < 0 && errno == ENODEV));
> if (valid) {
> igt_assert(fd >= 0);
> @@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
> close(fd);
> }
>
> -static void read_other(unsigned int i, bool valid)
> +static void read_other(int i915, unsigned int i, bool valid)
> {
> int fd;
>
> - fd = perf_i915_open(__I915_PMU_OTHER(i));
> + fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
> igt_require(!(fd < 0 && errno == ENODEV));
> if (valid) {
> igt_assert(fd >= 0);
> @@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
>
> igt_require(cpu0_hotplug_support());
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
> + fd = open_pmu(gem_fd,
> + I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
>
> /*
> * Create two spinners so test can ensure shorter gaps in engine
> @@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_INTERRUPTS);
> + fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
>
> /* Queue spinning batches. */
> for (int i = 0; i < target; i++) {
> @@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_INTERRUPTS);
> + fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
>
> /* Queue spinning batches. */
> for (int i = 0; i < target; i++)
> @@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
> igt_require(max_freq > min_freq);
> igt_require(boost_freq > min_freq);
>
> - fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
> - open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
> + fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
> + open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
>
> /*
> * Set GPU to min frequency and read PMU counters.
> @@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
>
> /* While parked, our convention is to report the GPU at 0Hz */
>
> - fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
> - open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
> + fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
> + open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
>
> gem_quiescent_gpu(gem_fd); /* Be idle! */
> measured_usleep(2000); /* Wait for timers to cease */
> @@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_RC6_RESIDENCY);
> + fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
>
> if (flags & TEST_RUNTIME_PM) {
> drmModeRes *res;
> @@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
> usleep(500e3);
>
> /* Enable the PMU. */
> - fd = open_pmu(config);
> + fd = open_pmu(gem_fd, config);
>
> /* Stop load and close the PMU. */
> igt_stop_helper(&engine_load);
> @@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
> igt_spin_free(gem_fd, spin);
> }
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> /* Let the child run. */
> read(link[0], &expected, sizeof(expected));
> @@ -1835,7 +1841,7 @@ igt_main
> fd = drm_open_driver_master(DRIVER_INTEL);
>
> igt_require_gem(fd);
> - igt_require(i915_type_id() > 0);
> + igt_require(i915_perf_type_id(fd) > 0);
>
> __for_each_physical_engine(fd, e)
> num_engines++;
> @@ -1845,7 +1851,7 @@ igt_main
> * Test invalid access via perf API is rejected.
> */
> igt_subtest("invalid-init")
> - invalid_init();
> + invalid_init(fd);
>
> __for_each_physical_engine(fd, e) {
> const unsigned int pct[] = { 2, 50, 98 };
> @@ -1996,10 +2002,10 @@ igt_main
> */
> for (i = 0; i < num_other_metrics + 1; i++) {
> igt_subtest_f("other-init-%u", i)
> - init_other(i, i < num_other_metrics);
> + init_other(fd, i, i < num_other_metrics);
>
> igt_subtest_f("other-read-%u", i)
> - read_other(i, i < num_other_metrics);
> + read_other(fd, i, i < num_other_metrics);
> }
>
> /**
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index cc8db7c53..8197482dd 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
> ({ \
> int fd__; \
> \
> - fd__ = perf_i915_open_group((pmu)->config, (fd)); \
> + fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
> if (fd__ >= 0) { \
> if ((fd) == -1) \
> (fd) = fd__; \
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
@ 2020-01-07 9:53 ` Tvrtko Ursulin
0 siblings, 0 replies; 16+ messages in thread
From: Tvrtko Ursulin @ 2020-01-07 9:53 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, saurabhg.gupta, Tvrtko Ursulin
+Arek, Saurabhg
On 05/01/2020 01:06, Chris Wilson wrote:
> Since with multiple devices, we may have multiple different perf_pmu
> each with their own type, we want to find the right one for the job.
>
> The tests are run with a specific fd, from which we can extract the
> appropriate bus-id and find the associated perf-type. The performance
> monitoring tools are a little more general and not yet ready to probe
> all device or bind to one in particular, so we just assume the default
> igfx for the time being.
>
> v2: Extract the bus address from out of sysfs
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
> benchmarks/gem_wsim.c | 4 +-
> lib/igt_perf.c | 84 +++++++++++++++++++++++++++++++---
> lib/igt_perf.h | 13 ++++--
> overlay/gem-interrupts.c | 2 +-
> overlay/gpu-freq.c | 4 +-
> overlay/gpu-top.c | 12 ++---
> overlay/rc6.c | 2 +-
> tests/i915/gem_ctx_freq.c | 2 +-
> tests/i915/gem_ctx_sseu.c | 2 +-
> tests/i915/gem_exec_balancer.c | 18 +++++---
> tests/perf_pmu.c | 84 ++++++++++++++++++----------------
> tools/intel_gpu_top.c | 2 +-
> 12 files changed, 159 insertions(+), 70 deletions(-)
>
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index 6305e0d7a..9156fdc90 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
> for (d = &engines[0]; d->id != VCS; d++) {
> int pfd;
>
> - pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> - d->inst),
> + pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> + d->inst),
> bb->fd);
> if (pfd < 0) {
> if (d->id != VCS2)
> diff --git a/lib/igt_perf.c b/lib/igt_perf.c
> index e3dec2cc2..840add043 100644
> --- a/lib/igt_perf.c
> +++ b/lib/igt_perf.c
> @@ -4,17 +4,77 @@
> #include <stdlib.h>
> #include <string.h>
> #include <errno.h>
> +#include <sys/stat.h>
> #include <sys/sysinfo.h>
> +#include <sys/sysmacros.h>
>
> #include "igt_perf.h"
>
> -uint64_t i915_type_id(void)
> +static char *bus_address(int i915, char *path, int pathlen)
> +{
> + struct stat st;
> + int len = -1;
> + int dir;
> + char *s;
> +
> + if (fstat(i915, &st) || !S_ISCHR(st.st_mode))
> + return NULL;
> +
> + snprintf(path, pathlen, "/sys/dev/char/%d:%d",
> + major(st.st_rdev), minor(st.st_rdev));
> +
> + dir = open(path, O_RDONLY);
> + if (dir != -1) {
> + len = readlinkat(dir, "device", path, pathlen - 1);
> + close(dir);
> + }
> + if (len < 0)
> + return NULL;
> +
> + path[len] = '\0';
> +
> + /* strip off the relative path */
> + s = strrchr(path, '/');
> + if (s)
> + memmove(path, s + 1, len - (s - path) + 1);
> +
> + return path;
> +}
> +
> +const char *i915_perf_device(int i915, char *buf, int buflen)
> +{
> +#define prefix "i915-"
> +#define plen strlen(prefix)
> +
> + if (!buf || buflen < plen)
> + return "i915";
> +
> + memcpy(buf, prefix, plen);
> +
> + if (!bus_address(i915, buf + plen, buflen - plen) ||
> + strcmp(buf + plen, "0000:00:02.0") == 0) /* legacy name for igfx */
> + buf[plen - 1] = '\0';
> +
> + return buf;
> +}
So DRM fd -> PCI string conversion, yes? On a glance it looks okay.
However Arek probably has this data as part of "[PATCH i-g-t 0/4] device
selection && lsgpu" (https://patchwork.freedesktop.org/series/70285/).
Also:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/52
https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/51
And VLK-5588.
This patch is overlap with #52 and then #51/VLK-5588 is about allowing
card selection for tools.
How to meld the two with minimum effort? We could put this in and then
later replace the PCI name resolve with a library routine and re-adjust
tools to allow card selection via some mechanism.
Regards,
Tvrtko
> +
> +uint64_t i915_perf_type_id(int i915)
> +{
> + char buf[80];
> +
> + return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
> +}
> +
> +uint64_t igt_perf_type_id(const char *device)
> {
> char buf[64];
> ssize_t ret;
> int fd;
>
> - fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
> + snprintf(buf, sizeof(buf),
> + "/sys/bus/event_source/devices/%s/type", device);
> +
> + fd = open(buf, O_RDONLY);
> if (fd < 0)
> return 0;
>
> @@ -52,15 +112,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
> return ret;
> }
>
> -int perf_i915_open(uint64_t config)
> +int perf_igfx_open(uint64_t config)
> +{
> + return _perf_open(igt_perf_type_id("i915"), config, -1,
> + PERF_FORMAT_TOTAL_TIME_ENABLED);
> +}
> +
> +int perf_igfx_open_group(uint64_t config, int group)
> +{
> + return _perf_open(igt_perf_type_id("i915"), config, group,
> + PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
> +}
> +
> +int perf_i915_open(int i915, uint64_t config)
> {
> - return _perf_open(i915_type_id(), config, -1,
> + return _perf_open(i915_perf_type_id(i915), config, -1,
> PERF_FORMAT_TOTAL_TIME_ENABLED);
> }
>
> -int perf_i915_open_group(uint64_t config, int group)
> +int perf_i915_open_group(int i915, uint64_t config, int group)
> {
> - return _perf_open(i915_type_id(), config, group,
> + return _perf_open(i915_perf_type_id(i915), config, group,
> PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
> }
>
> diff --git a/lib/igt_perf.h b/lib/igt_perf.h
> index e00718f47..a8328c70c 100644
> --- a/lib/igt_perf.h
> +++ b/lib/igt_perf.h
> @@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
> return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
> }
>
> -uint64_t i915_type_id(void);
> -int perf_i915_open(uint64_t config);
> -int perf_i915_open_group(uint64_t config, int group);
> +uint64_t igt_perf_type_id(const char *device);
> int igt_perf_open(uint64_t type, uint64_t config);
> int igt_perf_open_group(uint64_t type, uint64_t config, int group);
>
> +const char *i915_perf_device(int i915, char *buf, int buflen);
> +uint64_t i915_perf_type_id(int i915);
> +
> +int perf_igfx_open(uint64_t config);
> +int perf_igfx_open_group(uint64_t config, int group);
> +
> +int perf_i915_open(int i915, uint64_t config);
> +int perf_i915_open_group(int i915, uint64_t config, int group);
> +
> #endif /* I915_PERF_H */
> diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
> index 0233fbb05..be73b6931 100644
> --- a/overlay/gem-interrupts.c
> +++ b/overlay/gem-interrupts.c
> @@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
> {
> memset(irqs, 0, sizeof(*irqs));
>
> - irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
> + irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
> if (irqs->fd < 0 && interrupts_read() < 0)
> irqs->error = ENODEV;
>
> diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
> index 0d8032592..b73157d39 100644
> --- a/overlay/gpu-freq.c
> +++ b/overlay/gpu-freq.c
> @@ -37,8 +37,8 @@ static int perf_open(void)
> {
> int fd;
>
> - fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
> - if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
> + fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
> + if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
> close(fd);
> fd = -1;
> }
> diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
> index 6cec2e943..32123abdd 100644
> --- a/overlay/gpu-top.c
> +++ b/overlay/gpu-top.c
> @@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
>
> d = &engines[0];
>
> - gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
> + gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
> -1);
> if (gt->fd < 0)
> return -1;
>
> - if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
> + if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
> gt->fd) >= 0)
> gt->have_wait = 1;
>
> - if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
> + if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
> gt->fd) >= 0)
> gt->have_sema = 1;
>
> @@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
> gt->num_rings = 1;
>
> for (d++; d->name; d++) {
> - if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> + if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> d->inst),
> gt->fd) < 0)
> continue;
>
> if (gt->have_wait &&
> - perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
> + perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
> d->inst),
> gt->fd) < 0)
> return -1;
>
> if (gt->have_sema &&
> - perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
> + perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
> d->inst),
> gt->fd) < 0)
> return -1;
> diff --git a/overlay/rc6.c b/overlay/rc6.c
> index b5286f0cf..69f95f288 100644
> --- a/overlay/rc6.c
> +++ b/overlay/rc6.c
> @@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
> {
> memset(rc6, 0, sizeof(*rc6));
>
> - rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
> + rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
> if (rc6->fd < 0) {
> struct stat st;
> if (stat("/sys/class/drm/card0/power", &st) < 0)
> diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
> index 89f3d11ef..5d2d3ec31 100644
> --- a/tests/i915/gem_ctx_freq.c
> +++ b/tests/i915/gem_ctx_freq.c
> @@ -136,7 +136,7 @@ static void sysfs_range(int i915)
>
> triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
>
> - pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
> + pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
> igt_require(pmu >= 0);
>
> for (int outer = 0; outer <= 2*N_STEPS; outer++) {
> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
> index 48e4411c8..38dc584bc 100644
> --- a/tests/i915/gem_ctx_sseu.c
> +++ b/tests/i915/gem_ctx_sseu.c
> @@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
>
> static bool has_engine(int fd, unsigned int class, unsigned int instance)
> {
> - int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
> + int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
>
> if (pmu >= 0)
> close(pmu);
> diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
> index f4909a978..cebcc39c7 100644
> --- a/tests/i915/gem_exec_balancer.c
> +++ b/tests/i915/gem_exec_balancer.c
> @@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
> {
> int fd;
>
> - fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
> + fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
> if (fd != -1) {
> close(fd);
> return true;
> @@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
> }
> }
>
> -static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
> +static int
> +add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
> {
> - return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
> + return perf_i915_open_group(i915,
> + I915_PMU_ENGINE_BUSY(ci->engine_class,
> ci->engine_instance),
> pmu);
> }
> @@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
> double load;
> int pmu;
>
> - pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
> + pmu = perf_i915_open(i915,
> + I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
> ci[idx].engine_instance));
>
> spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
> @@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
>
> pmu[0] = -1;
> for (int i = 0; i < limit; i++)
> - pmu[i] = add_pmu(pmu[0], &siblings[i]);
> - pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
> + pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
> + pmu[limit] = add_pmu(i915,
> + pmu[0], &master_engines[bond]);
>
> igt_assert(siblings[bond].engine_class !=
> master_engines[bond].engine_class);
> @@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
> for (unsigned int n = 0; n < count; n++) {
> uint32_t ctx;
>
> - pmu[n] = add_pmu(pmu[0], &ci[n]);
> + pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
>
> if (flags & PULSE) {
> struct drm_i915_gem_execbuffer2 eb = {
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index e1bbf2410..3e179daef 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
> const double tolerance = 0.05f;
> const unsigned long batch_duration_ns = 500e6;
>
> -static int open_pmu(uint64_t config)
> +static int open_pmu(int i915, uint64_t config)
> {
> int fd;
>
> - fd = perf_i915_open(config);
> + fd = perf_i915_open(i915, config);
> igt_skip_on(fd < 0 && errno == ENODEV);
> igt_assert(fd >= 0);
>
> return fd;
> }
>
> -static int open_group(uint64_t config, int group)
> +static int open_group(int i915, uint64_t config, int group)
> {
> int fd;
>
> - fd = perf_i915_open_group(config, group);
> + fd = perf_i915_open_group(i915, config, group);
> igt_skip_on(fd < 0 && errno == ENODEV);
> igt_assert(fd >= 0);
>
> @@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
> bool exists;
>
> errno = 0;
> - fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
> + fd = perf_i915_open(gem_fd,
> + __I915_PMU_ENGINE(e->class, e->instance, sample));
> if (fd < 0)
> err = errno;
>
> @@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
> uint64_t val;
> int fd;
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> if (flags & TEST_BUSY)
> spin = spin_sync(gem_fd, 0, e);
> @@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
>
> spin = __spin_sync(gem_fd, 0, e);
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> val = __pmu_read_single(fd, &ts[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
> * Open PMU as fast as possible after the second spin batch in attempt
> * to be faster than the driver handling lite-restore.
> */
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> val = __pmu_read_single(fd, &ts[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> if (e->class == e_->class && e->instance == e_->instance)
> busy_idx = i;
>
> - fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
> + fd[i++] = open_group(gem_fd,
> + I915_PMU_ENGINE_BUSY(e_->class,
> e_->instance),
> fd[0]);
> }
> @@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>
> fd[0] = -1;
> for (i = 0; i < num_engines; i++)
> - fd[i] = open_group(val[i], fd[0]);
> + fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> @@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>
> fd[0] = -1;
> for (i = 0; i < num_engines; i++)
> - fd[i] = open_group(val[i], fd[0]);
> + fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> @@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
> uint64_t val[2][2];
> int fd;
>
> - fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> - open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
> + fd = open_group(gem_fd,
> + I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> + open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
>
> if (flags & TEST_BUSY)
> spin = spin_sync(gem_fd, 0, e);
> @@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
> * to expected time spent in semaphore wait state.
> */
>
> - fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
>
> val[0] = pmu_read_single(fd);
>
> @@ -817,8 +820,9 @@ sema_busy(int gem_fd,
>
> igt_require(gem_scheduler_has_semaphores(gem_fd));
>
> - fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> - open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
> + fd = open_group(gem_fd,
> + I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> + open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
>
> __for_each_physical_engine(gem_fd, signal) {
> if (e->class == signal->class &&
> @@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
> data.pipe = p;
> prepare_crtc(&data, gem_fd, output);
>
> - fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
> + fd = open_pmu(gem_fd,
> + I915_PMU_ENGINE_WAIT(e->class, e->instance));
>
> val[0] = pmu_read_single(fd);
>
> @@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd[0] = open_pmu(config);
> + fd[0] = open_pmu(gem_fd, config);
>
> /*
> * Second PMU client which is initialized after the first one,
> * and exists before it, should not affect accounting as reported
> * in the first client.
> */
> - fd[1] = open_pmu(config);
> + fd[1] = open_pmu(gem_fd, config);
>
> spin = spin_sync(gem_fd, 0, e);
>
> @@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
> * - cpu != 0 is not supported since i915 PMU only allows running on one cpu
> * and that is normally CPU0.
> */
> -static void invalid_init(void)
> +static void invalid_init(int i915)
> {
> struct perf_event_attr attr;
>
> @@ -1093,7 +1098,7 @@ static void invalid_init(void)
> do { \
> memset(&attr, 0, sizeof (attr)); \
> attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
> - attr.type = i915_type_id(); \
> + attr.type = i915_perf_type_id(i915); \
> igt_assert(attr.type != 0); \
> errno = 0; \
> } while(0)
> @@ -1112,11 +1117,11 @@ do { \
> igt_assert_eq(errno, EINVAL);
> }
>
> -static void init_other(unsigned int i, bool valid)
> +static void init_other(int i915, unsigned int i, bool valid)
> {
> int fd;
>
> - fd = perf_i915_open(__I915_PMU_OTHER(i));
> + fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
> igt_require(!(fd < 0 && errno == ENODEV));
> if (valid) {
> igt_assert(fd >= 0);
> @@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
> close(fd);
> }
>
> -static void read_other(unsigned int i, bool valid)
> +static void read_other(int i915, unsigned int i, bool valid)
> {
> int fd;
>
> - fd = perf_i915_open(__I915_PMU_OTHER(i));
> + fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
> igt_require(!(fd < 0 && errno == ENODEV));
> if (valid) {
> igt_assert(fd >= 0);
> @@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
>
> igt_require(cpu0_hotplug_support());
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
> + fd = open_pmu(gem_fd,
> + I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
>
> /*
> * Create two spinners so test can ensure shorter gaps in engine
> @@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_INTERRUPTS);
> + fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
>
> /* Queue spinning batches. */
> for (int i = 0; i < target; i++) {
> @@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_INTERRUPTS);
> + fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
>
> /* Queue spinning batches. */
> for (int i = 0; i < target; i++)
> @@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
> igt_require(max_freq > min_freq);
> igt_require(boost_freq > min_freq);
>
> - fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
> - open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
> + fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
> + open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
>
> /*
> * Set GPU to min frequency and read PMU counters.
> @@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
>
> /* While parked, our convention is to report the GPU at 0Hz */
>
> - fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
> - open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
> + fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
> + open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
>
> gem_quiescent_gpu(gem_fd); /* Be idle! */
> measured_usleep(2000); /* Wait for timers to cease */
> @@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_RC6_RESIDENCY);
> + fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
>
> if (flags & TEST_RUNTIME_PM) {
> drmModeRes *res;
> @@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
> usleep(500e3);
>
> /* Enable the PMU. */
> - fd = open_pmu(config);
> + fd = open_pmu(gem_fd, config);
>
> /* Stop load and close the PMU. */
> igt_stop_helper(&engine_load);
> @@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
> igt_spin_free(gem_fd, spin);
> }
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> /* Let the child run. */
> read(link[0], &expected, sizeof(expected));
> @@ -1835,7 +1841,7 @@ igt_main
> fd = drm_open_driver_master(DRIVER_INTEL);
>
> igt_require_gem(fd);
> - igt_require(i915_type_id() > 0);
> + igt_require(i915_perf_type_id(fd) > 0);
>
> __for_each_physical_engine(fd, e)
> num_engines++;
> @@ -1845,7 +1851,7 @@ igt_main
> * Test invalid access via perf API is rejected.
> */
> igt_subtest("invalid-init")
> - invalid_init();
> + invalid_init(fd);
>
> __for_each_physical_engine(fd, e) {
> const unsigned int pct[] = { 2, 50, 98 };
> @@ -1996,10 +2002,10 @@ igt_main
> */
> for (i = 0; i < num_other_metrics + 1; i++) {
> igt_subtest_f("other-init-%u", i)
> - init_other(i, i < num_other_metrics);
> + init_other(fd, i, i < num_other_metrics);
>
> igt_subtest_f("other-read-%u", i)
> - read_other(i, i < num_other_metrics);
> + read_other(fd, i, i < num_other_metrics);
> }
>
> /**
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index cc8db7c53..8197482dd 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
> ({ \
> int fd__; \
> \
> - fd__ = perf_i915_open_group((pmu)->config, (fd)); \
> + fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
> if (fd__ >= 0) { \
> if ((fd) == -1) \
> (fd) = fd__; \
>
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
2020-01-07 9:53 ` Tvrtko Ursulin
@ 2020-01-07 10:32 ` Chris Wilson
-1 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-07 10:32 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: igt-dev, saurabhg.gupta
Quoting Tvrtko Ursulin (2020-01-07 09:53:39)
>
> +Arek, Saurabhg
>
> On 05/01/2020 01:06, Chris Wilson wrote:
> > Since with multiple devices, we may have multiple different perf_pmu
> > each with their own type, we want to find the right one for the job.
> >
> > The tests are run with a specific fd, from which we can extract the
> > appropriate bus-id and find the associated perf-type. The performance
> > monitoring tools are a little more general and not yet ready to probe
> > all device or bind to one in particular, so we just assume the default
> > igfx for the time being.
> >
> > v2: Extract the bus address from out of sysfs
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > ---
> > benchmarks/gem_wsim.c | 4 +-
> > lib/igt_perf.c | 84 +++++++++++++++++++++++++++++++---
> > lib/igt_perf.h | 13 ++++--
> > overlay/gem-interrupts.c | 2 +-
> > overlay/gpu-freq.c | 4 +-
> > overlay/gpu-top.c | 12 ++---
> > overlay/rc6.c | 2 +-
> > tests/i915/gem_ctx_freq.c | 2 +-
> > tests/i915/gem_ctx_sseu.c | 2 +-
> > tests/i915/gem_exec_balancer.c | 18 +++++---
> > tests/perf_pmu.c | 84 ++++++++++++++++++----------------
> > tools/intel_gpu_top.c | 2 +-
> > 12 files changed, 159 insertions(+), 70 deletions(-)
> >
> > diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> > index 6305e0d7a..9156fdc90 100644
> > --- a/benchmarks/gem_wsim.c
> > +++ b/benchmarks/gem_wsim.c
> > @@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
> > for (d = &engines[0]; d->id != VCS; d++) {
> > int pfd;
> >
> > - pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> > - d->inst),
> > + pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> > + d->inst),
> > bb->fd);
> > if (pfd < 0) {
> > if (d->id != VCS2)
> > diff --git a/lib/igt_perf.c b/lib/igt_perf.c
> > index e3dec2cc2..840add043 100644
> > --- a/lib/igt_perf.c
> > +++ b/lib/igt_perf.c
> > @@ -4,17 +4,77 @@
> > #include <stdlib.h>
> > #include <string.h>
> > #include <errno.h>
> > +#include <sys/stat.h>
> > #include <sys/sysinfo.h>
> > +#include <sys/sysmacros.h>
> >
> > #include "igt_perf.h"
> >
> > -uint64_t i915_type_id(void)
> > +static char *bus_address(int i915, char *path, int pathlen)
> > +{
> > + struct stat st;
> > + int len = -1;
> > + int dir;
> > + char *s;
> > +
> > + if (fstat(i915, &st) || !S_ISCHR(st.st_mode))
> > + return NULL;
> > +
> > + snprintf(path, pathlen, "/sys/dev/char/%d:%d",
> > + major(st.st_rdev), minor(st.st_rdev));
> > +
> > + dir = open(path, O_RDONLY);
> > + if (dir != -1) {
> > + len = readlinkat(dir, "device", path, pathlen - 1);
> > + close(dir);
> > + }
> > + if (len < 0)
> > + return NULL;
> > +
> > + path[len] = '\0';
> > +
> > + /* strip off the relative path */
> > + s = strrchr(path, '/');
> > + if (s)
> > + memmove(path, s + 1, len - (s - path) + 1);
> > +
> > + return path;
> > +}
> > +
> > +const char *i915_perf_device(int i915, char *buf, int buflen)
> > +{
> > +#define prefix "i915-"
> > +#define plen strlen(prefix)
> > +
> > + if (!buf || buflen < plen)
> > + return "i915";
> > +
> > + memcpy(buf, prefix, plen);
> > +
> > + if (!bus_address(i915, buf + plen, buflen - plen) ||
> > + strcmp(buf + plen, "0000:00:02.0") == 0) /* legacy name for igfx */
> > + buf[plen - 1] = '\0';
> > +
> > + return buf;
> > +}
>
> So DRM fd -> PCI string conversion, yes? On a glance it looks okay.
> However Arek probably has this data as part of "[PATCH i-g-t 0/4] device
> selection && lsgpu" (https://patchwork.freedesktop.org/series/70285/).
If the string is known, we can use it. This simple routine is *simple*
yet effective :)
> Also:
>
> https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/52
> https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/51
How lightweight are they aiming to be?
> And VLK-5588.
>
> This patch is overlap with #52 and then #51/VLK-5588 is about allowing
> card selection for tools.
>
> How to meld the two with minimum effort? We could put this in and then
> later replace the PCI name resolve with a library routine and re-adjust
> tools to allow card selection via some mechanism.
Exactly. All we need here is a name to lookup the perf type id. One
routine to provide an introspection method for a given fd and assumption
of i915, does not prevent better methods :)
I do wonder though if we should have perf_name in our sysfs.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
@ 2020-01-07 10:32 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-07 10:32 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: igt-dev, saurabhg.gupta, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2020-01-07 09:53:39)
>
> +Arek, Saurabhg
>
> On 05/01/2020 01:06, Chris Wilson wrote:
> > Since with multiple devices, we may have multiple different perf_pmu
> > each with their own type, we want to find the right one for the job.
> >
> > The tests are run with a specific fd, from which we can extract the
> > appropriate bus-id and find the associated perf-type. The performance
> > monitoring tools are a little more general and not yet ready to probe
> > all device or bind to one in particular, so we just assume the default
> > igfx for the time being.
> >
> > v2: Extract the bus address from out of sysfs
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > ---
> > benchmarks/gem_wsim.c | 4 +-
> > lib/igt_perf.c | 84 +++++++++++++++++++++++++++++++---
> > lib/igt_perf.h | 13 ++++--
> > overlay/gem-interrupts.c | 2 +-
> > overlay/gpu-freq.c | 4 +-
> > overlay/gpu-top.c | 12 ++---
> > overlay/rc6.c | 2 +-
> > tests/i915/gem_ctx_freq.c | 2 +-
> > tests/i915/gem_ctx_sseu.c | 2 +-
> > tests/i915/gem_exec_balancer.c | 18 +++++---
> > tests/perf_pmu.c | 84 ++++++++++++++++++----------------
> > tools/intel_gpu_top.c | 2 +-
> > 12 files changed, 159 insertions(+), 70 deletions(-)
> >
> > diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> > index 6305e0d7a..9156fdc90 100644
> > --- a/benchmarks/gem_wsim.c
> > +++ b/benchmarks/gem_wsim.c
> > @@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
> > for (d = &engines[0]; d->id != VCS; d++) {
> > int pfd;
> >
> > - pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> > - d->inst),
> > + pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> > + d->inst),
> > bb->fd);
> > if (pfd < 0) {
> > if (d->id != VCS2)
> > diff --git a/lib/igt_perf.c b/lib/igt_perf.c
> > index e3dec2cc2..840add043 100644
> > --- a/lib/igt_perf.c
> > +++ b/lib/igt_perf.c
> > @@ -4,17 +4,77 @@
> > #include <stdlib.h>
> > #include <string.h>
> > #include <errno.h>
> > +#include <sys/stat.h>
> > #include <sys/sysinfo.h>
> > +#include <sys/sysmacros.h>
> >
> > #include "igt_perf.h"
> >
> > -uint64_t i915_type_id(void)
> > +static char *bus_address(int i915, char *path, int pathlen)
> > +{
> > + struct stat st;
> > + int len = -1;
> > + int dir;
> > + char *s;
> > +
> > + if (fstat(i915, &st) || !S_ISCHR(st.st_mode))
> > + return NULL;
> > +
> > + snprintf(path, pathlen, "/sys/dev/char/%d:%d",
> > + major(st.st_rdev), minor(st.st_rdev));
> > +
> > + dir = open(path, O_RDONLY);
> > + if (dir != -1) {
> > + len = readlinkat(dir, "device", path, pathlen - 1);
> > + close(dir);
> > + }
> > + if (len < 0)
> > + return NULL;
> > +
> > + path[len] = '\0';
> > +
> > + /* strip off the relative path */
> > + s = strrchr(path, '/');
> > + if (s)
> > + memmove(path, s + 1, len - (s - path) + 1);
> > +
> > + return path;
> > +}
> > +
> > +const char *i915_perf_device(int i915, char *buf, int buflen)
> > +{
> > +#define prefix "i915-"
> > +#define plen strlen(prefix)
> > +
> > + if (!buf || buflen < plen)
> > + return "i915";
> > +
> > + memcpy(buf, prefix, plen);
> > +
> > + if (!bus_address(i915, buf + plen, buflen - plen) ||
> > + strcmp(buf + plen, "0000:00:02.0") == 0) /* legacy name for igfx */
> > + buf[plen - 1] = '\0';
> > +
> > + return buf;
> > +}
>
> So DRM fd -> PCI string conversion, yes? On a glance it looks okay.
> However Arek probably has this data as part of "[PATCH i-g-t 0/4] device
> selection && lsgpu" (https://patchwork.freedesktop.org/series/70285/).
If the string is known, we can use it. This simple routine is *simple*
yet effective :)
> Also:
>
> https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/52
> https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/51
How lightweight are they aiming to be?
> And VLK-5588.
>
> This patch is overlap with #52 and then #51/VLK-5588 is about allowing
> card selection for tools.
>
> How to meld the two with minimum effort? We could put this in and then
> later replace the PCI name resolve with a library routine and re-adjust
> tools to allow card selection via some mechanism.
Exactly. All we need here is a name to lookup the perf type id. One
routine to provide an introspection method for a given fd and assumption
of i915, does not prevent better methods :)
I do wonder though if we should have perf_name in our sysfs.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
2020-01-07 10:32 ` Chris Wilson
@ 2020-01-08 22:19 ` Fosha, Robert M
-1 siblings, 0 replies; 16+ messages in thread
From: Fosha, Robert M @ 2020-01-08 22:19 UTC (permalink / raw)
To: Chris Wilson, Tvrtko Ursulin, intel-gfx; +Cc: igt-dev, saurabhg.gupta
On 1/7/20 2:32 AM, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2020-01-07 09:53:39)
>> +Arek, Saurabhg
>>
>> On 05/01/2020 01:06, Chris Wilson wrote:
>>> Since with multiple devices, we may have multiple different perf_pmu
>>> each with their own type, we want to find the right one for the job.
>>>
>>> The tests are run with a specific fd, from which we can extract the
>>> appropriate bus-id and find the associated perf-type. The performance
>>> monitoring tools are a little more general and not yet ready to probe
>>> all device or bind to one in particular, so we just assume the default
>>> igfx for the time being.
>>>
>>> v2: Extract the bus address from out of sysfs
>>>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Tested-by: Robert M. Fosha <robert.m.fosha@intel.com>
>>> ---
>>> benchmarks/gem_wsim.c | 4 +-
>>> lib/igt_perf.c | 84 +++++++++++++++++++++++++++++++---
>>> lib/igt_perf.h | 13 ++++--
>>> overlay/gem-interrupts.c | 2 +-
>>> overlay/gpu-freq.c | 4 +-
>>> overlay/gpu-top.c | 12 ++---
>>> overlay/rc6.c | 2 +-
>>> tests/i915/gem_ctx_freq.c | 2 +-
>>> tests/i915/gem_ctx_sseu.c | 2 +-
>>> tests/i915/gem_exec_balancer.c | 18 +++++---
>>> tests/perf_pmu.c | 84 ++++++++++++++++++----------------
>>> tools/intel_gpu_top.c | 2 +-
>>> 12 files changed, 159 insertions(+), 70 deletions(-)
>>>
>>> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
>>> index 6305e0d7a..9156fdc90 100644
>>> --- a/benchmarks/gem_wsim.c
>>> +++ b/benchmarks/gem_wsim.c
>>> @@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
>>> for (d = &engines[0]; d->id != VCS; d++) {
>>> int pfd;
>>>
>>> - pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
>>> - d->inst),
>>> + pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
>>> + d->inst),
>>> bb->fd);
>>> if (pfd < 0) {
>>> if (d->id != VCS2)
>>> diff --git a/lib/igt_perf.c b/lib/igt_perf.c
>>> index e3dec2cc2..840add043 100644
>>> --- a/lib/igt_perf.c
>>> +++ b/lib/igt_perf.c
>>> @@ -4,17 +4,77 @@
>>> #include <stdlib.h>
>>> #include <string.h>
>>> #include <errno.h>
>>> +#include <sys/stat.h>
>>> #include <sys/sysinfo.h>
>>> +#include <sys/sysmacros.h>
>>>
>>> #include "igt_perf.h"
>>>
>>> -uint64_t i915_type_id(void)
>>> +static char *bus_address(int i915, char *path, int pathlen)
>>> +{
>>> + struct stat st;
>>> + int len = -1;
>>> + int dir;
>>> + char *s;
>>> +
>>> + if (fstat(i915, &st) || !S_ISCHR(st.st_mode))
>>> + return NULL;
>>> +
>>> + snprintf(path, pathlen, "/sys/dev/char/%d:%d",
>>> + major(st.st_rdev), minor(st.st_rdev));
>>> +
>>> + dir = open(path, O_RDONLY);
>>> + if (dir != -1) {
>>> + len = readlinkat(dir, "device", path, pathlen - 1);
>>> + close(dir);
>>> + }
>>> + if (len < 0)
>>> + return NULL;
>>> +
>>> + path[len] = '\0';
>>> +
>>> + /* strip off the relative path */
>>> + s = strrchr(path, '/');
>>> + if (s)
>>> + memmove(path, s + 1, len - (s - path) + 1);
>>> +
>>> + return path;
>>> +}
>>> +
>>> +const char *i915_perf_device(int i915, char *buf, int buflen)
>>> +{
>>> +#define prefix "i915-"
>>> +#define plen strlen(prefix)
>>> +
>>> + if (!buf || buflen < plen)
>>> + return "i915";
>>> +
>>> + memcpy(buf, prefix, plen);
>>> +
>>> + if (!bus_address(i915, buf + plen, buflen - plen) ||
>>> + strcmp(buf + plen, "0000:00:02.0") == 0) /* legacy name for igfx */
>>> + buf[plen - 1] = '\0';
>>> +
>>> + return buf;
>>> +}
>> So DRM fd -> PCI string conversion, yes? On a glance it looks okay.
>> However Arek probably has this data as part of "[PATCH i-g-t 0/4] device
>> selection && lsgpu" (https://patchwork.freedesktop.org/series/70285/).
> If the string is known, we can use it. This simple routine is *simple*
> yet effective :)
>
>> Also:
>>
>> https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/52
>> https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/51
> How lightweight are they aiming to be?
>
>> And VLK-5588.
>>
>> This patch is overlap with #52 and then #51/VLK-5588 is about allowing
>> card selection for tools.
>>
>> How to meld the two with minimum effort? We could put this in and then
>> later replace the PCI name resolve with a library routine and re-adjust
>> tools to allow card selection via some mechanism.
> Exactly. All we need here is a name to lookup the perf type id. One
> routine to provide an introspection method for a given fd and assumption
> of i915, does not prevent better methods :)
>
> I do wonder though if we should have perf_name in our sysfs.
> -Chris
Agree with idea of adding this change now and re-adjusting if other
mechanism is added for other tests/tools. If no other concerns from
Tvrtko or Arek
Reviewed-by: Robert M. Fosha <robert.m.fosha@intel.com>
-Rob
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
@ 2020-01-08 22:19 ` Fosha, Robert M
0 siblings, 0 replies; 16+ messages in thread
From: Fosha, Robert M @ 2020-01-08 22:19 UTC (permalink / raw)
To: Chris Wilson, Tvrtko Ursulin, intel-gfx
Cc: igt-dev, saurabhg.gupta, Tvrtko Ursulin
On 1/7/20 2:32 AM, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2020-01-07 09:53:39)
>> +Arek, Saurabhg
>>
>> On 05/01/2020 01:06, Chris Wilson wrote:
>>> Since with multiple devices, we may have multiple different perf_pmu
>>> each with their own type, we want to find the right one for the job.
>>>
>>> The tests are run with a specific fd, from which we can extract the
>>> appropriate bus-id and find the associated perf-type. The performance
>>> monitoring tools are a little more general and not yet ready to probe
>>> all device or bind to one in particular, so we just assume the default
>>> igfx for the time being.
>>>
>>> v2: Extract the bus address from out of sysfs
>>>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Tested-by: Robert M. Fosha <robert.m.fosha@intel.com>
>>> ---
>>> benchmarks/gem_wsim.c | 4 +-
>>> lib/igt_perf.c | 84 +++++++++++++++++++++++++++++++---
>>> lib/igt_perf.h | 13 ++++--
>>> overlay/gem-interrupts.c | 2 +-
>>> overlay/gpu-freq.c | 4 +-
>>> overlay/gpu-top.c | 12 ++---
>>> overlay/rc6.c | 2 +-
>>> tests/i915/gem_ctx_freq.c | 2 +-
>>> tests/i915/gem_ctx_sseu.c | 2 +-
>>> tests/i915/gem_exec_balancer.c | 18 +++++---
>>> tests/perf_pmu.c | 84 ++++++++++++++++++----------------
>>> tools/intel_gpu_top.c | 2 +-
>>> 12 files changed, 159 insertions(+), 70 deletions(-)
>>>
>>> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
>>> index 6305e0d7a..9156fdc90 100644
>>> --- a/benchmarks/gem_wsim.c
>>> +++ b/benchmarks/gem_wsim.c
>>> @@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
>>> for (d = &engines[0]; d->id != VCS; d++) {
>>> int pfd;
>>>
>>> - pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
>>> - d->inst),
>>> + pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
>>> + d->inst),
>>> bb->fd);
>>> if (pfd < 0) {
>>> if (d->id != VCS2)
>>> diff --git a/lib/igt_perf.c b/lib/igt_perf.c
>>> index e3dec2cc2..840add043 100644
>>> --- a/lib/igt_perf.c
>>> +++ b/lib/igt_perf.c
>>> @@ -4,17 +4,77 @@
>>> #include <stdlib.h>
>>> #include <string.h>
>>> #include <errno.h>
>>> +#include <sys/stat.h>
>>> #include <sys/sysinfo.h>
>>> +#include <sys/sysmacros.h>
>>>
>>> #include "igt_perf.h"
>>>
>>> -uint64_t i915_type_id(void)
>>> +static char *bus_address(int i915, char *path, int pathlen)
>>> +{
>>> + struct stat st;
>>> + int len = -1;
>>> + int dir;
>>> + char *s;
>>> +
>>> + if (fstat(i915, &st) || !S_ISCHR(st.st_mode))
>>> + return NULL;
>>> +
>>> + snprintf(path, pathlen, "/sys/dev/char/%d:%d",
>>> + major(st.st_rdev), minor(st.st_rdev));
>>> +
>>> + dir = open(path, O_RDONLY);
>>> + if (dir != -1) {
>>> + len = readlinkat(dir, "device", path, pathlen - 1);
>>> + close(dir);
>>> + }
>>> + if (len < 0)
>>> + return NULL;
>>> +
>>> + path[len] = '\0';
>>> +
>>> + /* strip off the relative path */
>>> + s = strrchr(path, '/');
>>> + if (s)
>>> + memmove(path, s + 1, len - (s - path) + 1);
>>> +
>>> + return path;
>>> +}
>>> +
>>> +const char *i915_perf_device(int i915, char *buf, int buflen)
>>> +{
>>> +#define prefix "i915-"
>>> +#define plen strlen(prefix)
>>> +
>>> + if (!buf || buflen < plen)
>>> + return "i915";
>>> +
>>> + memcpy(buf, prefix, plen);
>>> +
>>> + if (!bus_address(i915, buf + plen, buflen - plen) ||
>>> + strcmp(buf + plen, "0000:00:02.0") == 0) /* legacy name for igfx */
>>> + buf[plen - 1] = '\0';
>>> +
>>> + return buf;
>>> +}
>> So DRM fd -> PCI string conversion, yes? On a glance it looks okay.
>> However Arek probably has this data as part of "[PATCH i-g-t 0/4] device
>> selection && lsgpu" (https://patchwork.freedesktop.org/series/70285/).
> If the string is known, we can use it. This simple routine is *simple*
> yet effective :)
>
>> Also:
>>
>> https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/52
>> https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/51
> How lightweight are they aiming to be?
>
>> And VLK-5588.
>>
>> This patch is overlap with #52 and then #51/VLK-5588 is about allowing
>> card selection for tools.
>>
>> How to meld the two with minimum effort? We could put this in and then
>> later replace the PCI name resolve with a library routine and re-adjust
>> tools to allow card selection via some mechanism.
> Exactly. All we need here is a name to lookup the perf type id. One
> routine to provide an introspection method for a given fd and assumption
> of i915, does not prevent better methods :)
>
> I do wonder though if we should have perf_name in our sysfs.
> -Chris
Agree with idea of adding this change now and re-adjusting if other
mechanism is added for other tests/tools. If no other concerns from
Tvrtko or Arek
Reviewed-by: Robert M. Fosha <robert.m.fosha@intel.com>
-Rob
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
2020-01-03 17:41 [Intel-gfx] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device Chris Wilson
@ 2020-01-03 21:20 ` Fosha, Robert M
0 siblings, 0 replies; 16+ messages in thread
From: Fosha, Robert M @ 2020-01-03 21:20 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 1/3/20 9:41 AM, Chris Wilson wrote:
> Since with multiple devices, we may have multiple different perf_pmu
> each with their own type, we want to find the right one for the job.
>
> The tests are run with a specific fd, from which we can extract the
> appropriate bus-id and find the associated perf-type. The performance
> monitoring tools are a little more general and not yet ready to probe
> all device or bind to one in particular, so we just assume the default
> igfx for the time being.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
> benchmarks/gem_wsim.c | 4 +-
> lib/igt_perf.c | 66 +++++++++++++++++++++++---
> lib/igt_perf.h | 13 ++++--
> overlay/gem-interrupts.c | 2 +-
> overlay/gpu-freq.c | 4 +-
> overlay/gpu-top.c | 12 ++---
> overlay/rc6.c | 2 +-
> tests/i915/gem_ctx_freq.c | 2 +-
> tests/i915/gem_ctx_sseu.c | 2 +-
> tests/i915/gem_exec_balancer.c | 18 +++++---
> tests/perf_pmu.c | 84 ++++++++++++++++++----------------
> tools/intel_gpu_top.c | 2 +-
> 12 files changed, 141 insertions(+), 70 deletions(-)
>
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index 6305e0d7a..9156fdc90 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
> for (d = &engines[0]; d->id != VCS; d++) {
> int pfd;
>
> - pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> - d->inst),
> + pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> + d->inst),
> bb->fd);
> if (pfd < 0) {
> if (d->id != VCS2)
> diff --git a/lib/igt_perf.c b/lib/igt_perf.c
> index e3dec2cc2..4922a2df7 100644
> --- a/lib/igt_perf.c
> +++ b/lib/igt_perf.c
> @@ -4,17 +4,59 @@
> #include <stdlib.h>
> #include <string.h>
> #include <errno.h>
> +#include <sys/ioctl.h>
> #include <sys/sysinfo.h>
>
> #include "igt_perf.h"
>
> -uint64_t i915_type_id(void)
> +const char *i915_perf_device(int i915, char *buf, int buflen)
> +{
> + drm_unique_t u = {
> + .unique = buf + 1,
> + .unique_len = buflen - 1,
> + };
> + drm_set_version_t sv = {
> + .drm_di_major = 1,
> + .drm_di_minor = 4,
> + .drm_dd_major = -1, /* Don't care */
> + .drm_dd_minor = -1, /* Don't care */
> + };
> +
> + if (ioctl(i915, DRM_IOCTL_SET_VERSION, &sv))
> + return "i915";
perf_pmu has test cases that use drm_open_driver_render() and pass the
render_fd. What about this cases?
> +
> + memset(buf, 0, buflen);
> + ioctl(i915, DRM_IOCTL_GET_UNIQUE, &u);
> +
> + if (u.unique_len >= buflen)
> + return NULL;
> +
> + if (strncmp(buf + 1, "pci:", 4))
> + return NULL;
> +
> + if (strcmp(buf + 1, "pci:0000:00:02.0") == 0)
> + return "i915";
> +
> + return memcpy(buf, "i915-", strlen("i915-"));
> +}
> +
> +uint64_t i915_perf_type_id(int i915)
> +{
> + char buf[80];
> +
> + return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
> +}
> +
> +uint64_t igt_perf_type_id(const char *device)
> {
> char buf[64];
> ssize_t ret;
> int fd;
>
> - fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
> + snprintf(buf, sizeof(buf),
> + "/sys/bus/event_source/devices/%s/type", device);
> +
> + fd = open(buf, O_RDONLY);
> if (fd < 0)
> return 0;
>
> @@ -52,15 +94,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
> return ret;
> }
>
> -int perf_i915_open(uint64_t config)
> +int perf_igfx_open(uint64_t config)
> +{
> + return _perf_open(igt_perf_type_id("i915"), config, -1,
> + PERF_FORMAT_TOTAL_TIME_ENABLED);
> +}
> +
> +int perf_igfx_open_group(uint64_t config, int group)
> +{
> + return _perf_open(igt_perf_type_id("i915"), config, group,
> + PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
> +}
> +
> +int perf_i915_open(int i915, uint64_t config)
> {
> - return _perf_open(i915_type_id(), config, -1,
> + return _perf_open(i915_perf_type_id(i915), config, -1,
> PERF_FORMAT_TOTAL_TIME_ENABLED);
> }
>
> -int perf_i915_open_group(uint64_t config, int group)
> +int perf_i915_open_group(int i915, uint64_t config, int group)
> {
> - return _perf_open(i915_type_id(), config, group,
> + return _perf_open(i915_perf_type_id(i915), config, group,
> PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
> }
>
> diff --git a/lib/igt_perf.h b/lib/igt_perf.h
> index e00718f47..a8328c70c 100644
> --- a/lib/igt_perf.h
> +++ b/lib/igt_perf.h
> @@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
> return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
> }
>
> -uint64_t i915_type_id(void);
> -int perf_i915_open(uint64_t config);
> -int perf_i915_open_group(uint64_t config, int group);
> +uint64_t igt_perf_type_id(const char *device);
> int igt_perf_open(uint64_t type, uint64_t config);
> int igt_perf_open_group(uint64_t type, uint64_t config, int group);
>
> +const char *i915_perf_device(int i915, char *buf, int buflen);
> +uint64_t i915_perf_type_id(int i915);
> +
> +int perf_igfx_open(uint64_t config);
> +int perf_igfx_open_group(uint64_t config, int group);
> +
> +int perf_i915_open(int i915, uint64_t config);
> +int perf_i915_open_group(int i915, uint64_t config, int group);
> +
> #endif /* I915_PERF_H */
> diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
> index 0233fbb05..be73b6931 100644
> --- a/overlay/gem-interrupts.c
> +++ b/overlay/gem-interrupts.c
> @@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
> {
> memset(irqs, 0, sizeof(*irqs));
>
> - irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
> + irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
> if (irqs->fd < 0 && interrupts_read() < 0)
> irqs->error = ENODEV;
>
> diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
> index 0d8032592..b73157d39 100644
> --- a/overlay/gpu-freq.c
> +++ b/overlay/gpu-freq.c
> @@ -37,8 +37,8 @@ static int perf_open(void)
> {
> int fd;
>
> - fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
> - if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
> + fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
> + if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
> close(fd);
> fd = -1;
> }
> diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
> index 6cec2e943..32123abdd 100644
> --- a/overlay/gpu-top.c
> +++ b/overlay/gpu-top.c
> @@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
>
> d = &engines[0];
>
> - gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
> + gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
> -1);
> if (gt->fd < 0)
> return -1;
>
> - if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
> + if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
> gt->fd) >= 0)
> gt->have_wait = 1;
>
> - if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
> + if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
> gt->fd) >= 0)
> gt->have_sema = 1;
>
> @@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
> gt->num_rings = 1;
>
> for (d++; d->name; d++) {
> - if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> + if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> d->inst),
> gt->fd) < 0)
> continue;
>
> if (gt->have_wait &&
> - perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
> + perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
> d->inst),
> gt->fd) < 0)
> return -1;
>
> if (gt->have_sema &&
> - perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
> + perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
> d->inst),
> gt->fd) < 0)
> return -1;
> diff --git a/overlay/rc6.c b/overlay/rc6.c
> index b5286f0cf..69f95f288 100644
> --- a/overlay/rc6.c
> +++ b/overlay/rc6.c
> @@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
> {
> memset(rc6, 0, sizeof(*rc6));
>
> - rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
> + rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
> if (rc6->fd < 0) {
> struct stat st;
> if (stat("/sys/class/drm/card0/power", &st) < 0)
> diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
> index 89f3d11ef..5d2d3ec31 100644
> --- a/tests/i915/gem_ctx_freq.c
> +++ b/tests/i915/gem_ctx_freq.c
> @@ -136,7 +136,7 @@ static void sysfs_range(int i915)
>
> triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
>
> - pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
> + pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
> igt_require(pmu >= 0);
>
> for (int outer = 0; outer <= 2*N_STEPS; outer++) {
> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
> index 48e4411c8..38dc584bc 100644
> --- a/tests/i915/gem_ctx_sseu.c
> +++ b/tests/i915/gem_ctx_sseu.c
> @@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
>
> static bool has_engine(int fd, unsigned int class, unsigned int instance)
> {
> - int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
> + int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
>
> if (pmu >= 0)
> close(pmu);
> diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
> index f4909a978..cebcc39c7 100644
> --- a/tests/i915/gem_exec_balancer.c
> +++ b/tests/i915/gem_exec_balancer.c
> @@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
> {
> int fd;
>
> - fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
> + fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
> if (fd != -1) {
> close(fd);
> return true;
> @@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
> }
> }
>
> -static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
> +static int
> +add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
> {
> - return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
> + return perf_i915_open_group(i915,
> + I915_PMU_ENGINE_BUSY(ci->engine_class,
> ci->engine_instance),
> pmu);
> }
> @@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
> double load;
> int pmu;
>
> - pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
> + pmu = perf_i915_open(i915,
> + I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
> ci[idx].engine_instance));
>
> spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
> @@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
>
> pmu[0] = -1;
> for (int i = 0; i < limit; i++)
> - pmu[i] = add_pmu(pmu[0], &siblings[i]);
> - pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
> + pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
> + pmu[limit] = add_pmu(i915,
> + pmu[0], &master_engines[bond]);
>
> igt_assert(siblings[bond].engine_class !=
> master_engines[bond].engine_class);
> @@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
> for (unsigned int n = 0; n < count; n++) {
> uint32_t ctx;
>
> - pmu[n] = add_pmu(pmu[0], &ci[n]);
> + pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
>
> if (flags & PULSE) {
> struct drm_i915_gem_execbuffer2 eb = {
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index e1bbf2410..3e179daef 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
> const double tolerance = 0.05f;
> const unsigned long batch_duration_ns = 500e6;
>
> -static int open_pmu(uint64_t config)
> +static int open_pmu(int i915, uint64_t config)
> {
> int fd;
>
> - fd = perf_i915_open(config);
> + fd = perf_i915_open(i915, config);
> igt_skip_on(fd < 0 && errno == ENODEV);
> igt_assert(fd >= 0);
>
> return fd;
> }
>
> -static int open_group(uint64_t config, int group)
> +static int open_group(int i915, uint64_t config, int group)
> {
> int fd;
>
> - fd = perf_i915_open_group(config, group);
> + fd = perf_i915_open_group(i915, config, group);
> igt_skip_on(fd < 0 && errno == ENODEV);
> igt_assert(fd >= 0);
>
> @@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
> bool exists;
>
> errno = 0;
> - fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
> + fd = perf_i915_open(gem_fd,
> + __I915_PMU_ENGINE(e->class, e->instance, sample));
> if (fd < 0)
> err = errno;
>
> @@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
> uint64_t val;
> int fd;
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> if (flags & TEST_BUSY)
> spin = spin_sync(gem_fd, 0, e);
> @@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
>
> spin = __spin_sync(gem_fd, 0, e);
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> val = __pmu_read_single(fd, &ts[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
> * Open PMU as fast as possible after the second spin batch in attempt
> * to be faster than the driver handling lite-restore.
> */
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> val = __pmu_read_single(fd, &ts[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> if (e->class == e_->class && e->instance == e_->instance)
> busy_idx = i;
>
> - fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
> + fd[i++] = open_group(gem_fd,
> + I915_PMU_ENGINE_BUSY(e_->class,
> e_->instance),
> fd[0]);
> }
> @@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>
> fd[0] = -1;
> for (i = 0; i < num_engines; i++)
> - fd[i] = open_group(val[i], fd[0]);
> + fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> @@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>
> fd[0] = -1;
> for (i = 0; i < num_engines; i++)
> - fd[i] = open_group(val[i], fd[0]);
> + fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> @@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
> uint64_t val[2][2];
> int fd;
>
> - fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> - open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
> + fd = open_group(gem_fd,
> + I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> + open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
>
> if (flags & TEST_BUSY)
> spin = spin_sync(gem_fd, 0, e);
> @@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
> * to expected time spent in semaphore wait state.
> */
>
> - fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
>
> val[0] = pmu_read_single(fd);
>
> @@ -817,8 +820,9 @@ sema_busy(int gem_fd,
>
> igt_require(gem_scheduler_has_semaphores(gem_fd));
>
> - fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> - open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
> + fd = open_group(gem_fd,
> + I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> + open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
>
> __for_each_physical_engine(gem_fd, signal) {
> if (e->class == signal->class &&
> @@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
> data.pipe = p;
> prepare_crtc(&data, gem_fd, output);
>
> - fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
> + fd = open_pmu(gem_fd,
> + I915_PMU_ENGINE_WAIT(e->class, e->instance));
>
> val[0] = pmu_read_single(fd);
>
> @@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd[0] = open_pmu(config);
> + fd[0] = open_pmu(gem_fd, config);
>
> /*
> * Second PMU client which is initialized after the first one,
> * and exists before it, should not affect accounting as reported
> * in the first client.
> */
> - fd[1] = open_pmu(config);
> + fd[1] = open_pmu(gem_fd, config);
>
> spin = spin_sync(gem_fd, 0, e);
>
> @@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
> * - cpu != 0 is not supported since i915 PMU only allows running on one cpu
> * and that is normally CPU0.
> */
> -static void invalid_init(void)
> +static void invalid_init(int i915)
> {
> struct perf_event_attr attr;
>
> @@ -1093,7 +1098,7 @@ static void invalid_init(void)
> do { \
> memset(&attr, 0, sizeof (attr)); \
> attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
> - attr.type = i915_type_id(); \
> + attr.type = i915_perf_type_id(i915); \
> igt_assert(attr.type != 0); \
> errno = 0; \
> } while(0)
> @@ -1112,11 +1117,11 @@ do { \
> igt_assert_eq(errno, EINVAL);
> }
>
> -static void init_other(unsigned int i, bool valid)
> +static void init_other(int i915, unsigned int i, bool valid)
> {
> int fd;
>
> - fd = perf_i915_open(__I915_PMU_OTHER(i));
> + fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
> igt_require(!(fd < 0 && errno == ENODEV));
> if (valid) {
> igt_assert(fd >= 0);
> @@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
> close(fd);
> }
>
> -static void read_other(unsigned int i, bool valid)
> +static void read_other(int i915, unsigned int i, bool valid)
> {
> int fd;
>
> - fd = perf_i915_open(__I915_PMU_OTHER(i));
> + fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
> igt_require(!(fd < 0 && errno == ENODEV));
> if (valid) {
> igt_assert(fd >= 0);
> @@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
>
> igt_require(cpu0_hotplug_support());
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
> + fd = open_pmu(gem_fd,
> + I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
>
> /*
> * Create two spinners so test can ensure shorter gaps in engine
> @@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_INTERRUPTS);
> + fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
>
> /* Queue spinning batches. */
> for (int i = 0; i < target; i++) {
> @@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_INTERRUPTS);
> + fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
>
> /* Queue spinning batches. */
> for (int i = 0; i < target; i++)
> @@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
> igt_require(max_freq > min_freq);
> igt_require(boost_freq > min_freq);
>
> - fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
> - open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
> + fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
> + open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
>
> /*
> * Set GPU to min frequency and read PMU counters.
> @@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
>
> /* While parked, our convention is to report the GPU at 0Hz */
>
> - fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
> - open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
> + fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
> + open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
>
> gem_quiescent_gpu(gem_fd); /* Be idle! */
> measured_usleep(2000); /* Wait for timers to cease */
> @@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_RC6_RESIDENCY);
> + fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
>
> if (flags & TEST_RUNTIME_PM) {
> drmModeRes *res;
> @@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
> usleep(500e3);
>
> /* Enable the PMU. */
> - fd = open_pmu(config);
> + fd = open_pmu(gem_fd, config);
>
> /* Stop load and close the PMU. */
> igt_stop_helper(&engine_load);
> @@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
> igt_spin_free(gem_fd, spin);
> }
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> /* Let the child run. */
> read(link[0], &expected, sizeof(expected));
> @@ -1835,7 +1841,7 @@ igt_main
> fd = drm_open_driver_master(DRIVER_INTEL);
>
> igt_require_gem(fd);
> - igt_require(i915_type_id() > 0);
> + igt_require(i915_perf_type_id(fd) > 0);
>
> __for_each_physical_engine(fd, e)
> num_engines++;
> @@ -1845,7 +1851,7 @@ igt_main
> * Test invalid access via perf API is rejected.
> */
> igt_subtest("invalid-init")
> - invalid_init();
> + invalid_init(fd);
>
> __for_each_physical_engine(fd, e) {
> const unsigned int pct[] = { 2, 50, 98 };
> @@ -1996,10 +2002,10 @@ igt_main
> */
> for (i = 0; i < num_other_metrics + 1; i++) {
> igt_subtest_f("other-init-%u", i)
> - init_other(i, i < num_other_metrics);
> + init_other(fd, i, i < num_other_metrics);
>
> igt_subtest_f("other-read-%u", i)
> - read_other(i, i < num_other_metrics);
> + read_other(fd, i, i < num_other_metrics);
> }
>
> /**
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index cc8db7c53..8197482dd 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
> ({ \
> int fd__; \
> \
> - fd__ = perf_i915_open_group((pmu)->config, (fd)); \
> + fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
> if (fd__ >= 0) { \
> if ((fd) == -1) \
> (fd) = fd__; \
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
@ 2020-01-03 17:41 Chris Wilson
2020-01-03 21:20 ` Fosha, Robert M
0 siblings, 1 reply; 16+ messages in thread
From: Chris Wilson @ 2020-01-03 17:41 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Since with multiple devices, we may have multiple different perf_pmu
each with their own type, we want to find the right one for the job.
The tests are run with a specific fd, from which we can extract the
appropriate bus-id and find the associated perf-type. The performance
monitoring tools are a little more general and not yet ready to probe
all device or bind to one in particular, so we just assume the default
igfx for the time being.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
benchmarks/gem_wsim.c | 4 +-
lib/igt_perf.c | 66 +++++++++++++++++++++++---
lib/igt_perf.h | 13 ++++--
overlay/gem-interrupts.c | 2 +-
overlay/gpu-freq.c | 4 +-
overlay/gpu-top.c | 12 ++---
overlay/rc6.c | 2 +-
tests/i915/gem_ctx_freq.c | 2 +-
tests/i915/gem_ctx_sseu.c | 2 +-
tests/i915/gem_exec_balancer.c | 18 +++++---
tests/perf_pmu.c | 84 ++++++++++++++++++----------------
tools/intel_gpu_top.c | 2 +-
12 files changed, 141 insertions(+), 70 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 6305e0d7a..9156fdc90 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
for (d = &engines[0]; d->id != VCS; d++) {
int pfd;
- pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
- d->inst),
+ pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ d->inst),
bb->fd);
if (pfd < 0) {
if (d->id != VCS2)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index e3dec2cc2..4922a2df7 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -4,17 +4,59 @@
#include <stdlib.h>
#include <string.h>
#include <errno.h>
+#include <sys/ioctl.h>
#include <sys/sysinfo.h>
#include "igt_perf.h"
-uint64_t i915_type_id(void)
+const char *i915_perf_device(int i915, char *buf, int buflen)
+{
+ drm_unique_t u = {
+ .unique = buf + 1,
+ .unique_len = buflen - 1,
+ };
+ drm_set_version_t sv = {
+ .drm_di_major = 1,
+ .drm_di_minor = 4,
+ .drm_dd_major = -1, /* Don't care */
+ .drm_dd_minor = -1, /* Don't care */
+ };
+
+ if (ioctl(i915, DRM_IOCTL_SET_VERSION, &sv))
+ return "i915";
+
+ memset(buf, 0, buflen);
+ ioctl(i915, DRM_IOCTL_GET_UNIQUE, &u);
+
+ if (u.unique_len >= buflen)
+ return NULL;
+
+ if (strncmp(buf + 1, "pci:", 4))
+ return NULL;
+
+ if (strcmp(buf + 1, "pci:0000:00:02.0") == 0)
+ return "i915";
+
+ return memcpy(buf, "i915-", strlen("i915-"));
+}
+
+uint64_t i915_perf_type_id(int i915)
+{
+ char buf[80];
+
+ return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
+}
+
+uint64_t igt_perf_type_id(const char *device)
{
char buf[64];
ssize_t ret;
int fd;
- fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
+ snprintf(buf, sizeof(buf),
+ "/sys/bus/event_source/devices/%s/type", device);
+
+ fd = open(buf, O_RDONLY);
if (fd < 0)
return 0;
@@ -52,15 +94,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
return ret;
}
-int perf_i915_open(uint64_t config)
+int perf_igfx_open(uint64_t config)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
+
+int perf_igfx_open_group(uint64_t config, int group)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, group,
+ PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
+}
+
+int perf_i915_open(int i915, uint64_t config)
{
- return _perf_open(i915_type_id(), config, -1,
+ return _perf_open(i915_perf_type_id(i915), config, -1,
PERF_FORMAT_TOTAL_TIME_ENABLED);
}
-int perf_i915_open_group(uint64_t config, int group)
+int perf_i915_open_group(int i915, uint64_t config, int group)
{
- return _perf_open(i915_type_id(), config, group,
+ return _perf_open(i915_perf_type_id(i915), config, group,
PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index e00718f47..a8328c70c 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
}
-uint64_t i915_type_id(void);
-int perf_i915_open(uint64_t config);
-int perf_i915_open_group(uint64_t config, int group);
+uint64_t igt_perf_type_id(const char *device);
int igt_perf_open(uint64_t type, uint64_t config);
int igt_perf_open_group(uint64_t type, uint64_t config, int group);
+const char *i915_perf_device(int i915, char *buf, int buflen);
+uint64_t i915_perf_type_id(int i915);
+
+int perf_igfx_open(uint64_t config);
+int perf_igfx_open_group(uint64_t config, int group);
+
+int perf_i915_open(int i915, uint64_t config);
+int perf_i915_open_group(int i915, uint64_t config, int group);
+
#endif /* I915_PERF_H */
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index 0233fbb05..be73b6931 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
{
memset(irqs, 0, sizeof(*irqs));
- irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
+ irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
if (irqs->fd < 0 && interrupts_read() < 0)
irqs->error = ENODEV;
diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
index 0d8032592..b73157d39 100644
--- a/overlay/gpu-freq.c
+++ b/overlay/gpu-freq.c
@@ -37,8 +37,8 @@ static int perf_open(void)
{
int fd;
- fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
- if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
+ fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
+ if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
close(fd);
fd = -1;
}
diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 6cec2e943..32123abdd 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
d = &engines[0];
- gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
+ gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
-1);
if (gt->fd < 0)
return -1;
- if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
gt->fd) >= 0)
gt->have_wait = 1;
- if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
gt->fd) >= 0)
gt->have_sema = 1;
@@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
gt->num_rings = 1;
for (d++; d->name; d++) {
- if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
d->inst),
gt->fd) < 0)
continue;
if (gt->have_wait &&
- perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
d->inst),
gt->fd) < 0)
return -1;
if (gt->have_sema &&
- perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
d->inst),
gt->fd) < 0)
return -1;
diff --git a/overlay/rc6.c b/overlay/rc6.c
index b5286f0cf..69f95f288 100644
--- a/overlay/rc6.c
+++ b/overlay/rc6.c
@@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
{
memset(rc6, 0, sizeof(*rc6));
- rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
+ rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
if (rc6->fd < 0) {
struct stat st;
if (stat("/sys/class/drm/card0/power", &st) < 0)
diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
index 89f3d11ef..5d2d3ec31 100644
--- a/tests/i915/gem_ctx_freq.c
+++ b/tests/i915/gem_ctx_freq.c
@@ -136,7 +136,7 @@ static void sysfs_range(int i915)
triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
- pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+ pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
igt_require(pmu >= 0);
for (int outer = 0; outer <= 2*N_STEPS; outer++) {
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
index 48e4411c8..38dc584bc 100644
--- a/tests/i915/gem_ctx_sseu.c
+++ b/tests/i915/gem_ctx_sseu.c
@@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
static bool has_engine(int fd, unsigned int class, unsigned int instance)
{
- int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
if (pmu >= 0)
close(pmu);
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index f4909a978..cebcc39c7 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
{
int fd;
- fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
if (fd != -1) {
close(fd);
return true;
@@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
}
}
-static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
+static int
+add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
{
- return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
+ return perf_i915_open_group(i915,
+ I915_PMU_ENGINE_BUSY(ci->engine_class,
ci->engine_instance),
pmu);
}
@@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
double load;
int pmu;
- pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
+ pmu = perf_i915_open(i915,
+ I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
ci[idx].engine_instance));
spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
@@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
pmu[0] = -1;
for (int i = 0; i < limit; i++)
- pmu[i] = add_pmu(pmu[0], &siblings[i]);
- pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
+ pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
+ pmu[limit] = add_pmu(i915,
+ pmu[0], &master_engines[bond]);
igt_assert(siblings[bond].engine_class !=
master_engines[bond].engine_class);
@@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
for (unsigned int n = 0; n < count; n++) {
uint32_t ctx;
- pmu[n] = add_pmu(pmu[0], &ci[n]);
+ pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
if (flags & PULSE) {
struct drm_i915_gem_execbuffer2 eb = {
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index e1bbf2410..3e179daef 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
const double tolerance = 0.05f;
const unsigned long batch_duration_ns = 500e6;
-static int open_pmu(uint64_t config)
+static int open_pmu(int i915, uint64_t config)
{
int fd;
- fd = perf_i915_open(config);
+ fd = perf_i915_open(i915, config);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
return fd;
}
-static int open_group(uint64_t config, int group)
+static int open_group(int i915, uint64_t config, int group)
{
int fd;
- fd = perf_i915_open_group(config, group);
+ fd = perf_i915_open_group(i915, config, group);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
@@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
bool exists;
errno = 0;
- fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
+ fd = perf_i915_open(gem_fd,
+ __I915_PMU_ENGINE(e->class, e->instance, sample));
if (fd < 0)
err = errno;
@@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val;
int fd;
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
spin = __spin_sync(gem_fd, 0, e);
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
* Open PMU as fast as possible after the second spin batch in attempt
* to be faster than the driver handling lite-restore.
*/
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
if (e->class == e_->class && e->instance == e_->instance)
busy_idx = i;
- fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
+ fd[i++] = open_group(gem_fd,
+ I915_PMU_ENGINE_BUSY(e_->class,
e_->instance),
fd[0]);
}
@@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val[2][2];
int fd;
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
* to expected time spent in semaphore wait state.
*/
- fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -817,8 +820,9 @@ sema_busy(int gem_fd,
igt_require(gem_scheduler_has_semaphores(gem_fd));
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
__for_each_physical_engine(gem_fd, signal) {
if (e->class == signal->class &&
@@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
data.pipe = p;
prepare_crtc(&data, gem_fd, output);
- fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_WAIT(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
gem_quiescent_gpu(gem_fd);
- fd[0] = open_pmu(config);
+ fd[0] = open_pmu(gem_fd, config);
/*
* Second PMU client which is initialized after the first one,
* and exists before it, should not affect accounting as reported
* in the first client.
*/
- fd[1] = open_pmu(config);
+ fd[1] = open_pmu(gem_fd, config);
spin = spin_sync(gem_fd, 0, e);
@@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
* - cpu != 0 is not supported since i915 PMU only allows running on one cpu
* and that is normally CPU0.
*/
-static void invalid_init(void)
+static void invalid_init(int i915)
{
struct perf_event_attr attr;
@@ -1093,7 +1098,7 @@ static void invalid_init(void)
do { \
memset(&attr, 0, sizeof (attr)); \
attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
- attr.type = i915_type_id(); \
+ attr.type = i915_perf_type_id(i915); \
igt_assert(attr.type != 0); \
errno = 0; \
} while(0)
@@ -1112,11 +1117,11 @@ do { \
igt_assert_eq(errno, EINVAL);
}
-static void init_other(unsigned int i, bool valid)
+static void init_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
close(fd);
}
-static void read_other(unsigned int i, bool valid)
+static void read_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
igt_require(cpu0_hotplug_support());
- fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
/*
* Create two spinners so test can ensure shorter gaps in engine
@@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++) {
@@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++)
@@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
igt_require(max_freq > min_freq);
igt_require(boost_freq > min_freq);
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
/*
* Set GPU to min frequency and read PMU counters.
@@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
/* While parked, our convention is to report the GPU at 0Hz */
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
gem_quiescent_gpu(gem_fd); /* Be idle! */
measured_usleep(2000); /* Wait for timers to cease */
@@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_RC6_RESIDENCY);
+ fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
if (flags & TEST_RUNTIME_PM) {
drmModeRes *res;
@@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
usleep(500e3);
/* Enable the PMU. */
- fd = open_pmu(config);
+ fd = open_pmu(gem_fd, config);
/* Stop load and close the PMU. */
igt_stop_helper(&engine_load);
@@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
igt_spin_free(gem_fd, spin);
}
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
/* Let the child run. */
read(link[0], &expected, sizeof(expected));
@@ -1835,7 +1841,7 @@ igt_main
fd = drm_open_driver_master(DRIVER_INTEL);
igt_require_gem(fd);
- igt_require(i915_type_id() > 0);
+ igt_require(i915_perf_type_id(fd) > 0);
__for_each_physical_engine(fd, e)
num_engines++;
@@ -1845,7 +1851,7 @@ igt_main
* Test invalid access via perf API is rejected.
*/
igt_subtest("invalid-init")
- invalid_init();
+ invalid_init(fd);
__for_each_physical_engine(fd, e) {
const unsigned int pct[] = { 2, 50, 98 };
@@ -1996,10 +2002,10 @@ igt_main
*/
for (i = 0; i < num_other_metrics + 1; i++) {
igt_subtest_f("other-init-%u", i)
- init_other(i, i < num_other_metrics);
+ init_other(fd, i, i < num_other_metrics);
igt_subtest_f("other-read-%u", i)
- read_other(i, i < num_other_metrics);
+ read_other(fd, i, i < num_other_metrics);
}
/**
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index cc8db7c53..8197482dd 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
({ \
int fd__; \
\
- fd__ = perf_i915_open_group((pmu)->config, (fd)); \
+ fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
if (fd__ >= 0) { \
if ((fd) == -1) \
(fd) = fd__; \
--
2.25.0.rc0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-01-08 22:28 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-04 15:37 [Intel-gfx] [PATCH i-g-t v2] i915/perf: Find the associated perf-type for a particular device Chris Wilson
2020-01-04 15:37 ` [igt-dev] " Chris Wilson
2020-01-04 17:00 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/perf: Find the associated perf-type for a particular device (rev2) Patchwork
2020-01-04 20:46 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2020-01-05 1:06 ` [Intel-gfx] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device Chris Wilson
2020-01-05 1:06 ` [igt-dev] " Chris Wilson
2020-01-07 9:53 ` [Intel-gfx] " Tvrtko Ursulin
2020-01-07 9:53 ` Tvrtko Ursulin
2020-01-07 10:32 ` [Intel-gfx] " Chris Wilson
2020-01-07 10:32 ` Chris Wilson
2020-01-08 22:19 ` [Intel-gfx] " Fosha, Robert M
2020-01-08 22:19 ` Fosha, Robert M
2020-01-05 1:40 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/perf: Find the associated perf-type for a particular device (rev3) Patchwork
2020-01-05 3:04 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-01-03 17:41 [Intel-gfx] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device Chris Wilson
2020-01-03 21:20 ` Fosha, Robert M
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.