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From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Igor Mammedov <imammedo@redhat.com>, Tao Xu <tao3.xu@intel.com>,
	Markus Armbruster <armbru@redhat.com>,
	Liu Jingqi <jingqi.liu@intel.com>
Subject: [PULL v3 15/32] hmat acpi: Build System Locality Latency and Bandwidth Information Structure(s)
Date: Sun, 5 Jan 2020 07:58:35 -0500	[thread overview]
Message-ID: <20200105125622.27231-16-mst@redhat.com> (raw)
In-Reply-To: <20200105125622.27231-1-mst@redhat.com>

From: Liu Jingqi <jingqi.liu@intel.com>

This structure describes the memory access latency and bandwidth
information from various memory access initiator proximity domains.
The latency and bandwidth numbers represented in this structure
correspond to rated latency and bandwidth for the platform.
The software could use this information as hint for optimization.

Acked-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20191213011929.2520-6-tao3.xu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/acpi/hmat.c | 104 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 103 insertions(+), 1 deletion(-)

diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
index 9ff79308a4..4635d45dee 100644
--- a/hw/acpi/hmat.c
+++ b/hw/acpi/hmat.c
@@ -25,6 +25,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "sysemu/numa.h"
 #include "hw/acpi/hmat.h"
 
@@ -67,11 +68,89 @@ static void build_hmat_mpda(GArray *table_data, uint16_t flags,
     build_append_int_noprefix(table_data, 0, 8);
 }
 
+/*
+ * ACPI 6.3: 5.2.27.4 System Locality Latency and Bandwidth Information
+ * Structure: Table 5-146
+ */
+static void build_hmat_lb(GArray *table_data, HMAT_LB_Info *hmat_lb,
+                          uint32_t num_initiator, uint32_t num_target,
+                          uint32_t *initiator_list)
+{
+    int i, index;
+    HMAT_LB_Data *lb_data;
+    uint16_t *entry_list;
+    uint32_t base;
+    /* Length in bytes for entire structure */
+    uint32_t lb_length
+        = 32 /* Table length upto and including Entry Base Unit */
+        + 4 * num_initiator /* Initiator Proximity Domain List */
+        + 4 * num_target /* Target Proximity Domain List */
+        + 2 * num_initiator * num_target; /* Latency or Bandwidth Entries */
+
+    /* Type */
+    build_append_int_noprefix(table_data, 1, 2);
+    /* Reserved */
+    build_append_int_noprefix(table_data, 0, 2);
+    /* Length */
+    build_append_int_noprefix(table_data, lb_length, 4);
+    /* Flags: Bits [3:0] Memory Hierarchy, Bits[7:4] Reserved */
+    assert(!(hmat_lb->hierarchy >> 4));
+    build_append_int_noprefix(table_data, hmat_lb->hierarchy, 1);
+    /* Data Type */
+    build_append_int_noprefix(table_data, hmat_lb->data_type, 1);
+    /* Reserved */
+    build_append_int_noprefix(table_data, 0, 2);
+    /* Number of Initiator Proximity Domains (s) */
+    build_append_int_noprefix(table_data, num_initiator, 4);
+    /* Number of Target Proximity Domains (t) */
+    build_append_int_noprefix(table_data, num_target, 4);
+    /* Reserved */
+    build_append_int_noprefix(table_data, 0, 4);
+
+    /* Entry Base Unit */
+    if (hmat_lb->data_type <= HMAT_LB_DATA_WRITE_LATENCY) {
+        /* Convert latency base from nanoseconds to picosecond */
+        base = hmat_lb->base * 1000;
+    } else {
+        /* Convert bandwidth base from Byte to Megabyte */
+        base = hmat_lb->base / MiB;
+    }
+    build_append_int_noprefix(table_data, base, 8);
+
+    /* Initiator Proximity Domain List */
+    for (i = 0; i < num_initiator; i++) {
+        build_append_int_noprefix(table_data, initiator_list[i], 4);
+    }
+
+    /* Target Proximity Domain List */
+    for (i = 0; i < num_target; i++) {
+        build_append_int_noprefix(table_data, i, 4);
+    }
+
+    /* Latency or Bandwidth Entries */
+    entry_list = g_malloc0(num_initiator * num_target * sizeof(uint16_t));
+    for (i = 0; i < hmat_lb->list->len; i++) {
+        lb_data = &g_array_index(hmat_lb->list, HMAT_LB_Data, i);
+        index = lb_data->initiator * num_target + lb_data->target;
+
+        entry_list[index] = (uint16_t)(lb_data->data / hmat_lb->base);
+    }
+
+    for (i = 0; i < num_initiator * num_target; i++) {
+        build_append_int_noprefix(table_data, entry_list[i], 2);
+    }
+
+    g_free(entry_list);
+}
+
 /* Build HMAT sub table structures */
 static void hmat_build_table_structs(GArray *table_data, NumaState *numa_state)
 {
     uint16_t flags;
-    int i;
+    uint32_t num_initiator = 0;
+    uint32_t initiator_list[MAX_NODES];
+    int i, hierarchy, type;
+    HMAT_LB_Info *hmat_lb;
 
     for (i = 0; i < numa_state->num_nodes; i++) {
         flags = 0;
@@ -82,6 +161,29 @@ static void hmat_build_table_structs(GArray *table_data, NumaState *numa_state)
 
         build_hmat_mpda(table_data, flags, numa_state->nodes[i].initiator, i);
     }
+
+    for (i = 0; i < numa_state->num_nodes; i++) {
+        if (numa_state->nodes[i].has_cpu) {
+            initiator_list[num_initiator++] = i;
+        }
+    }
+
+    /*
+     * ACPI 6.3: 5.2.27.4 System Locality Latency and Bandwidth Information
+     * Structure: Table 5-146
+     */
+    for (hierarchy = HMAT_LB_MEM_MEMORY;
+         hierarchy <= HMAT_LB_MEM_CACHE_3RD_LEVEL; hierarchy++) {
+        for (type = HMAT_LB_DATA_ACCESS_LATENCY;
+             type <= HMAT_LB_DATA_WRITE_BANDWIDTH; type++) {
+            hmat_lb = numa_state->hmat_lb[hierarchy][type];
+
+            if (hmat_lb && hmat_lb->list->len) {
+                build_hmat_lb(table_data, hmat_lb, num_initiator,
+                              numa_state->num_nodes, initiator_list);
+            }
+        }
+    }
 }
 
 void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_state)
-- 
MST



  parent reply	other threads:[~2020-01-05 13:06 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-05 12:57 [PULL v3 00/32] virtio, pci, pc: fixes, features Michael S. Tsirkin
2020-01-05 12:57 ` [PULL v3 01/32] virtio: add ability to delete vq through a pointer Michael S. Tsirkin
2020-01-05 12:57 ` [PULL v3 02/32] virtio: make virtio_delete_queue idempotent Michael S. Tsirkin
2020-01-05 12:57 ` [PULL v3 03/32] virtio-balloon: fix memory leak while attach virtio-balloon device Michael S. Tsirkin
2020-01-05 12:57 ` [PULL v3 04/32] virtio-serial-bus: fix memory leak while attach virtio-serial-bus Michael S. Tsirkin
2020-01-05 12:57 ` [PULL v3 05/32] virtio-input: convert to new virtio_delete_queue Michael S. Tsirkin
2020-01-05 12:57 ` [PULL v3 06/32] intel_iommu: fix bug to read DMAR_RTADDR_REG Michael S. Tsirkin
2020-01-05 12:57 ` [PULL v3 07/32] virtio: update queue size on guest write Michael S. Tsirkin
2020-01-05 12:57 ` [PULL v3 08/32] virtio-pci: disable vring processing when bus-mastering is disabled Michael S. Tsirkin
2020-01-05 12:58 ` [PULL v3 09/32] Implement backend program convention command for vhost-user-blk Michael S. Tsirkin
2020-01-05 12:58 ` [PULL v3 10/32] virtio: don't enable notifications during polling Michael S. Tsirkin
2020-01-05 12:58 ` [PULL v3 11/32] numa: Extend CLI to provide initiator information for numa nodes Michael S. Tsirkin
2020-01-05 12:58 ` [PULL v3 12/32] numa: Extend CLI to provide memory latency and bandwidth information Michael S. Tsirkin
2020-01-05 12:58 ` [PULL v3 13/32] numa: Extend CLI to provide memory side cache information Michael S. Tsirkin
2020-01-05 12:58 ` [PULL v3 14/32] hmat acpi: Build Memory Proximity Domain Attributes Structure(s) Michael S. Tsirkin
2020-01-05 12:58 ` Michael S. Tsirkin [this message]
2020-01-05 12:58 ` [PULL v3 16/32] hmat acpi: Build Memory Side Cache Information Structure(s) Michael S. Tsirkin
2020-01-05 12:58 ` [PULL v3 17/32] tests/numa: Add case for QMP build HMAT Michael S. Tsirkin
2020-01-05 12:58 ` [PULL v3 18/32] tests/bios-tables-test: add test cases for ACPI HMAT Michael S. Tsirkin
2020-01-05 12:58 ` [PULL v3 19/32] ACPI: add expected files for HMAT tests (acpihmat) Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 20/32] virtio-mmio: Clear v2 transport state on soft reset Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 21/32] hw/pci/pci_host: Remove redundant PCI_DPRINTF() Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 22/32] hw/pci/pci_host: Let pci_data_[read/write] use unsigned 'size' argument Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 23/32] vhost-user: add VHOST_USER_RESET_DEVICE to reset devices Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 24/32] vhost-user-scsi: reset the device if supported Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 25/32] hw: fix using 4.2 compat in 5.0 machine types for i440fx/q35 Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 26/32] virtio: make seg_max virtqueue size dependent Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 27/32] tests: add virtio-scsi and virtio-blk seg_max_adjust test Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 28/32] virtio-mmio: update queue size on guest write Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 29/32] virtio: reset region cache when on queue deletion Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 30/32] virtio-net: delete also control queue when TX/RX deleted Michael S. Tsirkin
2020-01-05 12:59 ` [PULL v3 31/32] intel_iommu: a fix to vtd_find_as_from_bus_num() Michael S. Tsirkin
2020-01-05 13:00 ` [PULL v3 32/32] intel_iommu: add present bit check for pasid table entries Michael S. Tsirkin
2020-01-06 16:48 ` [PULL v3 00/32] virtio, pci, pc: fixes, features Peter Maydell
2020-01-06 17:05   ` Michael S. Tsirkin
2020-01-07 16:29 Michael S. Tsirkin
2020-01-07 16:30 ` [PULL v3 15/32] hmat acpi: Build System Locality Latency and Bandwidth Information Structure(s) Michael S. Tsirkin

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