* [PATCH v2] PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30
@ 2020-01-07 8:14 Marcel Ziswiler
2020-01-07 10:19 ` Andrew Murray
2020-01-10 15:55 ` Lorenzo Pieralisi
0 siblings, 2 replies; 3+ messages in thread
From: Marcel Ziswiler @ 2020-01-07 8:14 UTC (permalink / raw)
To: Thierry Reding, linux-kernel
Cc: linux-tegra, linux-pci, Manikanta Maddireddy, Thierry Reding,
Marcel Ziswiler, Andrew Murray, Bjorn Helgaas, Jonathan Hunter,
Lorenzo Pieralisi
Fix AFI_PEX2_CTRL reg offset for Tegra30 by moving it from the Tegra20
SoC struct where it erroneously got added. This fixes the AFI_PEX2_CTRL
reg offset being uninitialised subsequently failing to bring up the
third PCIe port.
Fixes: adb2653b3d2e ("PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct")
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- Fix recipient list concerning CC: and To: lines as suggested by
Thierry.
- Fix subject line and commit message to adhere to standard formatting
rules as suggested by Thierry.
- Add Thierry's Acked-by tag.
- Add standard Fixes tag as suggested by Andrew.
drivers/pci/controller/pci-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 090b632965e2..ac93f5a0398e 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -2499,7 +2499,6 @@ static const struct tegra_pcie_soc tegra20_pcie = {
.num_ports = 2,
.ports = tegra20_pcie_ports,
.msi_base_shift = 0,
- .afi_pex2_ctrl = 0x128,
.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
.pads_refclk_cfg0 = 0xfa5cfa5c,
@@ -2528,6 +2527,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
.num_ports = 3,
.ports = tegra30_pcie_ports,
.msi_base_shift = 8,
+ .afi_pex2_ctrl = 0x128,
.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
.pads_refclk_cfg0 = 0xfa5cfa5c,
--
2.24.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30
2020-01-07 8:14 [PATCH v2] PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30 Marcel Ziswiler
@ 2020-01-07 10:19 ` Andrew Murray
2020-01-10 15:55 ` Lorenzo Pieralisi
1 sibling, 0 replies; 3+ messages in thread
From: Andrew Murray @ 2020-01-07 10:19 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: Thierry Reding, linux-kernel, linux-tegra, linux-pci,
Manikanta Maddireddy, Thierry Reding, Bjorn Helgaas,
Jonathan Hunter, Lorenzo Pieralisi
On Tue, Jan 07, 2020 at 09:14:02AM +0100, Marcel Ziswiler wrote:
> Fix AFI_PEX2_CTRL reg offset for Tegra30 by moving it from the Tegra20
> SoC struct where it erroneously got added. This fixes the AFI_PEX2_CTRL
> reg offset being uninitialised subsequently failing to bring up the
> third PCIe port.
>
> Fixes: adb2653b3d2e ("PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct")
>
> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
>
> ---
>
> Changes in v2:
> - Fix recipient list concerning CC: and To: lines as suggested by
> Thierry.
> - Fix subject line and commit message to adhere to standard formatting
> rules as suggested by Thierry.
> - Add Thierry's Acked-by tag.
> - Add standard Fixes tag as suggested by Andrew.
>
> drivers/pci/controller/pci-tegra.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index 090b632965e2..ac93f5a0398e 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -2499,7 +2499,6 @@ static const struct tegra_pcie_soc tegra20_pcie = {
> .num_ports = 2,
> .ports = tegra20_pcie_ports,
> .msi_base_shift = 0,
> - .afi_pex2_ctrl = 0x128,
> .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
> .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
> .pads_refclk_cfg0 = 0xfa5cfa5c,
> @@ -2528,6 +2527,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
> .num_ports = 3,
> .ports = tegra30_pcie_ports,
> .msi_base_shift = 8,
> + .afi_pex2_ctrl = 0x128,
> .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
> .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
> .pads_refclk_cfg0 = 0xfa5cfa5c,
> --
> 2.24.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30
2020-01-07 8:14 [PATCH v2] PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30 Marcel Ziswiler
2020-01-07 10:19 ` Andrew Murray
@ 2020-01-10 15:55 ` Lorenzo Pieralisi
1 sibling, 0 replies; 3+ messages in thread
From: Lorenzo Pieralisi @ 2020-01-10 15:55 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: Thierry Reding, linux-kernel, linux-tegra, linux-pci,
Manikanta Maddireddy, Thierry Reding, Andrew Murray,
Bjorn Helgaas, Jonathan Hunter
On Tue, Jan 07, 2020 at 09:14:02AM +0100, Marcel Ziswiler wrote:
> Fix AFI_PEX2_CTRL reg offset for Tegra30 by moving it from the Tegra20
> SoC struct where it erroneously got added. This fixes the AFI_PEX2_CTRL
> reg offset being uninitialised subsequently failing to bring up the
> third PCIe port.
>
> Fixes: adb2653b3d2e ("PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct")
>
> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
>
> ---
>
> Changes in v2:
> - Fix recipient list concerning CC: and To: lines as suggested by
> Thierry.
> - Fix subject line and commit message to adhere to standard formatting
> rules as suggested by Thierry.
> - Add Thierry's Acked-by tag.
> - Add standard Fixes tag as suggested by Andrew.
>
> drivers/pci/controller/pci-tegra.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to pci/tegra, thanks.
Lorenzo
> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index 090b632965e2..ac93f5a0398e 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -2499,7 +2499,6 @@ static const struct tegra_pcie_soc tegra20_pcie = {
> .num_ports = 2,
> .ports = tegra20_pcie_ports,
> .msi_base_shift = 0,
> - .afi_pex2_ctrl = 0x128,
> .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
> .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
> .pads_refclk_cfg0 = 0xfa5cfa5c,
> @@ -2528,6 +2527,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
> .num_ports = 3,
> .ports = tegra30_pcie_ports,
> .msi_base_shift = 8,
> + .afi_pex2_ctrl = 0x128,
> .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
> .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
> .pads_refclk_cfg0 = 0xfa5cfa5c,
> --
> 2.24.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-01-10 15:55 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2020-01-07 8:14 [PATCH v2] PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30 Marcel Ziswiler
2020-01-07 10:19 ` Andrew Murray
2020-01-10 15:55 ` Lorenzo Pieralisi
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