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[79.183.34.164]) by smtp.gmail.com with ESMTPSA id 201sm45486qkf.10.2020.01.07.08.30.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2020 08:30:47 -0800 (PST) Date: Tue, 7 Jan 2020 11:30:43 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Subject: [PULL v3 16/32] hmat acpi: Build Memory Side Cache Information Structure(s) Message-ID: <20200107162850.411448-17-mst@redhat.com> References: <20200107162850.411448-1-mst@redhat.com> MIME-Version: 1.0 In-Reply-To: <20200107162850.411448-1-mst@redhat.com> X-Mailer: git-send-email 2.24.1.751.gd10ce2899c X-Mutt-Fcc: =sent X-MC-Unique: aqa2ZuW6OrejtwSoq3UWzw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Liu Jingqi , Tao Xu , Markus Armbruster , Daniel Black , Jonathan Cameron , Igor Mammedov Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Liu Jingqi This structure describes memory side cache information for memory proximity domains if the memory side cache is present and the physical device forms the memory side cache. The software could use this information to effectively place the data in memory to maximize the performance of the system memory that use the memory side cache. Acked-by: Markus Armbruster Reviewed-by: Igor Mammedov Reviewed-by: Daniel Black Reviewed-by: Jonathan Cameron Signed-off-by: Liu Jingqi Signed-off-by: Tao Xu Message-Id: <20191213011929.2520-7-tao3.xu@intel.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/acpi/hmat.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c index 4635d45dee..7c24bb5371 100644 --- a/hw/acpi/hmat.c +++ b/hw/acpi/hmat.c @@ -143,14 +143,62 @@ static void build_hmat_lb(GArray *table_data, HMAT_LB= _Info *hmat_lb, g_free(entry_list); } =20 +/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-147= */ +static void build_hmat_cache(GArray *table_data, uint8_t total_levels, + NumaHmatCacheOptions *hmat_cache) +{ + /* + * Cache Attributes: Bits [3:0] =E2=80=93 Total Cache Levels + * for this Memory Proximity Domain + */ + uint32_t cache_attr =3D total_levels; + + /* Bits [7:4] : Cache Level described in this structure */ + cache_attr |=3D (uint32_t) hmat_cache->level << 4; + + /* Bits [11:8] - Cache Associativity */ + cache_attr |=3D (uint32_t) hmat_cache->associativity << 8; + + /* Bits [15:12] - Write Policy */ + cache_attr |=3D (uint32_t) hmat_cache->policy << 12; + + /* Bits [31:16] - Cache Line size in bytes */ + cache_attr |=3D (uint32_t) hmat_cache->line << 16; + + /* Type */ + build_append_int_noprefix(table_data, 2, 2); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 2); + /* Length */ + build_append_int_noprefix(table_data, 32, 4); + /* Proximity Domain for the Memory */ + build_append_int_noprefix(table_data, hmat_cache->node_id, 4); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); + /* Memory Side Cache Size */ + build_append_int_noprefix(table_data, hmat_cache->size, 8); + /* Cache Attributes */ + build_append_int_noprefix(table_data, cache_attr, 4); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 2); + /* + * Number of SMBIOS handles (n) + * Linux kernel uses Memory Side Cache Information Structure + * without SMBIOS entries for now, so set Number of SMBIOS handles + * as 0. + */ + build_append_int_noprefix(table_data, 0, 2); +} + /* Build HMAT sub table structures */ static void hmat_build_table_structs(GArray *table_data, NumaState *numa_s= tate) { uint16_t flags; uint32_t num_initiator =3D 0; uint32_t initiator_list[MAX_NODES]; - int i, hierarchy, type; + int i, hierarchy, type, cache_level, total_levels; HMAT_LB_Info *hmat_lb; + NumaHmatCacheOptions *hmat_cache; =20 for (i =3D 0; i < numa_state->num_nodes; i++) { flags =3D 0; @@ -184,6 +232,25 @@ static void hmat_build_table_structs(GArray *table_dat= a, NumaState *numa_state) } } } + + /* + * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: + * Table 5-147 + */ + for (i =3D 0; i < numa_state->num_nodes; i++) { + total_levels =3D 0; + for (cache_level =3D 1; cache_level < HMAT_LB_LEVELS; cache_level+= +) { + if (numa_state->hmat_cache[i][cache_level]) { + total_levels++; + } + } + for (cache_level =3D 0; cache_level <=3D total_levels; cache_level= ++) { + hmat_cache =3D numa_state->hmat_cache[i][cache_level]; + if (hmat_cache) { + build_hmat_cache(table_data, total_levels, hmat_cache); + } + } + } } =20 void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_st= ate) --=20 MST