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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: lvivier@redhat.com, qemu-devel@nongnu.org, groug@kaod.org,
	qemu-ppc@nongnu.org, clg@kaod.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [PULL 18/26] ppc/pnv: Add an "nr-threads" property to the base chip class
Date: Wed,  8 Jan 2020 16:23:04 +1100	[thread overview]
Message-ID: <20200108052312.238710-19-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20200108052312.238710-1-david@gibson.dropbear.id.au>

From: Greg Kurz <groug@kaod.org>

Set it at chip creation and forward it to the cores. This allows to drop
a call to qdev_get_machine().

Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20200106145645.4539-7-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/ppc/pnv.c         | 8 +++++---
 include/hw/ppc/pnv.h | 1 +
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index ead92d52b2..6a0aa78d53 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -802,6 +802,8 @@ static void pnv_init(MachineState *machine)
                                 &error_fatal);
         object_property_set_int(chip, machine->smp.cores,
                                 "nr-cores", &error_fatal);
+        object_property_set_int(chip, machine->smp.threads,
+                                "nr-threads", &error_fatal);
         /*
          * The POWER8 machine use the XICS interrupt interface.
          * Propagate the XICS fabric to the chip and its controllers.
@@ -1526,7 +1528,6 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
 
 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
 {
-    MachineState *ms = MACHINE(qdev_get_machine());
     Error *error = NULL;
     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
     const char *typename = pnv_chip_core_typename(chip);
@@ -1562,8 +1563,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
         object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
                                   &error_abort);
         chip->cores[i] = pnv_core;
-        object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads",
-                                &error_fatal);
+        object_property_set_int(OBJECT(pnv_core), chip->nr_threads,
+                                "nr-threads", &error_fatal);
         object_property_set_int(OBJECT(pnv_core), core_hwid,
                                 CPU_CORE_PROP_CORE_ID, &error_fatal);
         object_property_set_int(OBJECT(pnv_core),
@@ -1602,6 +1603,7 @@ static Property pnv_chip_properties[] = {
     DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
     DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
     DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
+    DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 56277862dd..4b9012f994 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -48,6 +48,7 @@ typedef struct PnvChip {
     uint64_t     ram_size;
 
     uint32_t     nr_cores;
+    uint32_t     nr_threads;
     uint64_t     cores_mask;
     PnvCore      **cores;
 
-- 
2.24.1



  parent reply	other threads:[~2020-01-08  5:27 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-08  5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
2020-01-08  5:22 ` [PULL 01/26] target/ppc: Remove unused PPC_INPUT_INT defines David Gibson
2020-01-08  5:22 ` [PULL 02/26] target/ppc: Handle AIL=0 in ppc_excp_vector_offset David Gibson
2020-01-08  5:22 ` [PULL 03/26] linux-headers: Update David Gibson
2020-01-08  5:22 ` [PULL 04/26] ppc/spapr: Support reboot of secure pseries guest David Gibson
2020-01-08  5:22 ` [PULL 05/26] ppc/pnv: Modify the powerdown notifier to get the PowerNV machine David Gibson
2020-01-08  5:22 ` [PULL 06/26] mos6522: remove anh register David Gibson
2020-01-08  5:22 ` [PULL 07/26] spapr/xive: Use device_class_set_parent_realize() David Gibson
2020-01-08  5:22 ` [PULL 08/26] ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCG David Gibson
2020-01-08  5:22 ` [PULL 09/26] spapr.c: remove 'out' label in spapr_dt_cas_updates() David Gibson
2020-01-08  5:22 ` [PULL 10/26] ppc440_bamboo.c: remove label from bamboo_load_device_tree() David Gibson
2020-01-08  5:22 ` [PULL 11/26] ppc/pnv: Drop "num-chips" machine property David Gibson
2020-01-08  5:22 ` [PULL 12/26] spapr/xive: remove redundant check in spapr_match_nvt() David Gibson
2020-01-08  5:22 ` [PULL 13/26] ppc/pnv: Introduce a "xics" property alias under the PSI model David Gibson
2020-01-08  5:23 ` [PULL 14/26] ppc/pnv: Introduce a "xics" property under the POWER8 chip David Gibson
2020-01-08  5:23 ` [PULL 15/26] pnv/xive: Use device_class_set_parent_realize() David Gibson
2020-01-08  5:23 ` [PULL 16/26] spapr, pnv, xive: Add a "xive-fabric" link to the XIVE router David Gibson
2020-01-08  5:23 ` [PULL 17/26] xive: Use the XIVE fabric link under " David Gibson
2020-01-08  5:23 ` David Gibson [this message]
2020-01-08  5:23 ` [PULL 19/26] ppc/pnv: Add a "pnor" const link property to the BMC internal simulator David Gibson
2020-01-08  5:23 ` [PULL 20/26] xive: Add a "presenter" link property to the TCTX object David Gibson
2020-01-08  5:23 ` [PULL 21/26] spapr/xive: Deduce the SpaprXive pointer from XiveTCTX::xptr David Gibson
2020-01-08  5:23 ` [PULL 22/26] pnv/xive: Deduce the PnvXive " David Gibson
2020-01-08  5:23 ` [PULL 23/26] pnv/psi: Add device reset hook David Gibson
2020-01-08  5:23 ` [PULL 24/26] pnv/psi: Consolidate some duplicated code in pnv_psi_realize() David Gibson
2020-01-08  5:23 ` [PULL 25/26] ppc/pnv: check return value of blk_pwrite() David Gibson
2020-01-08  5:23 ` [PULL 26/26] ppc/pnv: fix check on return value of blk_getlength() David Gibson
2020-01-10 17:16 ` [PULL 00/26] ppc-for-5.0 queue 20200108 Peter Maydell

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