From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7CC5C00523 for ; Wed, 8 Jan 2020 10:10:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9ACAF2077B for ; Wed, 8 Jan 2020 10:10:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727006AbgAHKK1 (ORCPT ); Wed, 8 Jan 2020 05:10:27 -0500 Received: from foss.arm.com ([217.140.110.172]:41702 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726368AbgAHKK1 (ORCPT ); Wed, 8 Jan 2020 05:10:27 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 935DB1FB; Wed, 8 Jan 2020 02:10:26 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2904B3F6C4; Wed, 8 Jan 2020 02:10:25 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai Cc: Mark Brown , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, Icenowy Zheng , devicetree@vger.kernel.org, Rob Herring , Mark Rutland Subject: [PATCH 0/2] arm64: dts: sun50i: H6: Enable SPI flash Date: Wed, 8 Jan 2020 10:10:04 +0000 Message-Id: <20200108101006.150706-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Even though the SPI controller in the Allwinner H6 SoC is more advanced than in the previous generations (it supports 3-wire and 4-wire mode), the register set stayed backwards-compatible. So we can use the existing driver to use the "normal" SPI mode, for instance to access the SPI flash soldered on the Pine H64 board. These two patches allow this by adding the SPI controller nodes to the DT. The compatible strings include an H6 specific name, so that any future 4-wire enhancements for instance would be automatically usable once the driver learns this new trick. For now we use the H3 fallback name to bind the current driver. This time I tested this actual branch ;-) (on top of sunxi/dt-for-5.6), on a Pine H64, both the internal SPI flash as well with SPI flash connected to the other SPI controller available on the GPIO headers. One thing I noticed: Only SPI0 seems to connect the two extra pins required for 4-wire mode. Does this require some extra DT property or the like? Can we derive this from the number of pins in the pinctrl-0 property? Or will we later introduce a new compatible string to prepend to the current list? Cheers, Andre. Andre Przywara (2): arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes arm64: dts: allwinner: h6: Pine H64: Add SPI flash node .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 13 +++++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 +++++++++++++++++++ 2 files changed, 67 insertions(+) -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Przywara Subject: [PATCH 0/2] arm64: dts: sun50i: H6: Enable SPI flash Date: Wed, 8 Jan 2020 10:10:04 +0000 Message-ID: <20200108101006.150706-1-andre.przywara@arm.com> Reply-To: andre.przywara-5wv7dgnIgG8@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Cc: Mark Brown , linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Icenowy Zheng , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , Mark Rutland To: Maxime Ripard , Chen-Yu Tsai Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , List-Id: linux-spi.vger.kernel.org Even though the SPI controller in the Allwinner H6 SoC is more advanced than in the previous generations (it supports 3-wire and 4-wire mode), the register set stayed backwards-compatible. So we can use the existing driver to use the "normal" SPI mode, for instance to access the SPI flash soldered on the Pine H64 board. These two patches allow this by adding the SPI controller nodes to the DT. The compatible strings include an H6 specific name, so that any future 4-wire enhancements for instance would be automatically usable once the driver learns this new trick. For now we use the H3 fallback name to bind the current driver. This time I tested this actual branch ;-) (on top of sunxi/dt-for-5.6), on a Pine H64, both the internal SPI flash as well with SPI flash connected to the other SPI controller available on the GPIO headers. One thing I noticed: Only SPI0 seems to connect the two extra pins required for 4-wire mode. Does this require some extra DT property or the like? Can we derive this from the number of pins in the pinctrl-0 property? Or will we later introduce a new compatible string to prepend to the current list? Cheers, Andre. Andre Przywara (2): arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes arm64: dts: allwinner: h6: Pine H64: Add SPI flash node .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 13 +++++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 +++++++++++++++++++ 2 files changed, 67 insertions(+) -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B519C00523 for ; Wed, 8 Jan 2020 10:10:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EE2082075D for ; Wed, 8 Jan 2020 10:10:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="AcvBF27C" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EE2082075D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=WJxd+DXLrOjWgmMM38ncYzsyfNJHESVslZEu6Bnzgyo=; b=Acv BF27CmPskC4xKA4b/64oBTYt2pFmzN3WCE5GoEfQZLLlA0Dv7CwM99SZI/vlRGeiumNWm0bEEB7xo wfFeQ1zmtPy+bHb2yOzwb5vWt5V0P5hrvtSxKM+kw86tGvFUPoQN37X1lIgf3OyQzvzKJTv8UMX4u R4Jhhz1Vq9yfknX2ve0PBKVSSB2sYmlxKToRL7B89vlUIIMtbd5Rt/1DmaMKNCshiExj3Y9K32MoV qqpQ/avqrrh9z+ZdE8P8U66N2rV0qxYhE0DL2JKlAgksKu0MHvRoEHTjQsICRZH4lUL1aq/9XE4DK gjeLg1qRefutpqlGaEv2ukSHyoocZtA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ip8IK-00051L-Vv; Wed, 08 Jan 2020 10:10:32 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ip8IH-00050F-N9 for linux-arm-kernel@lists.infradead.org; Wed, 08 Jan 2020 10:10:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 935DB1FB; Wed, 8 Jan 2020 02:10:26 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2904B3F6C4; Wed, 8 Jan 2020 02:10:25 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai Subject: [PATCH 0/2] arm64: dts: sun50i: H6: Enable SPI flash Date: Wed, 8 Jan 2020 10:10:04 +0000 Message-Id: <20200108101006.150706-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200108_021029_798103_A0D8A60A X-CRM114-Status: GOOD ( 12.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Rob Herring , linux-spi@vger.kernel.org, linux-sunxi@googlegroups.com, Mark Brown , Icenowy Zheng , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Even though the SPI controller in the Allwinner H6 SoC is more advanced than in the previous generations (it supports 3-wire and 4-wire mode), the register set stayed backwards-compatible. So we can use the existing driver to use the "normal" SPI mode, for instance to access the SPI flash soldered on the Pine H64 board. These two patches allow this by adding the SPI controller nodes to the DT. The compatible strings include an H6 specific name, so that any future 4-wire enhancements for instance would be automatically usable once the driver learns this new trick. For now we use the H3 fallback name to bind the current driver. This time I tested this actual branch ;-) (on top of sunxi/dt-for-5.6), on a Pine H64, both the internal SPI flash as well with SPI flash connected to the other SPI controller available on the GPIO headers. One thing I noticed: Only SPI0 seems to connect the two extra pins required for 4-wire mode. Does this require some extra DT property or the like? Can we derive this from the number of pins in the pinctrl-0 property? Or will we later introduce a new compatible string to prepend to the current list? Cheers, Andre. Andre Przywara (2): arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes arm64: dts: allwinner: h6: Pine H64: Add SPI flash node .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 13 +++++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 +++++++++++++++++++ 2 files changed, 67 insertions(+) -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel