From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5730BC33C9E for ; Wed, 8 Jan 2020 11:47:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3718620848 for ; Wed, 8 Jan 2020 11:47:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726323AbgAHLrY (ORCPT ); Wed, 8 Jan 2020 06:47:24 -0500 Received: from foss.arm.com ([217.140.110.172]:43260 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726290AbgAHLrY (ORCPT ); Wed, 8 Jan 2020 06:47:24 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EAE4231B; Wed, 8 Jan 2020 03:47:23 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 75C973F703; Wed, 8 Jan 2020 03:47:22 -0800 (PST) Date: Wed, 8 Jan 2020 11:47:06 +0000 From: Andre Przywara To: Emmanuel Vadot Cc: Maxime Ripard , Chen-Yu Tsai , Mark Rutland , devicetree@vger.kernel.org, Rob Herring , linux-spi@vger.kernel.org, linux-sunxi@googlegroups.com, Mark Brown , Icenowy Zheng , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/2] arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes Message-ID: <20200108114706.5f27a9b2@donnerap.cambridge.arm.com> In-Reply-To: <20200108123448.26286186e74f899caaf5ad35@bidouilliste.com> References: <20200108101006.150706-1-andre.przywara@arm.com> <20200108101006.150706-2-andre.przywara@arm.com> <20200108123448.26286186e74f899caaf5ad35@bidouilliste.com> Organization: ARM X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, 8 Jan 2020 12:34:48 +0100 Emmanuel Vadot wrote: Hi Emmanuel, > On Wed, 8 Jan 2020 10:10:05 +0000 > Andre Przywara wrote: > > > The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, > > but with the added capability of 3-wire and 4-wire operation modes. > > For now the driver does not support those, but the SPI registers are > > fully backwards-compatible, just adding bits and registers which were > > formerly reserved. So we can use the existing driver for the "normal" SPI > > modes, for instance to access the SPI NOR flash soldered on the PineH64 > > board. > > We use an H6 specific compatible string in addition to the existing H3 > > string, so when the driver later gains Quad SPI support, it should work > > automatically without any DT changes. > > > > Tested by accessing the SPI flash on a Pine H64 board (SPI0), also > > connecting another SPI flash to the SPI1 header pins. > > > > Signed-off-by: Andre Przywara > > --- > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 ++++++++++++++++++++ > > 1 file changed, 54 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > index 3329283e38ab..40835850893e 100644 > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > @@ -338,6 +338,30 @@ > > bias-pull-up; > > }; > > > > + /omit-if-no-ref/ > > That would prevent users to use an overlay and use those pins, is that > something that we want ? I'm not sure that the space saved by those are > useful. Me neither ;-), but Maxime asked for it before, and it doesn't really hurt. For overlays: if a .dtb is compiled with support for overlays (-@ to generate symbols), this tag is ignored, and the nodes stay in the .dtb, regardless of being referenced or not. Just confirmed by trying this. Cheers, Andre. > > Cheers, > > > + spi0_pins: spi0-pins { > > + pins = "PC0", "PC2", "PC3"; > > + function = "spi0"; > > + }; > > + > > + /omit-if-no-ref/ > > + spi0_cs_pin: spi0-cs-pin { > > + pins = "PC5"; > > + function = "spi0"; > > + }; > > + > > + /omit-if-no-ref/ > > + spi1_pins: spi1-pins { > > + pins = "PH4", "PH5", "PH6"; > > + function = "spi1"; > > + }; > > + > > + /omit-if-no-ref/ > > + spi1_cs_pin: spi1-cs-pin { > > + pins = "PH3"; > > + function = "spi1"; > > + }; > > + > > spdif_tx_pin: spdif-tx-pin { > > pins = "PH7"; > > function = "spdif"; > > @@ -504,6 +528,36 @@ > > #size-cells = <0>; > > }; > > > > + spi0: spi@5010000 { > > + compatible = "allwinner,sun50i-h6-spi", > > + "allwinner,sun8i-h3-spi"; > > + reg = <0x05010000 0x1000>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; > > + clock-names = "ahb", "mod"; > > + dmas = <&dma 22>, <&dma 22>; > > + dma-names = "rx", "tx"; > > + resets = <&ccu RST_BUS_SPI0>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + spi1: spi@5011000 { > > + compatible = "allwinner,sun50i-h6-spi", > > + "allwinner,sun8i-h3-spi"; > > + reg = <0x05011000 0x1000>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; > > + clock-names = "ahb", "mod"; > > + dmas = <&dma 23>, <&dma 23>; > > + dma-names = "rx", "tx"; > > + resets = <&ccu RST_BUS_SPI1>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > emac: ethernet@5020000 { > > compatible = "allwinner,sun50i-h6-emac", > > "allwinner,sun50i-a64-emac"; > > -- > > 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Przywara Subject: Re: [PATCH 1/2] arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes Date: Wed, 8 Jan 2020 11:47:06 +0000 Message-ID: <20200108114706.5f27a9b2@donnerap.cambridge.arm.com> References: <20200108101006.150706-1-andre.przywara@arm.com> <20200108101006.150706-2-andre.przywara@arm.com> <20200108123448.26286186e74f899caaf5ad35@bidouilliste.com> Reply-To: andre.przywara-5wv7dgnIgG8@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Cc: Maxime Ripard , Chen-Yu Tsai , Mark Rutland , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Mark Brown , Icenowy Zheng , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Emmanuel Vadot Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20200108123448.26286186e74f899caaf5ad35-xXdDKFdH5B3kFDPD4ZthVA@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , List-Id: linux-spi.vger.kernel.org On Wed, 8 Jan 2020 12:34:48 +0100 Emmanuel Vadot wrote: Hi Emmanuel, > On Wed, 8 Jan 2020 10:10:05 +0000 > Andre Przywara wrote: > > > The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, > > but with the added capability of 3-wire and 4-wire operation modes. > > For now the driver does not support those, but the SPI registers are > > fully backwards-compatible, just adding bits and registers which were > > formerly reserved. So we can use the existing driver for the "normal" SPI > > modes, for instance to access the SPI NOR flash soldered on the PineH64 > > board. > > We use an H6 specific compatible string in addition to the existing H3 > > string, so when the driver later gains Quad SPI support, it should work > > automatically without any DT changes. > > > > Tested by accessing the SPI flash on a Pine H64 board (SPI0), also > > connecting another SPI flash to the SPI1 header pins. > > > > Signed-off-by: Andre Przywara > > --- > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 ++++++++++++++++++++ > > 1 file changed, 54 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > index 3329283e38ab..40835850893e 100644 > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > @@ -338,6 +338,30 @@ > > bias-pull-up; > > }; > > > > + /omit-if-no-ref/ > > That would prevent users to use an overlay and use those pins, is that > something that we want ? I'm not sure that the space saved by those are > useful. Me neither ;-), but Maxime asked for it before, and it doesn't really hurt. For overlays: if a .dtb is compiled with support for overlays (-@ to generate symbols), this tag is ignored, and the nodes stay in the .dtb, regardless of being referenced or not. Just confirmed by trying this. Cheers, Andre. > > Cheers, > > > + spi0_pins: spi0-pins { > > + pins = "PC0", "PC2", "PC3"; > > + function = "spi0"; > > + }; > > + > > + /omit-if-no-ref/ > > + spi0_cs_pin: spi0-cs-pin { > > + pins = "PC5"; > > + function = "spi0"; > > + }; > > + > > + /omit-if-no-ref/ > > + spi1_pins: spi1-pins { > > + pins = "PH4", "PH5", "PH6"; > > + function = "spi1"; > > + }; > > + > > + /omit-if-no-ref/ > > + spi1_cs_pin: spi1-cs-pin { > > + pins = "PH3"; > > + function = "spi1"; > > + }; > > + > > spdif_tx_pin: spdif-tx-pin { > > pins = "PH7"; > > function = "spdif"; > > @@ -504,6 +528,36 @@ > > #size-cells = <0>; > > }; > > > > + spi0: spi@5010000 { > > + compatible = "allwinner,sun50i-h6-spi", > > + "allwinner,sun8i-h3-spi"; > > + reg = <0x05010000 0x1000>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; > > + clock-names = "ahb", "mod"; > > + dmas = <&dma 22>, <&dma 22>; > > + dma-names = "rx", "tx"; > > + resets = <&ccu RST_BUS_SPI0>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + spi1: spi@5011000 { > > + compatible = "allwinner,sun50i-h6-spi", > > + "allwinner,sun8i-h3-spi"; > > + reg = <0x05011000 0x1000>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; > > + clock-names = "ahb", "mod"; > > + dmas = <&dma 23>, <&dma 23>; > > + dma-names = "rx", "tx"; > > + resets = <&ccu RST_BUS_SPI1>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > emac: ethernet@5020000 { > > compatible = "allwinner,sun50i-h6-emac", > > "allwinner,sun50i-a64-emac"; > > -- > > 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94D87C33C9E for ; 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Wed, 8 Jan 2020 03:47:22 -0800 (PST) Date: Wed, 8 Jan 2020 11:47:06 +0000 From: Andre Przywara To: Emmanuel Vadot Subject: Re: [PATCH 1/2] arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes Message-ID: <20200108114706.5f27a9b2@donnerap.cambridge.arm.com> In-Reply-To: <20200108123448.26286186e74f899caaf5ad35@bidouilliste.com> References: <20200108101006.150706-1-andre.przywara@arm.com> <20200108101006.150706-2-andre.przywara@arm.com> <20200108123448.26286186e74f899caaf5ad35@bidouilliste.com> Organization: ARM X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200108_034724_972636_3DA5DA9D X-CRM114-Status: GOOD ( 23.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Mark Brown , linux-sunxi@googlegroups.com, Maxime Ripard , linux-spi@vger.kernel.org, Chen-Yu Tsai , Rob Herring , Icenowy Zheng , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 8 Jan 2020 12:34:48 +0100 Emmanuel Vadot wrote: Hi Emmanuel, > On Wed, 8 Jan 2020 10:10:05 +0000 > Andre Przywara wrote: > > > The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, > > but with the added capability of 3-wire and 4-wire operation modes. > > For now the driver does not support those, but the SPI registers are > > fully backwards-compatible, just adding bits and registers which were > > formerly reserved. So we can use the existing driver for the "normal" SPI > > modes, for instance to access the SPI NOR flash soldered on the PineH64 > > board. > > We use an H6 specific compatible string in addition to the existing H3 > > string, so when the driver later gains Quad SPI support, it should work > > automatically without any DT changes. > > > > Tested by accessing the SPI flash on a Pine H64 board (SPI0), also > > connecting another SPI flash to the SPI1 header pins. > > > > Signed-off-by: Andre Przywara > > --- > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 ++++++++++++++++++++ > > 1 file changed, 54 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > index 3329283e38ab..40835850893e 100644 > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > @@ -338,6 +338,30 @@ > > bias-pull-up; > > }; > > > > + /omit-if-no-ref/ > > That would prevent users to use an overlay and use those pins, is that > something that we want ? I'm not sure that the space saved by those are > useful. Me neither ;-), but Maxime asked for it before, and it doesn't really hurt. For overlays: if a .dtb is compiled with support for overlays (-@ to generate symbols), this tag is ignored, and the nodes stay in the .dtb, regardless of being referenced or not. Just confirmed by trying this. Cheers, Andre. > > Cheers, > > > + spi0_pins: spi0-pins { > > + pins = "PC0", "PC2", "PC3"; > > + function = "spi0"; > > + }; > > + > > + /omit-if-no-ref/ > > + spi0_cs_pin: spi0-cs-pin { > > + pins = "PC5"; > > + function = "spi0"; > > + }; > > + > > + /omit-if-no-ref/ > > + spi1_pins: spi1-pins { > > + pins = "PH4", "PH5", "PH6"; > > + function = "spi1"; > > + }; > > + > > + /omit-if-no-ref/ > > + spi1_cs_pin: spi1-cs-pin { > > + pins = "PH3"; > > + function = "spi1"; > > + }; > > + > > spdif_tx_pin: spdif-tx-pin { > > pins = "PH7"; > > function = "spdif"; > > @@ -504,6 +528,36 @@ > > #size-cells = <0>; > > }; > > > > + spi0: spi@5010000 { > > + compatible = "allwinner,sun50i-h6-spi", > > + "allwinner,sun8i-h3-spi"; > > + reg = <0x05010000 0x1000>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; > > + clock-names = "ahb", "mod"; > > + dmas = <&dma 22>, <&dma 22>; > > + dma-names = "rx", "tx"; > > + resets = <&ccu RST_BUS_SPI0>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + spi1: spi@5011000 { > > + compatible = "allwinner,sun50i-h6-spi", > > + "allwinner,sun8i-h3-spi"; > > + reg = <0x05011000 0x1000>; > > + interrupts = ; > > + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; > > + clock-names = "ahb", "mod"; > > + dmas = <&dma 23>, <&dma 23>; > > + dma-names = "rx", "tx"; > > + resets = <&ccu RST_BUS_SPI1>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > emac: ethernet@5020000 { > > compatible = "allwinner,sun50i-h6-emac", > > "allwinner,sun50i-a64-emac"; > > -- > > 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel