From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3A8CC33C9E for ; Wed, 8 Jan 2020 11:41:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8203F2077B for ; Wed, 8 Jan 2020 11:41:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=bidouilliste.com header.i=@bidouilliste.com header.b="PhASKloP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727112AbgAHLle (ORCPT ); Wed, 8 Jan 2020 06:41:34 -0500 Received: from mail.blih.net ([212.83.177.182]:49453 "EHLO mail.blih.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726098AbgAHLld (ORCPT ); Wed, 8 Jan 2020 06:41:33 -0500 X-Greylist: delayed 399 seconds by postgrey-1.27 at vger.kernel.org; Wed, 08 Jan 2020 06:41:32 EST Received: from mail.blih.net (mail.blih.net [212.83.177.182]) by mail.blih.net (OpenSMTPD) with ESMTP id 27424418; Wed, 8 Jan 2020 12:34:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=bidouilliste.com; h=date :from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=mail; bh=7H1NUSmMYGTvCzHTp3u946ayonA=; b=PhASKloPmfq2zxtZhhvFAVJcLYh9 EeNHZSLV3mkesmLFO4T3Zv9cyEvX7K8LYSaRUbtxmJKYjsJm59EEUnqH7jaTybjT MwIQgnrZKmvn/5njwiZ4jPZue6SdVnp3sw8xxu1XjqdfXjYAwEzYS07V1zttJZnb u76lUtexR10di7o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=bidouilliste.com; h=date :from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; q=dns; s= mail; b=Rxq9HddvpMW4jpGLx2rRA8IPzZWQwam861gSUz+9SUdaKmhBjzGWOdAa YtayE0ngW4S0NUt48Yaq4LgJRCyXj4MaleCocNkh652cQxB7HR0uOpdEoKuQoK+q xZIua6BHtguXz9stBKjDeKVTyAWVnlYhMNb1RSQUiTZxnRnPOns= Received: from skull.home.blih.net (lfbn-idf2-1-1164-130.w90-92.abo.wanadoo.fr [90.92.223.130]) by mail.blih.net (OpenSMTPD) with ESMTPSA id 32876efc TLS version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO; Wed, 8 Jan 2020 12:34:51 +0100 (CET) Date: Wed, 8 Jan 2020 12:34:48 +0100 From: Emmanuel Vadot To: Andre Przywara Cc: Maxime Ripard , Chen-Yu Tsai , Mark Rutland , devicetree@vger.kernel.org, Rob Herring , linux-spi@vger.kernel.org, linux-sunxi@googlegroups.com, Mark Brown , Icenowy Zheng , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/2] arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes Message-Id: <20200108123448.26286186e74f899caaf5ad35@bidouilliste.com> In-Reply-To: <20200108101006.150706-2-andre.przywara@arm.com> References: <20200108101006.150706-1-andre.przywara@arm.com> <20200108101006.150706-2-andre.przywara@arm.com> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; amd64-portbld-freebsd13.0) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Andre, On Wed, 8 Jan 2020 10:10:05 +0000 Andre Przywara wrote: > The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, > but with the added capability of 3-wire and 4-wire operation modes. > For now the driver does not support those, but the SPI registers are > fully backwards-compatible, just adding bits and registers which were > formerly reserved. So we can use the existing driver for the "normal" SPI > modes, for instance to access the SPI NOR flash soldered on the PineH64 > board. > We use an H6 specific compatible string in addition to the existing H3 > string, so when the driver later gains Quad SPI support, it should work > automatically without any DT changes. > > Tested by accessing the SPI flash on a Pine H64 board (SPI0), also > connecting another SPI flash to the SPI1 header pins. > > Signed-off-by: Andre Przywara > --- > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 ++++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > index 3329283e38ab..40835850893e 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > @@ -338,6 +338,30 @@ > bias-pull-up; > }; > > + /omit-if-no-ref/ That would prevent users to use an overlay and use those pins, is that something that we want ? I'm not sure that the space saved by those are useful. Cheers, > + spi0_pins: spi0-pins { > + pins = "PC0", "PC2", "PC3"; > + function = "spi0"; > + }; > + > + /omit-if-no-ref/ > + spi0_cs_pin: spi0-cs-pin { > + pins = "PC5"; > + function = "spi0"; > + }; > + > + /omit-if-no-ref/ > + spi1_pins: spi1-pins { > + pins = "PH4", "PH5", "PH6"; > + function = "spi1"; > + }; > + > + /omit-if-no-ref/ > + spi1_cs_pin: spi1-cs-pin { > + pins = "PH3"; > + function = "spi1"; > + }; > + > spdif_tx_pin: spdif-tx-pin { > pins = "PH7"; > function = "spdif"; > @@ -504,6 +528,36 @@ > #size-cells = <0>; > }; > > + spi0: spi@5010000 { > + compatible = "allwinner,sun50i-h6-spi", > + "allwinner,sun8i-h3-spi"; > + reg = <0x05010000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; > + clock-names = "ahb", "mod"; > + dmas = <&dma 22>, <&dma 22>; > + dma-names = "rx", "tx"; > + resets = <&ccu RST_BUS_SPI0>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + spi1: spi@5011000 { > + compatible = "allwinner,sun50i-h6-spi", > + "allwinner,sun8i-h3-spi"; > + reg = <0x05011000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; > + clock-names = "ahb", "mod"; > + dmas = <&dma 23>, <&dma 23>; > + dma-names = "rx", "tx"; > + resets = <&ccu RST_BUS_SPI1>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > emac: ethernet@5020000 { > compatible = "allwinner,sun50i-h6-emac", > "allwinner,sun50i-a64-emac"; > -- > 2.17.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Emmanuel Vadot From mboxrd@z Thu Jan 1 00:00:00 1970 From: Emmanuel Vadot Subject: Re: [PATCH 1/2] arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes Date: Wed, 8 Jan 2020 12:34:48 +0100 Message-ID: <20200108123448.26286186e74f899caaf5ad35@bidouilliste.com> References: <20200108101006.150706-1-andre.przywara@arm.com> <20200108101006.150706-2-andre.przywara@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Mark Rutland , devicetree@vger.kernel.org, Mark Brown , linux-sunxi@googlegroups.com, Maxime Ripard , linux-spi@vger.kernel.org, Chen-Yu Tsai , Rob Herring , Icenowy Zheng , linux-arm-kernel@lists.infradead.org To: Andre Przywara Return-path: In-Reply-To: <20200108101006.150706-2-andre.przywara@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org List-Id: linux-spi.vger.kernel.org Hi Andre, On Wed, 8 Jan 2020 10:10:05 +0000 Andre Przywara wrote: > The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, > but with the added capability of 3-wire and 4-wire operation modes. > For now the driver does not support those, but the SPI registers are > fully backwards-compatible, just adding bits and registers which were > formerly reserved. So we can use the existing driver for the "normal" SPI > modes, for instance to access the SPI NOR flash soldered on the PineH64 > board. > We use an H6 specific compatible string in addition to the existing H3 > string, so when the driver later gains Quad SPI support, it should work > automatically without any DT changes. > > Tested by accessing the SPI flash on a Pine H64 board (SPI0), also > connecting another SPI flash to the SPI1 header pins. > > Signed-off-by: Andre Przywara > --- > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 ++++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > index 3329283e38ab..40835850893e 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > @@ -338,6 +338,30 @@ > bias-pull-up; > }; > > + /omit-if-no-ref/ That would prevent users to use an overlay and use those pins, is that something that we want ? I'm not sure that the space saved by those are useful. Cheers, > + spi0_pins: spi0-pins { > + pins = "PC0", "PC2", "PC3"; > + function = "spi0"; > + }; > + > + /omit-if-no-ref/ > + spi0_cs_pin: spi0-cs-pin { > + pins = "PC5"; > + function = "spi0"; > + }; > + > + /omit-if-no-ref/ > + spi1_pins: spi1-pins { > + pins = "PH4", "PH5", "PH6"; > + function = "spi1"; > + }; > + > + /omit-if-no-ref/ > + spi1_cs_pin: spi1-cs-pin { > + pins = "PH3"; > + function = "spi1"; > + }; > + > spdif_tx_pin: spdif-tx-pin { > pins = "PH7"; > function = "spdif"; > @@ -504,6 +528,36 @@ > #size-cells = <0>; > }; > > + spi0: spi@5010000 { > + compatible = "allwinner,sun50i-h6-spi", > + "allwinner,sun8i-h3-spi"; > + reg = <0x05010000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; > + clock-names = "ahb", "mod"; > + dmas = <&dma 22>, <&dma 22>; > + dma-names = "rx", "tx"; > + resets = <&ccu RST_BUS_SPI0>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + spi1: spi@5011000 { > + compatible = "allwinner,sun50i-h6-spi", > + "allwinner,sun8i-h3-spi"; > + reg = <0x05011000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; > + clock-names = "ahb", "mod"; > + dmas = <&dma 23>, <&dma 23>; > + dma-names = "rx", "tx"; > + resets = <&ccu RST_BUS_SPI1>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > emac: ethernet@5020000 { > compatible = "allwinner,sun50i-h6-emac", > "allwinner,sun50i-a64-emac"; > -- > 2.17.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Emmanuel Vadot From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B03C4C33C9E for ; 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Wed, 8 Jan 2020 12:34:51 +0100 (CET) Date: Wed, 8 Jan 2020 12:34:48 +0100 From: Emmanuel Vadot To: Andre Przywara Subject: Re: [PATCH 1/2] arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes Message-Id: <20200108123448.26286186e74f899caaf5ad35@bidouilliste.com> In-Reply-To: <20200108101006.150706-2-andre.przywara@arm.com> References: <20200108101006.150706-1-andre.przywara@arm.com> <20200108101006.150706-2-andre.przywara@arm.com> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; amd64-portbld-freebsd13.0) Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200108_033456_667495_0B0B3222 X-CRM114-Status: GOOD ( 21.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Mark Brown , linux-sunxi@googlegroups.com, Maxime Ripard , linux-spi@vger.kernel.org, Chen-Yu Tsai , Rob Herring , Icenowy Zheng , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Andre, On Wed, 8 Jan 2020 10:10:05 +0000 Andre Przywara wrote: > The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, > but with the added capability of 3-wire and 4-wire operation modes. > For now the driver does not support those, but the SPI registers are > fully backwards-compatible, just adding bits and registers which were > formerly reserved. So we can use the existing driver for the "normal" SPI > modes, for instance to access the SPI NOR flash soldered on the PineH64 > board. > We use an H6 specific compatible string in addition to the existing H3 > string, so when the driver later gains Quad SPI support, it should work > automatically without any DT changes. > > Tested by accessing the SPI flash on a Pine H64 board (SPI0), also > connecting another SPI flash to the SPI1 header pins. > > Signed-off-by: Andre Przywara > --- > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 ++++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > index 3329283e38ab..40835850893e 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > @@ -338,6 +338,30 @@ > bias-pull-up; > }; > > + /omit-if-no-ref/ That would prevent users to use an overlay and use those pins, is that something that we want ? I'm not sure that the space saved by those are useful. Cheers, > + spi0_pins: spi0-pins { > + pins = "PC0", "PC2", "PC3"; > + function = "spi0"; > + }; > + > + /omit-if-no-ref/ > + spi0_cs_pin: spi0-cs-pin { > + pins = "PC5"; > + function = "spi0"; > + }; > + > + /omit-if-no-ref/ > + spi1_pins: spi1-pins { > + pins = "PH4", "PH5", "PH6"; > + function = "spi1"; > + }; > + > + /omit-if-no-ref/ > + spi1_cs_pin: spi1-cs-pin { > + pins = "PH3"; > + function = "spi1"; > + }; > + > spdif_tx_pin: spdif-tx-pin { > pins = "PH7"; > function = "spdif"; > @@ -504,6 +528,36 @@ > #size-cells = <0>; > }; > > + spi0: spi@5010000 { > + compatible = "allwinner,sun50i-h6-spi", > + "allwinner,sun8i-h3-spi"; > + reg = <0x05010000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; > + clock-names = "ahb", "mod"; > + dmas = <&dma 22>, <&dma 22>; > + dma-names = "rx", "tx"; > + resets = <&ccu RST_BUS_SPI0>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + spi1: spi@5011000 { > + compatible = "allwinner,sun50i-h6-spi", > + "allwinner,sun8i-h3-spi"; > + reg = <0x05011000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; > + clock-names = "ahb", "mod"; > + dmas = <&dma 23>, <&dma 23>; > + dma-names = "rx", "tx"; > + resets = <&ccu RST_BUS_SPI1>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > emac: ethernet@5020000 { > compatible = "allwinner,sun50i-h6-emac", > "allwinner,sun50i-a64-emac"; > -- > 2.17.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Emmanuel Vadot _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel