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[81.140.166.164]) by smtp.gmail.com with ESMTPSA id a16sm8545544wrt.37.2020.01.09.08.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 08:05:42 -0800 (PST) From: Julien Thierry To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: jpoimboe@redhat.com, peterz@infradead.org, raphael.gault@arm.com, catalin.marinas@arm.com, will@kernel.org, Julien Thierry Subject: [RFC v5 20/57] objtool: arm64: Decode unknown instructions Date: Thu, 9 Jan 2020 16:02:23 +0000 Message-Id: <20200109160300.26150-21-jthierry@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200109160300.26150-1-jthierry@redhat.com> References: <20200109160300.26150-1-jthierry@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For aarch64, it is possible to have byte sequences that aren't valid opcodes in the code sections. Do not report an error when the decoder finds such a sequence, but make sure that those bytes cannot be reached in the execution flow. Suggested-by: Raphael Gault Signed-off-by: Julien Thierry --- tools/objtool/arch.h | 1 + tools/objtool/arch/arm64/decode.c | 22 ++++++++++++++++++- .../objtool/arch/arm64/include/insn_decode.h | 7 ++++++ tools/objtool/check.c | 10 ++++++++- 4 files changed, 38 insertions(+), 2 deletions(-) diff --git a/tools/objtool/arch.h b/tools/objtool/arch.h index f9883c431949..0336efecb9d9 100644 --- a/tools/objtool/arch.h +++ b/tools/objtool/arch.h @@ -28,6 +28,7 @@ enum insn_type { INSN_STD, INSN_CLD, INSN_OTHER, + INSN_INVALID, }; enum op_dest_type { diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c index 4d0ab2acca27..04358f41ef1d 100644 --- a/tools/objtool/arch/arm64/decode.c +++ b/tools/objtool/arch/arm64/decode.c @@ -78,7 +78,9 @@ static int is_arm64(struct elf *elf) * struct list_head *ops_list); */ static arm_decode_class aarch64_insn_class_decode_table[NR_INSN_CLASS] = { - NULL, + [INSN_RESERVED] = arm_decode_unknown, + [INSN_UNKNOWN] = arm_decode_unknown, + [INSN_UNALLOC] = arm_decode_unknown, }; /* @@ -125,3 +127,21 @@ int arch_decode_instruction(struct elf *elf, struct section *sec, WARN_FUNC("Unsupported instruction", sec, offset); return res; } + +int arm_decode_unknown(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + /* + * There are a few reasons we might have non-valid opcodes in + * code sections: + * - For load literal, assembler can generate the data to be loaded in + * the code section + * - Compiler/assembler can generate zeroes to pad function that do not + * end on 8-byte alignment + * - Hand written assembly code might contain constants in the code + * section + */ + *type = INSN_INVALID; + + return 0; +} diff --git a/tools/objtool/arch/arm64/include/insn_decode.h b/tools/objtool/arch/arm64/include/insn_decode.h index c56b72ac4633..16066f8fca0d 100644 --- a/tools/objtool/arch/arm64/include/insn_decode.h +++ b/tools/objtool/arch/arm64/include/insn_decode.h @@ -5,6 +5,10 @@ #include "../../../arch.h" +#define INSN_RESERVED 0b0000 +#define INSN_UNKNOWN 0b0001 +#define INSN_UNALLOC 0b0011 + #define NR_INSN_CLASS 16 #define INSN_CLASS(opcode) (((opcode) >> 25) & (NR_INSN_CLASS - 1)) @@ -12,4 +16,7 @@ typedef int (*arm_decode_class)(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list); +/* arm64 instruction classes */ +int arm_decode_unknown(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list); #endif /* _ARM_INSN_DECODE_H */ diff --git a/tools/objtool/check.c b/tools/objtool/check.c index 48aec56a7760..52a8e64e15ca 100644 --- a/tools/objtool/check.c +++ b/tools/objtool/check.c @@ -1818,6 +1818,13 @@ static int validate_branch_alt_safe(struct objtool_file *file, while (1) { next_insn = next_insn_same_sec(file, insn); + if (insn->type == INSN_INVALID) { + WARN("%s+0x%lx non-executable instruction, should never be reached", + insn->sec->name, + insn->offset); + return 1; + } + if (file->c_file && func && insn->func && func != insn->func->pfunc) { WARN("%s() falls through to next function %s()", func->name, insn->func->name); @@ -2137,7 +2144,8 @@ static bool ignore_unreachable_insn(struct instruction *insn) { int i; - if (insn->ignore || insn->type == INSN_NOP) + if (insn->ignore || insn->type == INSN_NOP || + insn->type == INSN_INVALID) return true; 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[81.140.166.164]) by smtp.gmail.com with ESMTPSA id a16sm8545544wrt.37.2020.01.09.08.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 08:05:42 -0800 (PST) From: Julien Thierry To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC v5 20/57] objtool: arm64: Decode unknown instructions Date: Thu, 9 Jan 2020 16:02:23 +0000 Message-Id: <20200109160300.26150-21-jthierry@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200109160300.26150-1-jthierry@redhat.com> References: <20200109160300.26150-1-jthierry@redhat.com> MIME-Version: 1.0 X-MC-Unique: rPg8Z3-UMoOcS4N5SVcghg-1 X-Mimecast-Spam-Score: 0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200109_080546_905141_F3188191 X-CRM114-Status: GOOD ( 12.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julien Thierry , peterz@infradead.org, catalin.marinas@arm.com, raphael.gault@arm.com, jpoimboe@redhat.com, will@kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org For aarch64, it is possible to have byte sequences that aren't valid opcodes in the code sections. Do not report an error when the decoder finds such a sequence, but make sure that those bytes cannot be reached in the execution flow. Suggested-by: Raphael Gault Signed-off-by: Julien Thierry --- tools/objtool/arch.h | 1 + tools/objtool/arch/arm64/decode.c | 22 ++++++++++++++++++- .../objtool/arch/arm64/include/insn_decode.h | 7 ++++++ tools/objtool/check.c | 10 ++++++++- 4 files changed, 38 insertions(+), 2 deletions(-) diff --git a/tools/objtool/arch.h b/tools/objtool/arch.h index f9883c431949..0336efecb9d9 100644 --- a/tools/objtool/arch.h +++ b/tools/objtool/arch.h @@ -28,6 +28,7 @@ enum insn_type { INSN_STD, INSN_CLD, INSN_OTHER, + INSN_INVALID, }; enum op_dest_type { diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c index 4d0ab2acca27..04358f41ef1d 100644 --- a/tools/objtool/arch/arm64/decode.c +++ b/tools/objtool/arch/arm64/decode.c @@ -78,7 +78,9 @@ static int is_arm64(struct elf *elf) * struct list_head *ops_list); */ static arm_decode_class aarch64_insn_class_decode_table[NR_INSN_CLASS] = { - NULL, + [INSN_RESERVED] = arm_decode_unknown, + [INSN_UNKNOWN] = arm_decode_unknown, + [INSN_UNALLOC] = arm_decode_unknown, }; /* @@ -125,3 +127,21 @@ int arch_decode_instruction(struct elf *elf, struct section *sec, WARN_FUNC("Unsupported instruction", sec, offset); return res; } + +int arm_decode_unknown(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list) +{ + /* + * There are a few reasons we might have non-valid opcodes in + * code sections: + * - For load literal, assembler can generate the data to be loaded in + * the code section + * - Compiler/assembler can generate zeroes to pad function that do not + * end on 8-byte alignment + * - Hand written assembly code might contain constants in the code + * section + */ + *type = INSN_INVALID; + + return 0; +} diff --git a/tools/objtool/arch/arm64/include/insn_decode.h b/tools/objtool/arch/arm64/include/insn_decode.h index c56b72ac4633..16066f8fca0d 100644 --- a/tools/objtool/arch/arm64/include/insn_decode.h +++ b/tools/objtool/arch/arm64/include/insn_decode.h @@ -5,6 +5,10 @@ #include "../../../arch.h" +#define INSN_RESERVED 0b0000 +#define INSN_UNKNOWN 0b0001 +#define INSN_UNALLOC 0b0011 + #define NR_INSN_CLASS 16 #define INSN_CLASS(opcode) (((opcode) >> 25) & (NR_INSN_CLASS - 1)) @@ -12,4 +16,7 @@ typedef int (*arm_decode_class)(u32 instr, enum insn_type *type, unsigned long *immediate, struct list_head *ops_list); +/* arm64 instruction classes */ +int arm_decode_unknown(u32 instr, enum insn_type *type, + unsigned long *immediate, struct list_head *ops_list); #endif /* _ARM_INSN_DECODE_H */ diff --git a/tools/objtool/check.c b/tools/objtool/check.c index 48aec56a7760..52a8e64e15ca 100644 --- a/tools/objtool/check.c +++ b/tools/objtool/check.c @@ -1818,6 +1818,13 @@ static int validate_branch_alt_safe(struct objtool_file *file, while (1) { next_insn = next_insn_same_sec(file, insn); + if (insn->type == INSN_INVALID) { + WARN("%s+0x%lx non-executable instruction, should never be reached", + insn->sec->name, + insn->offset); + return 1; + } + if (file->c_file && func && insn->func && func != insn->func->pfunc) { WARN("%s() falls through to next function %s()", func->name, insn->func->name); @@ -2137,7 +2144,8 @@ static bool ignore_unreachable_insn(struct instruction *insn) { int i; - if (insn->ignore || insn->type == INSN_NOP) + if (insn->ignore || insn->type == INSN_NOP || + insn->type == INSN_INVALID) return true; /* -- 2.21.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel