From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25102C282DD for ; Thu, 9 Jan 2020 17:46:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 00F8720678 for ; Thu, 9 Jan 2020 17:46:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388277AbgAIRqZ (ORCPT ); Thu, 9 Jan 2020 12:46:25 -0500 Received: from foss.arm.com ([217.140.110.172]:35174 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728724AbgAIRqZ (ORCPT ); Thu, 9 Jan 2020 12:46:25 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 58D57328; Thu, 9 Jan 2020 09:46:24 -0800 (PST) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CDE423F703; Thu, 9 Jan 2020 09:46:23 -0800 (PST) Date: Thu, 9 Jan 2020 17:46:22 +0000 From: Andrew Murray To: Mark Rutland Cc: Marc Zyngier , kvm@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 11/18] KVM: arm64: don't trap Statistical Profiling controls to EL2 Message-ID: <20200109174621.GB42593@e119886-lin.cambridge.arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> <20191220143025.33853-12-andrew.murray@arm.com> <86bls0iqv6.wl-maz@kernel.org> <20191223115651.GA42593@e119886-lin.cambridge.arm.com> <1bb190091362262021dbaf41b5fe601e@www.loen.fr> <20191223121042.GC42593@e119886-lin.cambridge.arm.com> <20200109172511.GA42593@e119886-lin.cambridge.arm.com> <20200109174251.GJ3112@lakrids.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200109174251.GJ3112@lakrids.cambridge.arm.com> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 09, 2020 at 05:42:51PM +0000, Mark Rutland wrote: > Hi Andrew, > > On Thu, Jan 09, 2020 at 05:25:12PM +0000, Andrew Murray wrote: > > On Mon, Dec 23, 2019 at 12:10:42PM +0000, Andrew Murray wrote: > > > On Mon, Dec 23, 2019 at 12:05:12PM +0000, Marc Zyngier wrote: > > > > On 2019-12-23 11:56, Andrew Murray wrote: > > > > > My original concern in the cover letter was in how to prevent > > > > > the guest from attempting to use these registers in the first > > > > > place - I think the solution I was looking for is to > > > > > trap-and-emulate ID_AA64DFR0_EL1 such that the PMSVer bits > > > > > indicate that SPE is not emulated. > > > > > > > > That, and active trapping of the SPE system registers resulting in injection > > > > of an UNDEF into the offending guest. > > > > > > Yes that's no problem. > > > > The spec says that 'direct access to [these registers] are UNDEFINED' - is it > > not more correct to handle this with trap_raz_wi than an undefined instruction? > > The term UNDEFINED specifically means treated as an undefined > instruction. The Glossary in ARM DDI 0487E.a says for UNDEFINED: > > | Indicates cases where an attempt to execute a particular encoding bit > | pattern generates an exception, that is taken to the current Exception > | level, or to the default Exception level for taking exceptions if the > | UNDEFINED encoding was executed at EL0. This applies to: > | > | * Any encoding that is not allocated to any instruction. > | > | * Any encoding that is defined as never accessible at the current > | Exception level. > | > | * Some cases where an enable, disable, or trap control means an > | encoding is not accessible at the current Exception level. > > So these should trigger an UNDEFINED exception rather than behaving as > RAZ/WI. OK thanks for the clarification - I'll leave it as an undefined instruction. Thanks, Andrew Murray > > Thanks, > Mark. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06DFFC33CA1 for ; Thu, 9 Jan 2020 17:46:30 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 9480120678 for ; Thu, 9 Jan 2020 17:46:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9480120678 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id E81C44B24A; Thu, 9 Jan 2020 12:46:28 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rg3+Yk--M9YZ; Thu, 9 Jan 2020 12:46:27 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id CCD504B250; Thu, 9 Jan 2020 12:46:27 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id D12044B23E for ; Thu, 9 Jan 2020 12:46:25 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4Kg356vHmueM for ; Thu, 9 Jan 2020 12:46:24 -0500 (EST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id A874D4B214 for ; Thu, 9 Jan 2020 12:46:24 -0500 (EST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 58D57328; Thu, 9 Jan 2020 09:46:24 -0800 (PST) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CDE423F703; Thu, 9 Jan 2020 09:46:23 -0800 (PST) Date: Thu, 9 Jan 2020 17:46:22 +0000 From: Andrew Murray To: Mark Rutland Subject: Re: [PATCH v2 11/18] KVM: arm64: don't trap Statistical Profiling controls to EL2 Message-ID: <20200109174621.GB42593@e119886-lin.cambridge.arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> <20191220143025.33853-12-andrew.murray@arm.com> <86bls0iqv6.wl-maz@kernel.org> <20191223115651.GA42593@e119886-lin.cambridge.arm.com> <1bb190091362262021dbaf41b5fe601e@www.loen.fr> <20191223121042.GC42593@e119886-lin.cambridge.arm.com> <20200109172511.GA42593@e119886-lin.cambridge.arm.com> <20200109174251.GJ3112@lakrids.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200109174251.GJ3112@lakrids.cambridge.arm.com> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) Cc: Catalin Marinas , kvm@vger.kernel.org, Marc Zyngier , linux-kernel@vger.kernel.org, Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, Jan 09, 2020 at 05:42:51PM +0000, Mark Rutland wrote: > Hi Andrew, > > On Thu, Jan 09, 2020 at 05:25:12PM +0000, Andrew Murray wrote: > > On Mon, Dec 23, 2019 at 12:10:42PM +0000, Andrew Murray wrote: > > > On Mon, Dec 23, 2019 at 12:05:12PM +0000, Marc Zyngier wrote: > > > > On 2019-12-23 11:56, Andrew Murray wrote: > > > > > My original concern in the cover letter was in how to prevent > > > > > the guest from attempting to use these registers in the first > > > > > place - I think the solution I was looking for is to > > > > > trap-and-emulate ID_AA64DFR0_EL1 such that the PMSVer bits > > > > > indicate that SPE is not emulated. > > > > > > > > That, and active trapping of the SPE system registers resulting in injection > > > > of an UNDEF into the offending guest. > > > > > > Yes that's no problem. > > > > The spec says that 'direct access to [these registers] are UNDEFINED' - is it > > not more correct to handle this with trap_raz_wi than an undefined instruction? > > The term UNDEFINED specifically means treated as an undefined > instruction. The Glossary in ARM DDI 0487E.a says for UNDEFINED: > > | Indicates cases where an attempt to execute a particular encoding bit > | pattern generates an exception, that is taken to the current Exception > | level, or to the default Exception level for taking exceptions if the > | UNDEFINED encoding was executed at EL0. This applies to: > | > | * Any encoding that is not allocated to any instruction. > | > | * Any encoding that is defined as never accessible at the current > | Exception level. > | > | * Some cases where an enable, disable, or trap control means an > | encoding is not accessible at the current Exception level. > > So these should trigger an UNDEFINED exception rather than behaving as > RAZ/WI. OK thanks for the clarification - I'll leave it as an undefined instruction. Thanks, Andrew Murray > > Thanks, > Mark. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47151C282DD for ; Thu, 9 Jan 2020 17:46:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1A4142073A for ; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ipbt6-0001MH-Pd; Thu, 09 Jan 2020 17:46:28 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ipbt3-0001Lm-1G for linux-arm-kernel@lists.infradead.org; Thu, 09 Jan 2020 17:46:26 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 58D57328; Thu, 9 Jan 2020 09:46:24 -0800 (PST) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CDE423F703; Thu, 9 Jan 2020 09:46:23 -0800 (PST) Date: Thu, 9 Jan 2020 17:46:22 +0000 From: Andrew Murray To: Mark Rutland Subject: Re: [PATCH v2 11/18] KVM: arm64: don't trap Statistical Profiling controls to EL2 Message-ID: <20200109174621.GB42593@e119886-lin.cambridge.arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> <20191220143025.33853-12-andrew.murray@arm.com> <86bls0iqv6.wl-maz@kernel.org> <20191223115651.GA42593@e119886-lin.cambridge.arm.com> <1bb190091362262021dbaf41b5fe601e@www.loen.fr> <20191223121042.GC42593@e119886-lin.cambridge.arm.com> <20200109172511.GA42593@e119886-lin.cambridge.arm.com> <20200109174251.GJ3112@lakrids.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200109174251.GJ3112@lakrids.cambridge.arm.com> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200109_094625_119494_411CA2F5 X-CRM114-Status: GOOD ( 18.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Catalin Marinas , kvm@vger.kernel.org, Marc Zyngier , linux-kernel@vger.kernel.org, Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 09, 2020 at 05:42:51PM +0000, Mark Rutland wrote: > Hi Andrew, > > On Thu, Jan 09, 2020 at 05:25:12PM +0000, Andrew Murray wrote: > > On Mon, Dec 23, 2019 at 12:10:42PM +0000, Andrew Murray wrote: > > > On Mon, Dec 23, 2019 at 12:05:12PM +0000, Marc Zyngier wrote: > > > > On 2019-12-23 11:56, Andrew Murray wrote: > > > > > My original concern in the cover letter was in how to prevent > > > > > the guest from attempting to use these registers in the first > > > > > place - I think the solution I was looking for is to > > > > > trap-and-emulate ID_AA64DFR0_EL1 such that the PMSVer bits > > > > > indicate that SPE is not emulated. > > > > > > > > That, and active trapping of the SPE system registers resulting in injection > > > > of an UNDEF into the offending guest. > > > > > > Yes that's no problem. > > > > The spec says that 'direct access to [these registers] are UNDEFINED' - is it > > not more correct to handle this with trap_raz_wi than an undefined instruction? > > The term UNDEFINED specifically means treated as an undefined > instruction. The Glossary in ARM DDI 0487E.a says for UNDEFINED: > > | Indicates cases where an attempt to execute a particular encoding bit > | pattern generates an exception, that is taken to the current Exception > | level, or to the default Exception level for taking exceptions if the > | UNDEFINED encoding was executed at EL0. This applies to: > | > | * Any encoding that is not allocated to any instruction. > | > | * Any encoding that is defined as never accessible at the current > | Exception level. > | > | * Some cases where an enable, disable, or trap control means an > | encoding is not accessible at the current Exception level. > > So these should trigger an UNDEFINED exception rather than behaving as > RAZ/WI. OK thanks for the clarification - I'll leave it as an undefined instruction. Thanks, Andrew Murray > > Thanks, > Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel