From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA99BC33CA2 for ; Fri, 10 Jan 2020 08:13:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85C262072A for ; Fri, 10 Jan 2020 08:13:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 85C262072A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:42388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ippQW-0003Vp-MA for qemu-devel@archiver.kernel.org; Fri, 10 Jan 2020 03:13:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45716) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ippPs-0002yp-AG for qemu-devel@nongnu.org; Fri, 10 Jan 2020 03:13:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ippPq-0004UU-Sw for qemu-devel@nongnu.org; Fri, 10 Jan 2020 03:13:12 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:49220) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ippPq-0003xX-H2; Fri, 10 Jan 2020 03:13:10 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08015814|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.380576-0.0141733-0.605251; DS=CONTINUE|ham_system_inform|0.0907534-0.000993834-0.908253; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03306; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.GZbTVKh_1578643981; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GZbTVKh_1578643981) by smtp.aliyun-inc.com(10.147.41.158); Fri, 10 Jan 2020 16:13:01 +0800 From: LIU Zhiwei To: Alistair.Francis@wdc.com, palmer@dabbelt.com, chihmin.chao@sifive.com, jimw@sifive.com, bmeng.cn@gmail.com Subject: [PATCH 1/3] select gdb fpu xml by single or double float extension Date: Fri, 10 Jan 2020 16:12:18 +0800 Message-Id: <20200110081220.891-1-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" There is no reason why RISCV32 can't use RVD extension, or RISCV64 can't just use RVF extension. And gdb will check flen according to RVD or RVF feature in elf header. Signed-off-by: LIU Zhiwei --- configure | 4 ++-- target/riscv/gdbstub.c | 14 ++++++-------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/configure b/configure index 0ce2c0354a..2757c0a5a5 100755 --- a/configure +++ b/configure @@ -7679,13 +7679,13 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" ;; riscv64) TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" + gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" ;; sh4|sh4eb) TARGET_ARCH=sh4 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 1a7947e019..e3c9b320fb 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -403,23 +403,21 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; -#if defined(TARGET_RISCV32) - if (env->misa & RVF) { + if (env->misa & RVD) { + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + 36, "riscv-64bit-fpu.xml", 0); + } else if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 36, "riscv-32bit-fpu.xml", 0); + 36, "riscv-32bit-fpu.xml", 0); } +#if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-32bit-csr.xml", 0); gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-32bit-virtual.xml", 0); #elif defined(TARGET_RISCV64) - if (env->misa & RVF) { - gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 36, "riscv-64bit-fpu.xml", 0); - } - gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-64bit-csr.xml", 0); -- 2.23.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ippPx-00033R-Tj for mharc-qemu-riscv@gnu.org; Fri, 10 Jan 2020 03:13:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45843) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ippPu-00030R-Lo for qemu-riscv@nongnu.org; Fri, 10 Jan 2020 03:13:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ippPt-0004ge-FA for qemu-riscv@nongnu.org; Fri, 10 Jan 2020 03:13:14 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:49220) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ippPq-0003xX-H2; Fri, 10 Jan 2020 03:13:10 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08015814|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.380576-0.0141733-0.605251; DS=CONTINUE|ham_system_inform|0.0907534-0.000993834-0.908253; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03306; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.GZbTVKh_1578643981; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GZbTVKh_1578643981) by smtp.aliyun-inc.com(10.147.41.158); Fri, 10 Jan 2020 16:13:01 +0800 From: LIU Zhiwei To: Alistair.Francis@wdc.com, palmer@dabbelt.com, chihmin.chao@sifive.com, jimw@sifive.com, bmeng.cn@gmail.com Cc: wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, LIU Zhiwei Subject: [PATCH 1/3] select gdb fpu xml by single or double float extension Date: Fri, 10 Jan 2020 16:12:18 +0800 Message-Id: <20200110081220.891-1-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Jan 2020 08:13:15 -0000 There is no reason why RISCV32 can't use RVD extension, or RISCV64 can't just use RVF extension. And gdb will check flen according to RVD or RVF feature in elf header. Signed-off-by: LIU Zhiwei --- configure | 4 ++-- target/riscv/gdbstub.c | 14 ++++++-------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/configure b/configure index 0ce2c0354a..2757c0a5a5 100755 --- a/configure +++ b/configure @@ -7679,13 +7679,13 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" ;; riscv64) TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" + gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" ;; sh4|sh4eb) TARGET_ARCH=sh4 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 1a7947e019..e3c9b320fb 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -403,23 +403,21 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; -#if defined(TARGET_RISCV32) - if (env->misa & RVF) { + if (env->misa & RVD) { + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + 36, "riscv-64bit-fpu.xml", 0); + } else if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 36, "riscv-32bit-fpu.xml", 0); + 36, "riscv-32bit-fpu.xml", 0); } +#if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-32bit-csr.xml", 0); gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-32bit-virtual.xml", 0); #elif defined(TARGET_RISCV64) - if (env->misa & RVF) { - gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 36, "riscv-64bit-fpu.xml", 0); - } - gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-64bit-csr.xml", 0); -- 2.23.0