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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: mario.kleiner.de@gmail.de,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel <dri-devel@lists.freedesktop.org>,
	Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH] drm/i915/dp: Add current maximum eDP link rate to sink_rate array.
Date: Fri, 10 Jan 2020 15:32:32 +0200	[thread overview]
Message-ID: <20200110133232.GJ13686@intel.com> (raw)
In-Reply-To: <CAEsyxyiTxRZC=Mw4rKvjCQO557Qg6Q2JRkoUvQWOia7SxumznA@mail.gmail.com>

On Thu, Jan 09, 2020 at 09:19:07PM +0100, Mario Kleiner wrote:
> On Thu, Jan 9, 2020 at 7:24 PM Ville Syrjälä <ville.syrjala@linux.intel.com>
> wrote:
> 
> > On Thu, Jan 09, 2020 at 06:57:14PM +0100, Mario Kleiner wrote:
> > > On Thu, Jan 9, 2020 at 5:47 PM Ville Syrjälä <
> > ville.syrjala@linux.intel.com>
> > > wrote:
> > >
> > > > On Thu, Jan 09, 2020 at 05:30:05PM +0100, Mario Kleiner wrote:
> > > > > On Thu, Jan 9, 2020 at 4:38 PM Ville Syrjälä <
> > > > ville.syrjala@linux.intel.com>
> > > > > wrote:
> > > > >
> >
> 
> > wouldn't work if dpcd[0x1] == 0xa, which it likely is [*]. AMD DC
> > > identified it as DP 1.1, eDP 1.3, and these extended caps seem to be only
> > > part of DP 1.3+ if i understand the comments in
> > > intel_dp_extended_receiver_capabilities() correctly.
> >
> >
> Ok, looking at previous debug output logs shows that those extended caps
> are not present on the systems, ie. that extended caps bit is not set. So
> dpcd[0x1] == 0xa.
> 
> 
> > Yeah, but you never know how creative they've been with the DPCD in
> > such a propritary machine. A full DPCD dump from /dev/drm_dp_aux* would
> > be nice. Can you file a bug an attach the DPCD dump there so we have a
> > good reference on what we're talking about (also for future if/when
> > someone eventually starts to wonder why we have such hacks in the
> > code)?
> >
> >
> True, it's Apple which likes to "Think different..." :/
> 
> Will do. But is there a proper/better way to do the /dev/drm_dp_aux0 dump?
> I used cat /dev/drm_dp_aux0 > dump, and that hangs, but if i interrupt it
> after a few seconds, i get a dump file of 512k size, which seems excessive?
> On AMD DC atm., in case that matters.

It can take a while to dump the whole thing. If there are errors in some
parts (against the spec but some devices simply don't care about the
spec) you may need to use ddrescue/etc. to dump everything that can be
dumped.

-- 
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: mario.kleiner.de@gmail.de,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel <dri-devel@lists.freedesktop.org>,
	Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dp: Add current maximum eDP link rate to sink_rate array.
Date: Fri, 10 Jan 2020 15:32:32 +0200	[thread overview]
Message-ID: <20200110133232.GJ13686@intel.com> (raw)
In-Reply-To: <CAEsyxyiTxRZC=Mw4rKvjCQO557Qg6Q2JRkoUvQWOia7SxumznA@mail.gmail.com>

On Thu, Jan 09, 2020 at 09:19:07PM +0100, Mario Kleiner wrote:
> On Thu, Jan 9, 2020 at 7:24 PM Ville Syrjälä <ville.syrjala@linux.intel.com>
> wrote:
> 
> > On Thu, Jan 09, 2020 at 06:57:14PM +0100, Mario Kleiner wrote:
> > > On Thu, Jan 9, 2020 at 5:47 PM Ville Syrjälä <
> > ville.syrjala@linux.intel.com>
> > > wrote:
> > >
> > > > On Thu, Jan 09, 2020 at 05:30:05PM +0100, Mario Kleiner wrote:
> > > > > On Thu, Jan 9, 2020 at 4:38 PM Ville Syrjälä <
> > > > ville.syrjala@linux.intel.com>
> > > > > wrote:
> > > > >
> >
> 
> > wouldn't work if dpcd[0x1] == 0xa, which it likely is [*]. AMD DC
> > > identified it as DP 1.1, eDP 1.3, and these extended caps seem to be only
> > > part of DP 1.3+ if i understand the comments in
> > > intel_dp_extended_receiver_capabilities() correctly.
> >
> >
> Ok, looking at previous debug output logs shows that those extended caps
> are not present on the systems, ie. that extended caps bit is not set. So
> dpcd[0x1] == 0xa.
> 
> 
> > Yeah, but you never know how creative they've been with the DPCD in
> > such a propritary machine. A full DPCD dump from /dev/drm_dp_aux* would
> > be nice. Can you file a bug an attach the DPCD dump there so we have a
> > good reference on what we're talking about (also for future if/when
> > someone eventually starts to wonder why we have such hacks in the
> > code)?
> >
> >
> True, it's Apple which likes to "Think different..." :/
> 
> Will do. But is there a proper/better way to do the /dev/drm_dp_aux0 dump?
> I used cat /dev/drm_dp_aux0 > dump, and that hangs, but if i interrupt it
> after a few seconds, i get a dump file of 512k size, which seems excessive?
> On AMD DC atm., in case that matters.

It can take a while to dump the whole thing. If there are errors in some
parts (against the spec but some devices simply don't care about the
spec) you may need to use ddrescue/etc. to dump everything that can be
dumped.

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-01-10 13:32 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-09 15:07 Mario Kleiner
2020-01-09 15:07 ` [Intel-gfx] " Mario Kleiner
2020-01-09 15:26 ` Ville Syrjälä
2020-01-09 15:26   ` [Intel-gfx] " Ville Syrjälä
2020-01-09 15:38   ` Ville Syrjälä
2020-01-09 15:38     ` [Intel-gfx] " Ville Syrjälä
2020-01-09 16:30     ` Mario Kleiner
2020-01-09 16:30       ` [Intel-gfx] " Mario Kleiner
2020-01-09 16:47       ` Ville Syrjälä
2020-01-09 16:47         ` [Intel-gfx] " Ville Syrjälä
2020-01-09 17:57         ` Mario Kleiner
2020-01-09 17:57           ` [Intel-gfx] " Mario Kleiner
2020-01-09 18:24           ` Ville Syrjälä
2020-01-09 18:24             ` [Intel-gfx] " Ville Syrjälä
2020-01-09 20:19             ` Mario Kleiner
2020-01-09 20:19               ` [Intel-gfx] " Mario Kleiner
2020-01-10 13:32               ` Ville Syrjälä [this message]
2020-01-10 13:32                 ` Ville Syrjälä
2020-01-10 15:50                 ` Mario Kleiner
2020-01-10 15:50                   ` [Intel-gfx] " Mario Kleiner
2020-01-09 16:31     ` Ville Syrjälä
2020-01-09 16:31       ` [Intel-gfx] " Ville Syrjälä
2020-01-09 16:27   ` Mario Kleiner
2020-01-09 16:27     ` [Intel-gfx] " Mario Kleiner
2020-01-09 15:39 ` Alex Deucher
2020-01-09 15:39   ` [Intel-gfx] " Alex Deucher
2020-01-09 16:46   ` Mario Kleiner
2020-01-09 16:46     ` [Intel-gfx] " Mario Kleiner
2020-01-09 19:49     ` Alex Deucher
2020-01-09 19:49       ` [Intel-gfx] " Alex Deucher
2020-01-09 21:04       ` Mario Kleiner
2020-01-09 21:04         ` [Intel-gfx] " Mario Kleiner
2020-01-09 21:26         ` Harry Wentland
2020-01-09 21:26           ` [Intel-gfx] " Harry Wentland
2020-01-10 16:02           ` Mario Kleiner
2020-01-10 16:02             ` [Intel-gfx] " Mario Kleiner
2020-01-10 18:09           ` Ville Syrjälä
2020-01-10 18:09             ` Ville Syrjälä
2020-01-15 12:34             ` Jani Nikula
2020-01-15 12:34               ` Jani Nikula
2020-01-15 14:17               ` Ville Syrjälä
2020-01-15 14:17                 ` Ville Syrjälä
2020-01-09 23:52 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: Add current maximum eDP link rate to sink_rate array. (rev2) Patchwork

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