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From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Leo Li <sunpeng.li@amd.com>,
	Bhawanpreet.Lakha@amd.com,
	Harry Wentland <harry.wentland@amd.com>
Subject: [PATCH 01/43] drm/amd/include: Add OCSC registers
Date: Fri, 10 Jan 2020 09:46:13 -0500	[thread overview]
Message-ID: <20200110144655.55845-2-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20200110144655.55845-1-Rodrigo.Siqueira@amd.com>

Add registers for handling Post Gamma Color Blending (OCSC), which is
useful for conversion from RGB->YUV for HDMI.

Reviewed-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h  | 4 ++++
 .../gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h | 9 ++++++++-
 .../gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h  | 5 ++++-
 .../gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h | 8 ++++++++
 4 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h
index cff8f91555d3..e9b2bd84cfed 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h
@@ -8134,6 +8134,10 @@
 #define mmMPC_OUT5_CSC_C33_C34_B                                                                       0x1604
 #define mmMPC_OUT5_CSC_C33_C34_B_BASE_IDX                                                              2
 
+#define mmMPC_OCSC_TEST_DEBUG_INDEX                                                                    0x163b
+#define mmMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX                                                           2
+#define mmMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX                                                            2
+#define mmMPC_OCSC_TEST_DEBUG_DATA                                                                     0x163c
 
 // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
 // base address: 0x5964
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h
index 10c83fecd147..dc8ce7aaa0cf 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h
@@ -28263,7 +28263,14 @@
 #define MPC_OUT5_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
 #define MPC_OUT5_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
 #define MPC_OUT5_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
-
+//MPC_OCSC_TEST_DEBUG_INDEX
+#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX__SHIFT                                           0x0
+#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN__SHIFT                                        0x8
+#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX_MASK                                             0x000000FFL
+#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN_MASK                                          0x00000100L
+//MPC_OCSC_TEST_DEBUG_DATA
+#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA__SHIFT                                             0x0
+#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA_MASK                                               0xFFFFFFFFL
 
 // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
 //DC_PERFMON17_PERFCOUNTER_CNTL
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
index eddf83ec1c39..7cd0ee61c030 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
@@ -7103,7 +7103,10 @@
 #define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              2
 #define mmMPC_OUT3_CSC_C33_C34_B                                                                       0x15ea
 #define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              2
-
+#define mmMPC_OCSC_TEST_DEBUG_INDEX                                                                    0x163b
+#define mmMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX                                                           2
+#define mmMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX                                                            2
+#define mmMPC_OCSC_TEST_DEBUG_DATA                                                                     0x163c
 
 // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
 // base address: 0x5964
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h
index faa0e76e32b4..2f780aefc722 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h
@@ -56634,5 +56634,13 @@
 #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
 #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
 
+//MPC_OCSC_TEST_DEBUG_INDEX
+#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX__SHIFT                                           0x0
+#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN__SHIFT                                        0x8
+#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX_MASK                                             0x000000FFL
+#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN_MASK                                          0x00000100L
+//MPC_OCSC_TEST_DEBUG_DATA
+#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA__SHIFT                                             0x0
+#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA_MASK                                               0xFFFFFFFFL
 
 #endif
-- 
2.24.1

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  reply	other threads:[~2020-01-10 14:47 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-10 14:46 [PATCH 00/43] DC Patches - January 10, 2020 Rodrigo Siqueira
2020-01-10 14:46 ` Rodrigo Siqueira [this message]
2020-01-10 14:46 ` [PATCH 02/43] drm/amd/display: Clear state after exiting fixed active VRR state Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 03/43] drm/amd/display: 3.2.65 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 04/43] drm/amd/display: fix chroma vp wa corner case Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 05/43] drm/amd/display: Fix 300Hz Freesync bug Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 06/43] drm/amd/display: Disable secondary link for certain monitors Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 07/43] drm/amd/display: Adding forgotten hubbub func Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 08/43] drm/amd/display: Flush framebuffer data before passing to DMCUB Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 09/43] drm/amd/display: Read inst_fb data back during DMUB loading Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 10/43] drm/amd/display: Soft reset DMUIF during DMUB reset Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 11/43] drm/amd/display: Add double buffering to dcn20 OCSC Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 12/43] drm/amd/display: store lttpr mode with dpcd Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 13/43] drm/amd/display: Don't always set pstate true if dummy latency = 0 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 14/43] drm/amd/display: Update HDMI hang w/a to apply to all TMDS signals Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 15/43] drm/amd/display: wait for update when setting dpg test pattern Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 16/43] drm/amd/display: stop doing unnecessary detection when going to D3 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 17/43] drm/amd/display: expand dml structs Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 18/43] drm/amd/display: 3.2.66 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 19/43] drm/amd/display: Fix double buffering in dcn2 ICSC Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 20/43] drm/amd/display: Driverside changes to support PSR in DMCUB Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 21/43] drm/amd/display: Double buffer dcn2 Gamut Remap Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 22/43] drm/amd/display: programing surface flip by dmcub Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 23/43] drm/amd/display: DMCUB FW Changes to support PSR Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 24/43] drm/amd/display: Indirect reg read macro with shift and mask Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 25/43] drm/amd/display: Refactor surface flip programming Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 26/43] drm/amd/display: Fix DMUB PSR command IDs Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 27/43] drm/amd/display: Add w/a to reset PHY before link training in verify_link_cap Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 28/43] drm/amd/display: rename _lvp to l_vp Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 29/43] drm/amd/display: Use SMU ClockTable Values for DML Calculations Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 30/43] drm/amd/display: Add default switch case for DCC Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 31/43] drm/amd/display: implement fw-driver interface for abm 2.4 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 32/43] drm/amd/display: remove psr state condition when psr exit case Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 33/43] drm/amd/display: 3.2.67 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 34/43] drm/amd/display: make PSR static screen entry within 30 ms Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 35/43] drm/amd/display: wait for test pattern after when all pipes are programmed Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 36/43] drm/amd/display: Add monitor patch for AUO dpcd issue Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 37/43] drm/amd/display: Enable double buffer for OTG_BLANK Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 38/43] drm/amd/display: Only program surface flip for video plane via dmcub Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 39/43] drm/amd/display: Use udelay to avoid context switch Rodrigo Siqueira
2020-01-10 15:01   ` Christian König
2020-01-10 18:47     ` Liu, Zhan
2020-01-10 21:16       ` Harry Wentland
2020-01-10 21:30         ` Harry Wentland
2020-01-11 16:34           ` Christian König
2020-01-13 17:12             ` Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 40/43] drm/amd/display: fixup DML dependencies Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 41/43] drm/amd/display: reallocate MST payload when link loss Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 42/43] drm/amd/display: 3.2.68 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 43/43] drm/amd/display: skip opp blank or unblank if test pattern enabled Rodrigo Siqueira

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