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* [PATCH v2 00/21] Add i.MXRT family support
@ 2020-01-10 14:46 Giulio Benetti
  2020-01-10 14:46 ` [PATCH v2 01/21] spl: fix entry_point equal to load_addr Giulio Benetti
                   ` (14 more replies)
  0 siblings, 15 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:46 UTC (permalink / raw)
  To: u-boot

This patchset add support for i.MXRT family starting from i.MXRT1050 SoC.
It provides:
- i.MXRT1050 SoC entry
- i.MXRT pinctrl driver
- i.MXRT serial driver tweaking
- i.MXRT sdram controller driver
- i.MXRT usdhc driver tweaking
- i.MXRT1050-evk initial support

It uses all DM clocks all around and it loads correctly a basic Linux zImage.

Changes:
V1->V2:
* added gpio driver adaption
* fixed potential failure on lpuart get_clock() if DM is not used
* introduced CONFIG_IMXRT and CONFIG_IMXRT1050 to prevent using ARCH_IMXRT
* removed lcd enabling from defconfig(it's still not available)
* added -u-boot.dtsi for imxrt1050-evk.dts board
* re-grouped some patch separating support for board and support for i.MXRT family

Giulio Benetti (21):
  spl: fix entry_point equal to load_addr
  armv7m: cache: add mmu_set_region_dcache_behaviour() stub for
    compatibility
  clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks
  clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB
  clk: imx: pllv3: add enable() support
  clk: imx: pllv3: add disable() support
  clk: imx: pllv3: add set_rate() support
  clk: imx: pllv3: add PLLV3_SYS support
  clk: imx: pllv3: add support for PLLV3_AV type
  clk: imx: pfd: add set_rate()
  clk: imx: add i.IMXRT1050 clk driver
  pinctrl: add i.MXRT driver
  gpio: mxc_gpio: add support for i.MXRT1050
  ARM: dts: imxrt1050: add dtsi file
  serial_lpuart: add clock enable if CONFIG_CLK is defined
  serial_lpuart: add support for i.MXRT
  ram: add SDRAM driver for i.MXRT SoCs
  mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statement
  mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhc
  imx: Add basic support for the NXP IMXRT10xx SoC family
  imx: imxrt1050-evk: Add support for the NXP i.MXRT1050-EVK

 arch/arm/Kconfig                              |  10 +
 arch/arm/Makefile                             |   4 +-
 arch/arm/cpu/armv7m/cache.c                   |   6 +
 arch/arm/dts/Makefile                         |   2 +
 arch/arm/dts/imxrt1050-evk-u-boot.dtsi        |  44 +
 arch/arm/dts/imxrt1050-evk.dts                | 200 ++++
 arch/arm/dts/imxrt1050.dtsi                   | 146 +++
 arch/arm/include/asm/arch-imxrt/clock.h       |  10 +
 arch/arm/include/asm/arch-imxrt/gpio.h        |  19 +
 arch/arm/include/asm/arch-imxrt/imx-regs.h    |  20 +
 arch/arm/include/asm/arch-imxrt/imxrt.h       |  11 +
 arch/arm/include/asm/arch-imxrt/sys_proto.h   |  11 +
 arch/arm/mach-imx/Makefile                    |   3 +-
 arch/arm/mach-imx/imxrt/Kconfig               |  25 +
 arch/arm/mach-imx/imxrt/Makefile              |   7 +
 arch/arm/mach-imx/imxrt/soc.c                 |  35 +
 board/freescale/imxrt1050-evk/Kconfig         |  22 +
 board/freescale/imxrt1050-evk/MAINTAINERS     |   6 +
 board/freescale/imxrt1050-evk/Makefile        |   6 +
 board/freescale/imxrt1050-evk/README          |  31 +
 board/freescale/imxrt1050-evk/imximage.cfg    |  36 +
 board/freescale/imxrt1050-evk/imxrt1050-evk.c |  81 ++
 common/spl/spl.c                              |   4 +-
 configs/imxrt1050-evk_defconfig               |  69 ++
 drivers/clk/imx/Kconfig                       |  16 +
 drivers/clk/imx/Makefile                      |   2 +
 drivers/clk/imx/clk-imxrt1050.c               | 292 +++++
 drivers/clk/imx/clk-pfd.c                     |  22 +
 drivers/clk/imx/clk-pllv3.c                   | 218 +++-
 drivers/gpio/mxc_gpio.c                       |   7 +-
 drivers/mmc/Kconfig                           |   2 +-
 drivers/mmc/fsl_esdhc_imx.c                   |  41 +-
 drivers/pinctrl/nxp/Kconfig                   |  14 +
 drivers/pinctrl/nxp/Makefile                  |   1 +
 drivers/pinctrl/nxp/pinctrl-imxrt.c           |  40 +
 drivers/ram/Kconfig                           |   8 +
 drivers/ram/Makefile                          |   2 +
 drivers/ram/imxrt_sdram.c                     | 439 ++++++++
 drivers/serial/serial_lpuart.c                |  31 +-
 include/configs/imxrt1050-evk.h               |  46 +
 include/dt-bindings/clock/imxrt1050-clock.h   |  65 ++
 include/dt-bindings/memory/imxrt-sdram.h      | 100 ++
 include/dt-bindings/pinctrl/pins-imxrt1050.h  | 993 ++++++++++++++++++
 include/fsl_lpuart.h                          |   3 +-
 44 files changed, 3111 insertions(+), 39 deletions(-)
 create mode 100644 arch/arm/dts/imxrt1050-evk-u-boot.dtsi
 create mode 100644 arch/arm/dts/imxrt1050-evk.dts
 create mode 100644 arch/arm/dts/imxrt1050.dtsi
 create mode 100644 arch/arm/include/asm/arch-imxrt/clock.h
 create mode 100644 arch/arm/include/asm/arch-imxrt/gpio.h
 create mode 100644 arch/arm/include/asm/arch-imxrt/imx-regs.h
 create mode 100644 arch/arm/include/asm/arch-imxrt/imxrt.h
 create mode 100644 arch/arm/include/asm/arch-imxrt/sys_proto.h
 create mode 100644 arch/arm/mach-imx/imxrt/Kconfig
 create mode 100644 arch/arm/mach-imx/imxrt/Makefile
 create mode 100644 arch/arm/mach-imx/imxrt/soc.c
 create mode 100644 board/freescale/imxrt1050-evk/Kconfig
 create mode 100644 board/freescale/imxrt1050-evk/MAINTAINERS
 create mode 100644 board/freescale/imxrt1050-evk/Makefile
 create mode 100644 board/freescale/imxrt1050-evk/README
 create mode 100644 board/freescale/imxrt1050-evk/imximage.cfg
 create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.c
 create mode 100644 configs/imxrt1050-evk_defconfig
 create mode 100644 drivers/clk/imx/clk-imxrt1050.c
 create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c
 create mode 100644 drivers/ram/imxrt_sdram.c
 create mode 100644 include/configs/imxrt1050-evk.h
 create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h
 create mode 100644 include/dt-bindings/memory/imxrt-sdram.h
 create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h

-- 
2.20.1

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 01/21] spl: fix entry_point equal to load_addr
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
@ 2020-01-10 14:46 ` Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:09   ` Lukasz Majewski
  2020-01-10 14:46 ` [PATCH v2 02/21] armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibility Giulio Benetti
                   ` (13 subsequent siblings)
  14 siblings, 2 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:46 UTC (permalink / raw)
  To: u-boot

At the moment entry_point is set to image_get_load(header) that sets it
to "load address" instead of "entry point", assuming entry_point is
equal to load_addr, but it's not true. Then load_addr is set to
"entry_point - header_size", but this is wrong too since load_addr is
not an entry point.

So use image_get_ep() for entry_point assignment and image_get_load()
for load_addr assignment.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
 common/spl/spl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index c1fce62b91..19085ad270 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -284,9 +284,9 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
 			spl_image->entry_point = image_get_ep(header);
 			spl_image->size = image_get_data_size(header);
 		} else {
-			spl_image->entry_point = image_get_load(header);
+			spl_image->entry_point = image_get_ep(header);
 			/* Load including the header */
-			spl_image->load_addr = spl_image->entry_point -
+			spl_image->load_addr = image_get_load(header) -
 				header_size;
 			spl_image->size = image_get_data_size(header) +
 				header_size;
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 02/21] armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibility
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
  2020-01-10 14:46 ` [PATCH v2 01/21] spl: fix entry_point equal to load_addr Giulio Benetti
@ 2020-01-10 14:46 ` Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:10   ` Lukasz Majewski
  2020-01-10 14:46 ` [PATCH v2 03/21] clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Giulio Benetti
                   ` (12 subsequent siblings)
  14 siblings, 2 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:46 UTC (permalink / raw)
  To: u-boot

Since some driver requires this function add it as an empty stub
when DCACHE is OFF.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
 arch/arm/cpu/armv7m/cache.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
index f4ba3ad50e..7353698557 100644
--- a/arch/arm/cpu/armv7m/cache.c
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -291,6 +291,12 @@ void flush_dcache_all(void)
 void invalidate_dcache_all(void)
 {
 }
+
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option)
+{
+}
+
 #endif
 
 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 03/21] clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
  2020-01-10 14:46 ` [PATCH v2 01/21] spl: fix entry_point equal to load_addr Giulio Benetti
  2020-01-10 14:46 ` [PATCH v2 02/21] armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibility Giulio Benetti
@ 2020-01-10 14:46 ` Giulio Benetti
  2020-01-15 12:47   ` sbabic at denx.de
  2020-01-10 14:46 ` [PATCH v2 04/21] clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB Giulio Benetti
                   ` (11 subsequent siblings)
  14 siblings, 1 reply; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:46 UTC (permalink / raw)
  To: u-boot

Better to register the 2 clock as 2 different drivers because they work
slightly differently depending on power_bit and powerup_set bits coming
on next patches.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
---
 drivers/clk/imx/clk-pllv3.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index fbb7b24d5e..d1e4c3fe30 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -13,7 +13,8 @@
 #include <clk.h>
 #include "clk.h"
 
-#define UBOOT_DM_CLK_IMX_PLLV3 "imx_clk_pllv3"
+#define UBOOT_DM_CLK_IMX_PLLV3_GENERIC	"imx_clk_pllv3_generic"
+#define UBOOT_DM_CLK_IMX_PLLV3_USB	"imx_clk_pllv3_usb"
 
 struct clk_pllv3 {
 	struct clk	clk;
@@ -24,7 +25,7 @@ struct clk_pllv3 {
 
 #define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
 
-static ulong clk_pllv3_get_rate(struct clk *clk)
+static ulong clk_pllv3_generic_get_rate(struct clk *clk)
 {
 	struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
 	unsigned long parent_rate = clk_get_parent_rate(clk);
@@ -35,7 +36,7 @@ static ulong clk_pllv3_get_rate(struct clk *clk)
 }
 
 static const struct clk_ops clk_pllv3_generic_ops = {
-	.get_rate       = clk_pllv3_get_rate,
+	.get_rate	= clk_pllv3_generic_get_rate,
 };
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
@@ -53,8 +54,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 
 	switch (type) {
 	case IMX_PLLV3_GENERIC:
+		drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
+		break;
 	case IMX_PLLV3_USB:
-		drv_name = UBOOT_DM_CLK_IMX_PLLV3;
+		drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
 		break;
 	default:
 		kfree(pll);
@@ -75,7 +78,14 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 }
 
 U_BOOT_DRIVER(clk_pllv3_generic) = {
-	.name	= UBOOT_DM_CLK_IMX_PLLV3,
+	.name	= UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
+	.id	= UCLASS_CLK,
+	.ops	= &clk_pllv3_generic_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(clk_pllv3_usb) = {
+	.name	= UBOOT_DM_CLK_IMX_PLLV3_USB,
 	.id	= UCLASS_CLK,
 	.ops	= &clk_pllv3_generic_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 04/21] clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (2 preceding siblings ...)
  2020-01-10 14:46 ` [PATCH v2 03/21] clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Giulio Benetti
@ 2020-01-10 14:46 ` Giulio Benetti
  2020-01-15 12:47   ` sbabic at denx.de
  2020-01-10 14:46 ` [PATCH v2 05/21] clk: imx: pllv3: add enable() support Giulio Benetti
                   ` (10 subsequent siblings)
  14 siblings, 1 reply; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:46 UTC (permalink / raw)
  To: u-boot

div_mask is different for GENERIC and USB pll, so set it according.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
---
 drivers/clk/imx/clk-pllv3.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index d1e4c3fe30..02c75c37ea 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -55,9 +55,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 	switch (type) {
 	case IMX_PLLV3_GENERIC:
 		drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
+		pll->div_shift = 0;
 		break;
 	case IMX_PLLV3_USB:
 		drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
+		pll->div_shift = 1;
 		break;
 	default:
 		kfree(pll);
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 05/21] clk: imx: pllv3: add enable() support
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (3 preceding siblings ...)
  2020-01-10 14:46 ` [PATCH v2 04/21] clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB Giulio Benetti
@ 2020-01-10 14:46 ` Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:14   ` Lukasz Majewski
  2020-01-10 14:46 ` [PATCH v2 06/21] clk: imx: pllv3: add disable() support Giulio Benetti
                   ` (9 subsequent siblings)
  14 siblings, 2 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:46 UTC (permalink / raw)
  To: u-boot

Before set_rate() pllv3 needs enable() to power the pll up.
Add enable() taking into account different power_bit and
different powerup_set, because some pll needs its power_bit to be
set or reset to be powered on.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
 drivers/clk/imx/clk-pllv3.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 02c75c37ea..d8cbe3dd4e 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -16,9 +16,13 @@
 #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC	"imx_clk_pllv3_generic"
 #define UBOOT_DM_CLK_IMX_PLLV3_USB	"imx_clk_pllv3_usb"
 
+#define BM_PLL_POWER		(0x1 << 12)
+
 struct clk_pllv3 {
 	struct clk	clk;
 	void __iomem	*base;
+	u32		power_bit;
+	bool		powerup_set;
 	u32		div_mask;
 	u32		div_shift;
 };
@@ -35,8 +39,24 @@ static ulong clk_pllv3_generic_get_rate(struct clk *clk)
 	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
 }
 
+static int clk_pllv3_generic_enable(struct clk *clk)
+{
+	struct clk_pllv3 *pll = to_clk_pllv3(clk);
+	u32 val;
+
+	val = readl(pll->base);
+	if (pll->powerup_set)
+		val |= pll->power_bit;
+	else
+		val &= ~pll->power_bit;
+	writel(val, pll->base);
+
+	return 0;
+}
+
 static const struct clk_ops clk_pllv3_generic_ops = {
 	.get_rate	= clk_pllv3_generic_get_rate,
+	.enable		= clk_pllv3_generic_enable,
 };
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
@@ -52,14 +72,18 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 	if (!pll)
 		return ERR_PTR(-ENOMEM);
 
+	pll->power_bit = BM_PLL_POWER;
+
 	switch (type) {
 	case IMX_PLLV3_GENERIC:
 		drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
 		pll->div_shift = 0;
+		pll->powerup_set = false;
 		break;
 	case IMX_PLLV3_USB:
 		drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
 		pll->div_shift = 1;
+		pll->powerup_set = true;
 		break;
 	default:
 		kfree(pll);
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 06/21] clk: imx: pllv3: add disable() support
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (4 preceding siblings ...)
  2020-01-10 14:46 ` [PATCH v2 05/21] clk: imx: pllv3: add enable() support Giulio Benetti
@ 2020-01-10 14:46 ` Giulio Benetti
  2020-01-15 12:47   ` sbabic at denx.de
  2020-01-10 14:46 ` [PATCH v2 07/21] clk: imx: pllv3: add set_rate() support Giulio Benetti
                   ` (8 subsequent siblings)
  14 siblings, 1 reply; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:46 UTC (permalink / raw)
  To: u-boot

Add disable() support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
---
 drivers/clk/imx/clk-pllv3.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index d8cbe3dd4e..9b37cd9cd9 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -54,9 +54,25 @@ static int clk_pllv3_generic_enable(struct clk *clk)
 	return 0;
 }
 
+static int clk_pllv3_generic_disable(struct clk *clk)
+{
+	struct clk_pllv3 *pll = to_clk_pllv3(clk);
+	u32 val;
+
+	val = readl(pll->base);
+	if (pll->powerup_set)
+		val &= ~pll->power_bit;
+	else
+		val |= pll->power_bit;
+	writel(val, pll->base);
+
+	return 0;
+}
+
 static const struct clk_ops clk_pllv3_generic_ops = {
 	.get_rate	= clk_pllv3_generic_get_rate,
 	.enable		= clk_pllv3_generic_enable,
+	.disable	= clk_pllv3_generic_disable,
 };
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 07/21] clk: imx: pllv3: add set_rate() support
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (5 preceding siblings ...)
  2020-01-10 14:46 ` [PATCH v2 06/21] clk: imx: pllv3: add disable() support Giulio Benetti
@ 2020-01-10 14:46 ` Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
  2020-01-10 14:46 ` [PATCH v2 08/21] clk: imx: pllv3: add PLLV3_SYS support Giulio Benetti
                   ` (7 subsequent siblings)
  14 siblings, 1 reply; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:46 UTC (permalink / raw)
  To: u-boot

Add generic set_rate() support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
---
 drivers/clk/imx/clk-pllv3.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 9b37cd9cd9..a721dbee94 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -17,6 +17,7 @@
 #define UBOOT_DM_CLK_IMX_PLLV3_USB	"imx_clk_pllv3_usb"
 
 #define BM_PLL_POWER		(0x1 << 12)
+#define BM_PLL_LOCK		(0x1 << 31)
 
 struct clk_pllv3 {
 	struct clk	clk;
@@ -39,6 +40,31 @@ static ulong clk_pllv3_generic_get_rate(struct clk *clk)
 	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
 }
 
+static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk_pllv3 *pll = to_clk_pllv3(clk);
+	unsigned long parent_rate = clk_get_parent_rate(clk);
+	u32 val, div;
+
+	if (rate == parent_rate * 22)
+		div = 1;
+	else if (rate == parent_rate * 20)
+		div = 0;
+	else
+		return -EINVAL;
+
+	val = readl(pll->base);
+	val &= ~(pll->div_mask << pll->div_shift);
+	val |= (div << pll->div_shift);
+	writel(val, pll->base);
+
+	/* Wait for PLL to lock */
+	while (!(readl(pll->base) & BM_PLL_LOCK))
+		;
+
+	return 0;
+}
+
 static int clk_pllv3_generic_enable(struct clk *clk)
 {
 	struct clk_pllv3 *pll = to_clk_pllv3(clk);
@@ -73,6 +99,7 @@ static const struct clk_ops clk_pllv3_generic_ops = {
 	.get_rate	= clk_pllv3_generic_get_rate,
 	.enable		= clk_pllv3_generic_enable,
 	.disable	= clk_pllv3_generic_disable,
+	.set_rate	= clk_pllv3_generic_set_rate,
 };
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 08/21] clk: imx: pllv3: add PLLV3_SYS support
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (6 preceding siblings ...)
  2020-01-10 14:46 ` [PATCH v2 07/21] clk: imx: pllv3: add set_rate() support Giulio Benetti
@ 2020-01-10 14:46 ` Giulio Benetti
  2020-01-15 12:47   ` sbabic at denx.de
  2020-01-10 14:46 ` [PATCH v2 09/21] clk: imx: pllv3: add support for PLLV3_AV type Giulio Benetti
                   ` (6 subsequent siblings)
  14 siblings, 1 reply; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:46 UTC (permalink / raw)
  To: u-boot

Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping
generic enable()/disable(). Add a different driver because ops are
different respect to GENERIC/USB.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
---
 drivers/clk/imx/clk-pllv3.c | 53 +++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index a721dbee94..d5087a104e 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -14,6 +14,7 @@
 #include "clk.h"
 
 #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC	"imx_clk_pllv3_generic"
+#define UBOOT_DM_CLK_IMX_PLLV3_SYS	"imx_clk_pllv3_sys"
 #define UBOOT_DM_CLK_IMX_PLLV3_USB	"imx_clk_pllv3_usb"
 
 #define BM_PLL_POWER		(0x1 << 12)
@@ -102,6 +103,46 @@ static const struct clk_ops clk_pllv3_generic_ops = {
 	.set_rate	= clk_pllv3_generic_set_rate,
 };
 
+static ulong clk_pllv3_sys_get_rate(struct clk *clk)
+{
+	struct clk_pllv3 *pll = to_clk_pllv3(clk);
+	unsigned long parent_rate = clk_get_parent_rate(clk);
+	u32 div = readl(pll->base) & pll->div_mask;
+
+	return parent_rate * div / 2;
+}
+
+static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk_pllv3 *pll = to_clk_pllv3(clk);
+	unsigned long parent_rate = clk_get_parent_rate(clk);
+	unsigned long min_rate = parent_rate * 54 / 2;
+	unsigned long max_rate = parent_rate * 108 / 2;
+	u32 val, div;
+
+	if (rate < min_rate || rate > max_rate)
+		return -EINVAL;
+
+	div = rate * 2 / parent_rate;
+	val = readl(pll->base);
+	val &= ~pll->div_mask;
+	val |= div;
+	writel(val, pll->base);
+
+	/* Wait for PLL to lock */
+	while (!(readl(pll->base) & BM_PLL_LOCK))
+		;
+
+	return 0;
+}
+
+static const struct clk_ops clk_pllv3_sys_ops = {
+	.enable 	= clk_pllv3_generic_enable,
+	.disable	= clk_pllv3_generic_disable,
+	.get_rate	= clk_pllv3_sys_get_rate,
+	.set_rate	= clk_pllv3_sys_set_rate,
+};
+
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 			  const char *parent_name, void __iomem *base,
 			  u32 div_mask)
@@ -123,6 +164,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 		pll->div_shift = 0;
 		pll->powerup_set = false;
 		break;
+	case IMX_PLLV3_SYS:
+		drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
+		pll->div_shift = 0;
+		pll->powerup_set = false;
+		break;
 	case IMX_PLLV3_USB:
 		drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
 		pll->div_shift = 1;
@@ -153,6 +199,13 @@ U_BOOT_DRIVER(clk_pllv3_generic) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
+U_BOOT_DRIVER(clk_pllv3_sys) = {
+	.name	= UBOOT_DM_CLK_IMX_PLLV3_SYS,
+	.id	= UCLASS_CLK,
+	.ops	= &clk_pllv3_sys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
 U_BOOT_DRIVER(clk_pllv3_usb) = {
 	.name	= UBOOT_DM_CLK_IMX_PLLV3_USB,
 	.id	= UCLASS_CLK,
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 09/21] clk: imx: pllv3: add support for PLLV3_AV type
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (7 preceding siblings ...)
  2020-01-10 14:46 ` [PATCH v2 08/21] clk: imx: pllv3: add PLLV3_SYS support Giulio Benetti
@ 2020-01-10 14:46 ` Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:20   ` Lukasz Majewski
  2020-01-10 14:47 ` [PATCH v2 10/21] clk: imx: pfd: add set_rate() Giulio Benetti
                   ` (5 subsequent siblings)
  14 siblings, 2 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:46 UTC (permalink / raw)
  To: u-boot

Add support for PLLV3 AV type.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
 drivers/clk/imx/clk-pllv3.c | 76 +++++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index d5087a104e..fc16416d5f 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <div64.h>
 #include <malloc.h>
 #include <clk-uclass.h>
 #include <dm/device.h>
@@ -16,6 +17,10 @@
 #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC	"imx_clk_pllv3_generic"
 #define UBOOT_DM_CLK_IMX_PLLV3_SYS	"imx_clk_pllv3_sys"
 #define UBOOT_DM_CLK_IMX_PLLV3_USB	"imx_clk_pllv3_usb"
+#define UBOOT_DM_CLK_IMX_PLLV3_AV	"imx_clk_pllv3_av"
+
+#define PLL_NUM_OFFSET		0x10
+#define PLL_DENOM_OFFSET	0x20
 
 #define BM_PLL_POWER		(0x1 << 12)
 #define BM_PLL_LOCK		(0x1 << 31)
@@ -143,6 +148,65 @@ static const struct clk_ops clk_pllv3_sys_ops = {
 	.set_rate	= clk_pllv3_sys_set_rate,
 };
 
+static ulong clk_pllv3_av_get_rate(struct clk *clk)
+{
+	struct clk_pllv3 *pll = to_clk_pllv3(clk);
+	unsigned long parent_rate = clk_get_parent_rate(clk);
+	u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
+	u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
+	u32 div = readl(pll->base) & pll->div_mask;
+	u64 temp64 = (u64)parent_rate;
+
+	temp64 *= mfn;
+	do_div(temp64, mfd);
+
+	return parent_rate * div + (unsigned long)temp64;
+}
+
+static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk_pllv3 *pll = to_clk_pllv3(clk);
+	unsigned long parent_rate = clk_get_parent_rate(clk);
+	unsigned long min_rate = parent_rate * 27;
+	unsigned long max_rate = parent_rate * 54;
+	u32 val, div;
+	u32 mfn, mfd = 1000000;
+	u32 max_mfd = 0x3FFFFFFF;
+	u64 temp64;
+
+	if (rate < min_rate || rate > max_rate)
+		return -EINVAL;
+
+	if (parent_rate <= max_mfd)
+		mfd = parent_rate;
+
+	div = rate / parent_rate;
+	temp64 = (u64)(rate - div * parent_rate);
+	temp64 *= mfd;
+	do_div(temp64, parent_rate);
+	mfn = temp64;
+
+	val = readl(pll->base);
+	val &= ~pll->div_mask;
+	val |= div;
+	writel(val, pll->base);
+	writel(mfn, pll->base + PLL_NUM_OFFSET);
+	writel(mfd, pll->base + PLL_DENOM_OFFSET);
+
+	/* Wait for PLL to lock */
+	while (!(readl(pll->base) & BM_PLL_LOCK))
+		;
+
+	return 0;
+}
+
+static const struct clk_ops clk_pllv3_av_ops = {
+	.enable		= clk_pllv3_generic_enable,
+	.disable	= clk_pllv3_generic_disable,
+	.get_rate	= clk_pllv3_av_get_rate,
+	.set_rate	= clk_pllv3_av_set_rate,
+};
+
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 			  const char *parent_name, void __iomem *base,
 			  u32 div_mask)
@@ -174,6 +238,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 		pll->div_shift = 1;
 		pll->powerup_set = true;
 		break;
+	case IMX_PLLV3_AV:
+		drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
+		pll->div_shift = 0;
+		pll->powerup_set = false;
+		break;
 	default:
 		kfree(pll);
 		return ERR_PTR(-ENOTSUPP);
@@ -212,3 +281,10 @@ U_BOOT_DRIVER(clk_pllv3_usb) = {
 	.ops	= &clk_pllv3_generic_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
+
+U_BOOT_DRIVER(clk_pllv3_av) = {
+	.name	= UBOOT_DM_CLK_IMX_PLLV3_AV,
+	.id	= UCLASS_CLK,
+	.ops	= &clk_pllv3_av_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 10/21] clk: imx: pfd: add set_rate()
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (8 preceding siblings ...)
  2020-01-10 14:46 ` [PATCH v2 09/21] clk: imx: pllv3: add support for PLLV3_AV type Giulio Benetti
@ 2020-01-10 14:47 ` Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
  2020-01-10 14:47 ` [PATCH v2 11/21] clk: imx: add i.IMXRT1050 clk driver Giulio Benetti
                   ` (4 subsequent siblings)
  14 siblings, 1 reply; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:47 UTC (permalink / raw)
  To: u-boot

Implement set_rate() for pfd.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
---
 drivers/clk/imx/clk-pfd.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c
index 188b2b3b90..4ae55f5a07 100644
--- a/drivers/clk/imx/clk-pfd.c
+++ b/drivers/clk/imx/clk-pfd.c
@@ -52,8 +52,30 @@ static unsigned long clk_pfd_recalc_rate(struct clk *clk)
 	return tmp;
 }
 
+static unsigned long clk_pfd_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk_pfd *pfd = to_clk_pfd(clk);
+	unsigned long parent_rate = clk_get_parent_rate(clk);
+	u64 tmp = parent_rate;
+	u8 frac;
+
+	tmp = tmp * 18 + rate / 2;
+	do_div(tmp, rate);
+	frac = tmp;
+	if (frac < 12)
+		frac = 12;
+	else if (frac > 35)
+		frac = 35;
+
+	writel(0x3f << (pfd->idx * 8), pfd->reg + CLR);
+	writel(frac << (pfd->idx * 8), pfd->reg + SET);
+
+	return 0;
+}
+
 static const struct clk_ops clk_pfd_ops = {
 	.get_rate	= clk_pfd_recalc_rate,
+	.set_rate	= clk_pfd_set_rate,
 };
 
 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 11/21] clk: imx: add i.IMXRT1050 clk driver
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (9 preceding siblings ...)
  2020-01-10 14:47 ` [PATCH v2 10/21] clk: imx: pfd: add set_rate() Giulio Benetti
@ 2020-01-10 14:47 ` Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:23   ` Lukasz Majewski
  2020-01-10 14:47 ` [PATCH v2 12/21] pinctrl: add i.MXRT driver Giulio Benetti
                   ` (3 subsequent siblings)
  14 siblings, 2 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:47 UTC (permalink / raw)
  To: u-boot

Add i.MXRT1050 clk driver support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
 drivers/clk/imx/Kconfig                     |  16 ++
 drivers/clk/imx/Makefile                    |   2 +
 drivers/clk/imx/clk-imxrt1050.c             | 292 ++++++++++++++++++++
 include/dt-bindings/clock/imxrt1050-clock.h |  65 +++++
 4 files changed, 375 insertions(+)
 create mode 100644 drivers/clk/imx/clk-imxrt1050.c
 create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 2f149ff6f8..059bc2fbb9 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -68,3 +68,19 @@ config CLK_IMX8MP
 	select CLK_CCF
 	help
 	  This enables support clock driver for i.MX8MP platforms.
+
+config SPL_CLK_IMXRT1050
+	bool "SPL clock support for i.MXRT1050"
+	depends on ARCH_IMXRT && SPL
+	select SPL_CLK
+	select SPL_CLK_CCF
+	help
+	  This enables SPL DM/DTS support for clock driver in i.MXRT1050
+
+config CLK_IMXRT1050
+	bool "Clock support for i.MXRT1050"
+	depends on ARCH_IMXRT
+	select CLK
+	select CLK_CCF
+	help
+	  This enables support clock driver for i.MXRT1050 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 255a87b18e..1e8a49d0f3 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -16,3 +16,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
 				clk-composite-8m.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
 				clk-composite-8m.o
+
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
new file mode 100644
index 0000000000..44ca52c013
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dt-bindings/clock/imxrt1050-clock.h>
+
+#include "clk.h"
+
+static ulong imxrt1050_clk_get_rate(struct clk *clk)
+{
+	struct clk *c;
+	int ret;
+
+	debug("%s(#%lu)\n", __func__, clk->id);
+
+	ret = clk_get_by_id(clk->id, &c);
+	if (ret)
+		return ret;
+
+	return clk_get_rate(c);
+}
+
+static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk *c;
+	int ret;
+
+	debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+	ret = clk_get_by_id(clk->id, &c);
+	if (ret)
+		return ret;
+
+	return clk_set_rate(c, rate);
+}
+
+static int __imxrt1050_clk_enable(struct clk *clk, bool enable)
+{
+	struct clk *c;
+	int ret;
+
+	debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+	ret = clk_get_by_id(clk->id, &c);
+	if (ret)
+		return ret;
+
+	if (enable)
+		ret = clk_enable(c);
+	else
+		ret = clk_disable(c);
+
+	return ret;
+}
+
+static int imxrt1050_clk_disable(struct clk *clk)
+{
+	return __imxrt1050_clk_enable(clk, 0);
+}
+
+static int imxrt1050_clk_enable(struct clk *clk)
+{
+	return __imxrt1050_clk_enable(clk, 1);
+}
+
+static struct clk_ops imxrt1050_clk_ops = {
+	.set_rate = imxrt1050_clk_set_rate,
+	.get_rate = imxrt1050_clk_get_rate,
+	.enable = imxrt1050_clk_enable,
+	.disable = imxrt1050_clk_disable,
+};
+
+static const char * const pll_ref_sels[] = {"osc", "dummy", };
+static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", };
+static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", };
+static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
+static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", };
+
+static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", };
+static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
+static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
+static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
+static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
+static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"};
+
+static int imxrt1050_clk_probe(struct udevice *dev)
+{
+	void *base;
+
+	/* Anatop clocks */
+	base = (void *)ANATOP_BASE_ADDR;
+
+	clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
+	       imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
+			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,
+	       imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
+			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,
+	       imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
+			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,
+	       imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
+			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+
+	clk_dm(IMXRT1050_CLK_PLL1_ARM,
+	       imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
+			     base + 0x0, 0x7f));
+	clk_dm(IMXRT1050_CLK_PLL2_SYS,
+	       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
+			     base + 0x30, 0x1));
+	clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,
+	       imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
+			     "pll3_usb_otg_ref_sel",
+			     base + 0x10, 0x1));
+	clk_dm(IMXRT1050_CLK_PLL5_VIDEO,
+	       imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
+			     base + 0xa0, 0x7f));
+
+	/* PLL bypass out */
+	clk_dm(IMXRT1050_CLK_PLL1_BYPASS,
+	       imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
+				 pll1_bypass_sels,
+				 ARRAY_SIZE(pll1_bypass_sels),
+				 CLK_SET_RATE_PARENT));
+	clk_dm(IMXRT1050_CLK_PLL2_BYPASS,
+	       imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
+				 pll2_bypass_sels,
+				 ARRAY_SIZE(pll2_bypass_sels),
+				 CLK_SET_RATE_PARENT));
+	clk_dm(IMXRT1050_CLK_PLL3_BYPASS,
+	       imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
+				 pll3_bypass_sels,
+				 ARRAY_SIZE(pll3_bypass_sels),
+				 CLK_SET_RATE_PARENT));
+	clk_dm(IMXRT1050_CLK_PLL5_BYPASS,
+	       imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
+				 pll5_bypass_sels,
+				 ARRAY_SIZE(pll5_bypass_sels),
+				 CLK_SET_RATE_PARENT));
+
+	clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,
+	       imx_clk_divider("video_post_div_sel", "pll5_video",
+			       base + 0xa0, 19, 2));
+	clk_dm(IMXRT1050_CLK_VIDEO_DIV,
+	       imx_clk_divider("video_div", "video_post_div_sel",
+			       base + 0x170, 30, 2));
+
+	clk_dm(IMXRT1050_CLK_PLL3_80M,
+	       imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6));
+
+	clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,
+	       imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
+	clk_dm(IMXRT1050_CLK_PLL2_PFD1_594M,
+	       imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
+	clk_dm(IMXRT1050_CLK_PLL2_PFD2_396M,
+	       imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
+	clk_dm(IMXRT1050_CLK_PLL3_PFD1_664_62M,
+	       imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0,
+			   1));
+	clk_dm(IMXRT1050_CLK_PLL3_PFD3_454_74M,
+	       imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0,
+			   3));
+
+	/* CCM clocks */
+	base = dev_read_addr_ptr(dev);
+	if (base == (void *)FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	clk_dm(IMXRT1050_CLK_ARM_PODF,
+	       imx_clk_divider("arm_podf", "pll1_arm",
+			       base + 0x10, 0, 3));
+
+	clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,
+	       imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
+			   pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
+	clk_dm(IMXRT1050_CLK_PERIPH_SEL,
+	       imx_clk_mux("periph_sel", base + 0x14, 25, 1,
+			   periph_sels, ARRAY_SIZE(periph_sels)));
+	clk_dm(IMXRT1050_CLK_USDHC1_SEL,
+	       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+	clk_dm(IMXRT1050_CLK_USDHC2_SEL,
+	       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+	clk_dm(IMXRT1050_CLK_LPUART_SEL,
+	       imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
+			   lpuart_sels, ARRAY_SIZE(lpuart_sels)));
+	clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,
+	       imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
+			   semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
+	clk_dm(IMXRT1050_CLK_SEMC_SEL,
+	       imx_clk_mux("semc_sel", base + 0x14, 6, 1,
+			   semc_sels, ARRAY_SIZE(semc_sels)));
+	clk_dm(IMXRT1050_CLK_LCDIF_SEL,
+	       imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
+			   lcdif_sels, ARRAY_SIZE(lcdif_sels)));
+
+	clk_dm(IMXRT1050_CLK_AHB_PODF,
+	       imx_clk_divider("ahb_podf", "periph_sel",
+			       base + 0x14, 10, 3));
+	clk_dm(IMXRT1050_CLK_USDHC1_PODF,
+	       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+			       base + 0x24, 11, 3));
+	clk_dm(IMXRT1050_CLK_USDHC2_PODF,
+	       imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+			       base + 0x24, 16, 3));
+	clk_dm(IMXRT1050_CLK_LPUART_PODF,
+	       imx_clk_divider("lpuart_podf", "lpuart_sel",
+			       base + 0x24, 0, 6));
+	clk_dm(IMXRT1050_CLK_SEMC_PODF,
+	       imx_clk_divider("semc_podf", "semc_sel",
+			       base + 0x14, 16, 3));
+	clk_dm(IMXRT1050_CLK_LCDIF_PRED,
+	       imx_clk_divider("lcdif_pred", "lcdif_sel",
+			       base + 0x38, 12, 3));
+	clk_dm(IMXRT1050_CLK_LCDIF_PODF,
+	       imx_clk_divider("lcdif_podf", "lcdif_pred",
+			       base + 0x18, 23, 3));
+
+	clk_dm(IMXRT1050_CLK_USDHC1,
+	       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+	clk_dm(IMXRT1050_CLK_USDHC2,
+	       imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+	clk_dm(IMXRT1050_CLK_LPUART1,
+	       imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
+	clk_dm(IMXRT1050_CLK_SEMC,
+	       imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
+	clk_dm(IMXRT1050_CLK_LCDIF,
+	       imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+
+#ifdef CONFIG_SPL_BUILD
+	struct clk *clk, *clk1;
+
+	/* bypass pll1 before setting its rate */
+	clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
+	clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
+	clk_set_parent(clk1, clk);
+
+	clk_get_by_id(IMXRT1050_CLK_PLL1_ARM, &clk);
+	clk_enable(clk);
+	clk_set_rate(clk, 1056000000UL);
+
+	clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
+	clk_set_parent(clk1, clk);
+
+	clk_get_by_id(IMXRT1050_CLK_SEMC_SEL, &clk1);
+	clk_get_by_id(IMXRT1050_CLK_SEMC_ALT_SEL, &clk);
+	clk_set_parent(clk1, clk);
+
+	clk_get_by_id(IMXRT1050_CLK_PLL2_SYS, &clk);
+	clk_enable(clk);
+	clk_set_rate(clk, 528000000UL);
+
+	clk_get_by_id(IMXRT1050_CLK_PLL2_BYPASS, &clk1);
+	clk_set_parent(clk1, clk);
+
+	/* Configure PLL3_USB_OTG to 480MHz */
+	clk_get_by_id(IMXRT1050_CLK_PLL3_USB_OTG, &clk);
+	clk_enable(clk);
+	clk_set_rate(clk, 480000000UL);
+
+	clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1);
+	clk_set_parent(clk1, clk);
+
+#endif
+
+	return 0;
+}
+
+static const struct udevice_id imxrt1050_clk_ids[] = {
+	{ .compatible = "fsl,imxrt1050-ccm" },
+	{ },
+};
+
+U_BOOT_DRIVER(imxrt1050_clk) = {
+	.name = "clk_imxrt1050",
+	.id = UCLASS_CLK,
+	.of_match = imxrt1050_clk_ids,
+	.ops = &imxrt1050_clk_ops,
+	.probe = imxrt1050_clk_probe,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h
new file mode 100644
index 0000000000..c174f90c1a
--- /dev/null
+++ b/include/dt-bindings/clock/imxrt1050-clock.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H
+#define __DT_BINDINGS_CLOCK_IMXRT1050_H
+
+#define IMXRT1050_CLK_DUMMY			0
+#define IMXRT1050_CLK_CKIL			1
+#define IMXRT1050_CLK_CKIH			2
+#define IMXRT1050_CLK_OSC			3
+#define IMXRT1050_CLK_PLL2_PFD0_352M		4
+#define IMXRT1050_CLK_PLL2_PFD1_594M		5
+#define IMXRT1050_CLK_PLL2_PFD2_396M		6
+#define IMXRT1050_CLK_PLL3_PFD0_720M		7
+#define IMXRT1050_CLK_PLL3_PFD1_664_62M		8
+#define IMXRT1050_CLK_PLL3_PFD2_508_24M		9
+#define IMXRT1050_CLK_PLL3_PFD3_454_74M		10
+#define IMXRT1050_CLK_PLL2_198M			11
+#define IMXRT1050_CLK_PLL3_120M			12
+#define IMXRT1050_CLK_PLL3_80M			13
+#define IMXRT1050_CLK_PLL3_60M			14
+#define IMXRT1050_CLK_PLL1_BYPASS		15
+#define IMXRT1050_CLK_PLL2_BYPASS		16
+#define IMXRT1050_CLK_PLL3_BYPASS		17
+#define IMXRT1050_CLK_PLL5_BYPASS		19
+#define IMXRT1050_CLK_PLL1_REF_SEL		20
+#define IMXRT1050_CLK_PLL2_REF_SEL		21
+#define IMXRT1050_CLK_PLL3_REF_SEL		22
+#define IMXRT1050_CLK_PLL5_REF_SEL		23
+#define IMXRT1050_CLK_PRE_PERIPH_SEL		24
+#define IMXRT1050_CLK_PERIPH_SEL		25
+#define IMXRT1050_CLK_SEMC_ALT_SEL		26
+#define IMXRT1050_CLK_SEMC_SEL			27
+#define IMXRT1050_CLK_USDHC1_SEL		28
+#define IMXRT1050_CLK_USDHC2_SEL		29
+#define IMXRT1050_CLK_LPUART_SEL		30
+#define IMXRT1050_CLK_LCDIF_SEL			31
+#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL	32
+#define IMXRT1050_CLK_VIDEO_DIV			33
+#define IMXRT1050_CLK_ARM_PODF			34
+#define IMXRT1050_CLK_LPUART_PODF		35
+#define IMXRT1050_CLK_USDHC1_PODF		36
+#define IMXRT1050_CLK_USDHC2_PODF		37
+#define IMXRT1050_CLK_SEMC_PODF			38
+#define IMXRT1050_CLK_AHB_PODF			39
+#define IMXRT1050_CLK_LCDIF_PRED		40
+#define IMXRT1050_CLK_LCDIF_PODF		41
+#define IMXRT1050_CLK_USDHC1			42
+#define IMXRT1050_CLK_USDHC2			43
+#define IMXRT1050_CLK_LPUART1			44
+#define IMXRT1050_CLK_SEMC			45
+#define IMXRT1050_CLK_LCDIF			46
+#define IMXRT1050_CLK_PLL1_ARM			47
+#define IMXRT1050_CLK_PLL2_SYS			48
+#define IMXRT1050_CLK_PLL3_USB_OTG		49
+#define IMXRT1050_CLK_PLL4_AUDIO		50
+#define IMXRT1050_CLK_PLL5_VIDEO		51
+#define IMXRT1050_CLK_PLL6_ENET			52
+#define IMXRT1050_CLK_PLL7_USB_HOST		53
+#define IMXRT1050_CLK_END			54
+
+#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 12/21] pinctrl: add i.MXRT driver
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (10 preceding siblings ...)
  2020-01-10 14:47 ` [PATCH v2 11/21] clk: imx: add i.IMXRT1050 clk driver Giulio Benetti
@ 2020-01-10 14:47 ` Giulio Benetti
  2020-01-15 12:47   ` sbabic at denx.de
  2020-01-28  8:27   ` Lukasz Majewski
  2020-01-10 14:47 ` [PATCH v2 13/21] gpio: mxc_gpio: add support for i.MXRT1050 Giulio Benetti
                   ` (2 subsequent siblings)
  14 siblings, 2 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:47 UTC (permalink / raw)
  To: u-boot

Add i.MXRT pinctrl driver.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
 drivers/pinctrl/nxp/Kconfig         | 14 ++++++++++
 drivers/pinctrl/nxp/Makefile        |  1 +
 drivers/pinctrl/nxp/pinctrl-imxrt.c | 40 +++++++++++++++++++++++++++++
 3 files changed, 55 insertions(+)
 create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c

diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index f2e67ca231..ec55351e61 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -99,6 +99,20 @@ config PINCTRL_MXS
 	  familiy, e.g. i.MX28. This feature depends on device tree
 	  configuration.
 
+config PINCTRL_IMXRT
+	bool "IMXRT pinctrl driver"
+	depends on ARCH_IMXRT && PINCTRL_FULL
+	select DEVRES
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the imxrt pinctrl driver
+
+	  This provides a simple pinctrl driver for i.MXRT SoC familiy.
+	  This feature depends on device tree configuration. This driver
+	  is different from the linux one, this is a simple implementation,
+	  only parses the 'fsl,pins' property and configure related
+	  registers.
+
 config PINCTRL_VYBRID
 	bool "Vybrid (vf610) pinctrl driver"
 	depends on ARCH_VF610 && PINCTRL_FULL
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index b86448aac9..066ca75b65 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_IMX8)		+= pinctrl-imx8.o
 obj-$(CONFIG_PINCTRL_IMX8M)		+= pinctrl-imx8m.o
 obj-$(CONFIG_PINCTRL_MXS)		+= pinctrl-mxs.o
 obj-$(CONFIG_PINCTRL_VYBRID)		+= pinctrl-vf610.o
+obj-$(CONFIG_PINCTRL_IMXRT)		+= pinctrl-imxrt.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imxrt.c b/drivers/pinctrl/nxp/pinctrl-imxrt.c
new file mode 100644
index 0000000000..4a93941927
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imxrt.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+static struct imx_pinctrl_soc_info imxrt_pinctrl_soc_info = {
+	.flags = ZERO_OFFSET_VALID,
+};
+
+static int imxrt_pinctrl_probe(struct udevice *dev)
+{
+	struct imx_pinctrl_soc_info *info =
+		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+	return imx_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id imxrt_pinctrl_match[] = {
+	{ .compatible = "fsl,imxrt-iomuxc",
+	  .data = (ulong)&imxrt_pinctrl_soc_info },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imxrt_pinctrl) = {
+	.name = "imxrt-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(imxrt_pinctrl_match),
+	.probe = imxrt_pinctrl_probe,
+	.remove = imx_pinctrl_remove,
+	.priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+	.ops = &imx_pinctrl_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 13/21] gpio: mxc_gpio: add support for i.MXRT1050
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (11 preceding siblings ...)
  2020-01-10 14:47 ` [PATCH v2 12/21] pinctrl: add i.MXRT driver Giulio Benetti
@ 2020-01-10 14:47 ` Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:27   ` Lukasz Majewski
  2020-01-10 14:47 ` [PATCH v2 14/21] ARM: dts: imxrt1050: add dtsi file Giulio Benetti
  2020-01-10 14:47 ` [PATCH v2 15/21] serial_lpuart: add clock enable if CONFIG_CLK is defined Giulio Benetti
  14 siblings, 2 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:47 UTC (permalink / raw)
  To: u-boot

Add i.MXRT1050 support, there are 5 GPIO banks.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
V1->V2:
* introduced this patch
---
 drivers/gpio/mxc_gpio.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 6592d141d3..c924e52f07 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -41,14 +41,15 @@ static unsigned long gpio_ports[] = {
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
-		defined(CONFIG_ARCH_IMX8)
+		defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
 	[3] = GPIO4_BASE_ADDR,
 #endif
 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
-		defined(CONFIG_ARCH_IMX8)
+		defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
 	[4] = GPIO5_BASE_ADDR,
-#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M))
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+		defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT1050))
 	[5] = GPIO6_BASE_ADDR,
 #endif
 #endif
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 14/21] ARM: dts: imxrt1050: add dtsi file
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (12 preceding siblings ...)
  2020-01-10 14:47 ` [PATCH v2 13/21] gpio: mxc_gpio: add support for i.MXRT1050 Giulio Benetti
@ 2020-01-10 14:47 ` Giulio Benetti
  2020-01-15 12:47   ` sbabic at denx.de
  2020-01-28  8:31   ` Lukasz Majewski
  2020-01-10 14:47 ` [PATCH v2 15/21] serial_lpuart: add clock enable if CONFIG_CLK is defined Giulio Benetti
  14 siblings, 2 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:47 UTC (permalink / raw)
  To: u-boot

Add dtsi file for i.MXRT1050.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
 arch/arm/dts/imxrt1050.dtsi                  | 146 +++
 include/dt-bindings/pinctrl/pins-imxrt1050.h | 993 +++++++++++++++++++
 2 files changed, 1139 insertions(+)
 create mode 100644 arch/arm/dts/imxrt1050.dtsi
 create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h

diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
new file mode 100644
index 0000000000..b1d98e6feb
--- /dev/null
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt1050-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/memory/imxrt-sdram.h>
+
+/ {
+	aliases {
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		mmc0 = &usdhc1;
+		serial0 = &lpuart1;
+	};
+
+	clocks {
+		u-boot,dm-spl;
+
+		osc {
+			u-boot,dm-spl;
+			compatible = "fsl,imx-osc", "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <24000000>;
+		};
+	};
+
+	soc {
+		u-boot,dm-spl;
+
+		semc: semc at 402f0000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-semc";
+			reg = <0x402f0000 0x4000>;
+			clocks = <&clks IMXRT1050_CLK_SEMC>;
+			pinctrl-0 = <&pinctrl_semc>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		lpuart1: serial at 40184000 {
+			compatible = "fsl,imxrt-lpuart";
+			reg = <0x40184000 0x4000>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMXRT1050_CLK_LPUART1>;
+			clock-names = "per";
+			status = "disabled";
+		};
+
+		iomuxc: iomuxc at 401f8000 {
+			compatible = "fsl,imxrt-iomuxc";
+			reg = <0x401f8000 0x4000>;
+			fsl,mux_mask = <0x7>;
+		};
+
+		clks: ccm at 400fc000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt1050-ccm";
+			reg = <0x400fc000 0x4000>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			#clock-cells = <1>;
+		};
+
+		usdhc1: usdhc at 402c0000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-usdhc";
+			reg = <0x402c0000 0x10000>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMXRT1050_CLK_USDHC1>;
+			clock-names = "per";
+			bus-width = <4>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		gpio1: gpio at 401b8000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401b8000 0x4000>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio at 401bc000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401bc000 0x4000>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio at 401c0000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401c0000 0x4000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio4: gpio at 401c4000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401c4000 0x4000>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio5: gpio at 400c0000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x400c0000 0x4000>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/include/dt-bindings/pinctrl/pins-imxrt1050.h b/include/dt-bindings/pinctrl/pins-imxrt1050.h
new file mode 100644
index 0000000000..a29031ab3d
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pins-imxrt1050.h
@@ -0,0 +1,993 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
+#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
+
+#define IMX_PAD_SION	0x40000000
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00				0x014 0x204 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A			0x014 0x204 0x494 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK				0x014 0x204 0x500 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2				0x014 0x204 0x60C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00				0x014 0x204 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00				0x014 0x204 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01				0x018 0x208 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B			0x018 0x208 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0				0x018 0x208 0x4FC 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3				0x018 0x208 0x610 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01				0x018 0x208 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01				0x018 0x208 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02				0x01C 0x20C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A			0x01C 0x20C 0x498 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO				0x01C 0x20C 0x508 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4				0x01C 0x20C 0x614 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02				0x01C 0x20C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02				0x01C 0x20C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03				0x020 0x210 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B			0x020 0x210 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI				0x020 0x210 0x504 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5				0x020 0x210 0x618 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03				0x020 0x210 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03				0x020 0x210 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04				0x024 0x214 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A			0x024 0x214 0x49C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA			0x024 0x214 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6				0x024 0x214 0x61C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04				0x024 0x214 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04				0x024 0x214 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05				0x028 0x218 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B			0x028 0x218 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC			0x028 0x218 0x5C4 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7				0x028 0x218 0x620 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05				0x028 0x218 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05				0x028 0x218 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06				0x02C 0x21C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A			0x02C 0x21C 0x478 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK			0x02C 0x21C 0x5C0 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8				0x02C 0x21C 0x624 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06				0x02C 0x21C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06				0x02C 0x21C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07				0x030 0x220 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B			0x030 0x220 0x488 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK				0x030 0x220 0x5B0 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9				0x030 0x220 0x628 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07				0x030 0x220 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07				0x030 0x220 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00				0x034 0x224 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A			0x034 0x224 0x47C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA			0x034 0x224 0x5B8 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17			0x034 0x224 0x62C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08				0x034 0x224 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08				0x034 0x224 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00				0x038 0x228 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B			0x038 0x228 0x48C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC			0x038 0x228 0x5BC 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX				0x038 0x228 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09				0x038 0x228 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09				0x038 0x228 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01				0x03C 0x22C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A			0x03C 0x22C 0x480 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK			0x03C 0x22C 0x5B4 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX				0x03C 0x22C 0x450 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10				0x03C 0x22C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10				0x03C 0x22C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02				0x040 0x230 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B			0x040 0x230 0x490 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA				0x040 0x230 0x4E8 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B			0x040 0x230 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11				0x040 0x230 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11				0x040 0x230 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03				0x044 0x234 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24			0x044 0x234 0x640 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL				0x044 0x234 0x4E4 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP				0x044 0x234 0x5D8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A			0x044 0x234 0x454 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12				0x044 0x234 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04				0x048 0x238 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25			0x048 0x238 0x650 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD				0x048 0x238 0x53C 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT				0x048 0x238 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B			0x048 0x238 0x464 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13				0x048 0x238 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05				0x04C 0x23C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19			0x04C 0x23C 0x654 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD				0x04C 0x23C 0x538 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT				0x04C 0x23C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1				0x04C 0x23C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14				0x04C 0x23C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06				0x050 0x240 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20			0x050 0x240 0x634 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B			0x050 0x240 0x534 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT				0x050 0x240 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0				0x050 0x240 0x57C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15				0x050 0x240 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07				0x054 0x244 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21			0x054 0x244 0x658 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B			0x054 0x244 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN				0x054 0x244 0x5C8 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1				0x054 0x244 0x580 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16				0x054 0x244 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08				0x058 0x248 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A			0x058 0x248 0x4A0 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B			0x058 0x248 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX				0x058 0x248 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2				0x058 0x248 0x584 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17				0x058 0x248 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09				0x05C 0x24C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B			0x05C 0x24C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B			0x05C 0x24C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX				0x05C 0x24C 0x44C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3				0x05C 0x24C 0x588 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18				0x05C 0x24C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL			0x05C 0x24C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11				0x060 0x250 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A			0x060 0x250 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD				0x060 0x250 0x544 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01			0x060 0x250 0x438 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0				0x060 0x250 0x56C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19				0x060 0x250 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5				0x060 0x250 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12				0x064 0x254 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B			0x064 0x254 0x484 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD				0x064 0x254 0x540 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00			0x064 0x254 0x434 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0				0x064 0x254 0x570 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20				0x064 0x254 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0				0x068 0x258 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A			0x068 0x258 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA				0x068 0x258 0x4E0 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01			0x068 0x258 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2				0x068 0x258 0x574 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21				0x068 0x258 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1				0x06C 0x25C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B			0x06C 0x25C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL				0x06C 0x25C 0x4DC 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00			0x06C 0x25C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3				0x06C 0x25C 0x578 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22				0x06C 0x25C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10				0x070 0x260 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A			0x070 0x260 0x458 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD				0x070 0x260 0x54C 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN				0x070 0x260 0x43C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2			0x070 0x260 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23				0x070 0x260 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS				0x074 0x264 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B			0x074 0x264 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD				0x074 0x264 0x548 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN				0x074 0x264 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1			0x074 0x264 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24				0x074 0x264 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS				0x078 0x268 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A			0x078 0x268 0x45C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD				0x078 0x268 0x554 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK				0x078 0x268 0x448 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK			0x078 0x268 0x42C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25				0x078 0x268 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK				0x07C 0x26C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B			0x07C 0x26C 0x46C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD				0x07C 0x26C 0x550 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER				0x07C 0x26C 0x440 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12				0x07C 0x26C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26				0x07C 0x26C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE				0x080 0x270 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A			0x080 0x270 0x460 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B			0x080 0x270 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK				0x080 0x270 0x4F0 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13				0x080 0x270 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27				0x080 0x270 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE				0x084 0x274 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B			0x084 0x274 0x470 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B			0x084 0x274 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO				0x084 0x274 0x4F8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14				0x084 0x274 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28				0x084 0x274 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0				0x088 0x278 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A			0x088 0x278 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B			0x088 0x278 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI				0x088 0x278 0x4F4 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15				0x088 0x278 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29				0x088 0x278 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08				0x08C 0x27C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B			0x08C 0x27C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B			0x08C 0x27C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0				0x08C 0x27C 0x4EC 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23				0x08C 0x27C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30				0x08C 0x27C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09				0x090 0x280 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A			0x090 0x280 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD				0x090 0x280 0x55C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1				0x090 0x280 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22				0x090 0x280 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31				0x090 0x280 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10				0x094 0x284 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B			0x094 0x284 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD				0x094 0x284 0x558 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY			0x094 0x284 0x3FC 0x3 0x4
+#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21				0x094 0x284 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18				0x094 0x284 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11				0x098 0x288 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A			0x098 0x288 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B			0x098 0x288 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA			0x098 0x288 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20				0x098 0x288 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19				0x098 0x288 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12				0x09C 0x28C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B			0x09C 0x28C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT			0x09C 0x28C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC			0x09C 0x28C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19				0x09C 0x28C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20				0x09C 0x28C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13				0x0A0 0x290 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18			0x0A0 0x290 0x630 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1			0x0A0 0x290 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK			0x0A0 0x290 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18				0x0A0 0x290 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21				0x0A0 0x290 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B				0x0A0 0x290 0x5D4 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14				0x0A4 0x294 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22			0x0A4 0x294 0x638 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2			0x0A4 0x294 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA			0x0A4 0x294 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17				0x0A4 0x294 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22				0x0A4 0x294 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP				0x0A4 0x294 0x5D8 0x6 0x1
+
+#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15				0x0A8 0x298 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23			0x0A8 0x298 0x63C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3			0x0A8 0x298 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK				0x0A8 0x298 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16				0x0A8 0x298 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23				0x0A8 0x298 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP				0x0A8 0x298 0x608 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01				0x0AC 0x29C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A			0x0AC 0x29C 0x454 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD				0x0AC 0x29C 0x564 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK			0x0AC 0x29C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD				0x0AC 0x29C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24				0x0AC 0x29C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT			0x0AC 0x29C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS				0x0B0 0x2A0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B			0x0B0 0x2A0 0x464 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD				0x0B0 0x2A0 0x560 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC			0x0B0 0x2A0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B				0x0B0 0x2A0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25				0x0B0 0x2A0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B				0x0B0 0x2A0 0x5E0 0x6 0x1
+
+#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY				0x0B4 0x2A4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2			0x0B4 0x2A4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2				0x0B4 0x2A4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC				0x0B4 0x2A4 0x5CC 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC				0x0B4 0x2A4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26				0x0B4 0x2A4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B			0x0B4 0x2A4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0				0x0B8 0x2A8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1			0x0B8 0x2A8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3				0x0B8 0x2A8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR			0x0B8 0x2A8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO				0x0B8 0x2A8 0x430 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27				0x0B8 0x2A8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT			0x0B8 0x2A8 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A			0x0BC 0x2AC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14			0x0BC 0x2AC 0x644 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K			0x0BC 0x2AC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID			0x0BC 0x2AC 0x3F8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS			0x0BC 0x2AC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00			0x0BC 0x2AC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B			0x0BC 0x2AC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK			0x0BC 0x2AC 0x510 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B			0x0C0 0x2B0 0x484 0x0 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15			0x0C0 0x2B0 0x648 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M			0x0C0 0x2B0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID			0x0C0 0x2B0 0x3F4 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS			0x0C0 0x2B0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01			0x0C0 0x2B0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B				0x0C0 0x2B0 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO			0x0C0 0x2B0 0x518 0x7 0x1
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX			0x0C4 0x2B4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16			0x0C4 0x2B4 0x64C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD			0x0C4 0x2B4 0x554 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR			0x0C4 0x2B4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X			0x0C4 0x2B4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02			0x0C4 0x2B4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ			0x0C4 0x2B4 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI			0x0C4 0x2B4 0x514 0x7 0x1
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX			0x0C8 0x2B8 0x450 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17			0x0C8 0x2B8 0x62C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD			0x0C8 0x2B8 0x550 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC			0x0C8 0x2B8 0x5D0 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X			0x0C8 0x2B8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03			0x0C8 0x2B8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M			0x0C8 0x2B8 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0			0x0C8 0x2B8 0x50C 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00			0x0CC 0x2BC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT				0x0CC 0x2BC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03			0x0CC 0x2BC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC			0x0CC 0x2BC 0x5C4 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09			0x0CC 0x2BC 0x41C 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04			0x0CC 0x2BC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00			0x0CC 0x2BC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1			0x0CC 0x2BC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01			0x0D0 0x2C0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT				0x0D0 0x2C0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02			0x0D0 0x2C0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK			0x0D0 0x2C0 0x5C0 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08			0x0D0 0x2C0 0x418 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05			0x0D0 0x2C0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17			0x0D0 0x2C0 0x62C 0x6 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2			0x0D0 0x2C0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS				0x0D4 0x2C4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1			0x0D4 0x2C4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK			0x0D4 0x2C4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK			0x0D4 0x2C4 0x5B4 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07			0x0D4 0x2C4 0x414 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06			0x0D4 0x2C4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18			0x0D4 0x2C4 0x630 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3			0x0D4 0x2C4 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK				0x0D8 0x2C8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2			0x0D8 0x2C8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER			0x0D8 0x2C8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC			0x0D8 0x2C8 0x5BC 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06			0x0D8 0x2C8 0x410 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07			0x0D8 0x2C8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19			0x0D8 0x2C8 0x654 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT		0x0D8 0x2C8 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD				0x0DC 0x2CC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3			0x0DC 0x2CC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03			0x0DC 0x2CC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA			0x0DC 0x2CC 0x5B8 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05			0x0DC 0x2CC 0x40C 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08			0x0DC 0x2CC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20			0x0DC 0x2CC 0x634 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN		0x0DC 0x2CC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI				0x0E0 0x2D0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A			0x0E0 0x2D0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02			0x0E0 0x2D0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA			0x0E0 0x2D0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04			0x0E0 0x2D0 0x408 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09			0x0E0 0x2D0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21			0x0E0 0x2D0 0x658 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK				0x0E0 0x2D0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO				0x0E4 0x2D4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A			0x0E4 0x2D4 0x454 0x1 0x3
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS				0x0E4 0x2D4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK				0x0E4 0x2D4 0x5B0 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03			0x0E4 0x2D4 0x404 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10			0x0E4 0x2D4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22			0x0E4 0x2D4 0x638 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT		0x0E4 0x2D4 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB			0x0E8 0x2D8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B			0x0E8 0x2D8 0x464 0x1 0x3
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL				0x0E8 0x2D8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B				0x0E8 0x2D8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02			0x0E8 0x2D8 0x400 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11			0x0E8 0x2D8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23			0x0E8 0x2D8 0x63C 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN		0x0E8 0x2D8 0x444 0x7 0x1
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL			0x0EC 0x2DC 0x4E4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY			0x0EC 0x2DC 0x3FC 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD			0x0EC 0x2DC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B				0x0EC 0x2DC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X			0x0EC 0x2DC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12			0x0EC 0x2DC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT		0x0EC 0x2DC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI				0x0EC 0x2DC 0x568 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA			0x0F0 0x2E0 0x4E8 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK				0x0F0 0x2E0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD			0x0F0 0x2E0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B				0x0F0 0x2E0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X			0x0F0 0x2E0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13			0x0F0 0x2E0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN		0x0F0 0x2E0 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M			0x0F0 0x2E0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC			0x0F4 0x2E4 0x5CC 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24			0x0F4 0x2E4 0x640 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B			0x0F4 0x2E4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT		0x0F4 0x2E4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC				0x0F4 0x2E4 0x428 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14			0x0F4 0x2E4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX			0x0F4 0x2E4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR			0x0F8 0x2E8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25			0x0F8 0x2E8 0x650 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B			0x0F8 0x2E8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN		0x0F8 0x2E8 0x444 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC				0x0F8 0x2E8 0x420 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15			0x0F8 0x2E8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX			0x0F8 0x2E8 0x450 0x6 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB		0x0F8 0x2E8 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID			0x0FC 0x2EC 0x3F8 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0			0x0FC 0x2EC 0x57C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B			0x0FC 0x2EC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL			0x0FC 0x2EC 0x4CC 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B				0x0FC 0x2EC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16			0x0FC 0x2EC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP				0x0FC 0x2EC 0x5D8 0x6 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07				0x0FC 0x2EC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR			0x100 0x2F0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1			0x100 0x2F0 0x580 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B			0x100 0x2F0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA			0x100 0x2F0 0x4D0 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY			0x100 0x2F0 0x3FC 0x4 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17			0x100 0x2F0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT			0x100 0x2F0 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07				0x100 0x2F0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID			0x104 0x2F4 0x3F4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2			0x104 0x2F4 0x584 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD			0x104 0x2F4 0x530 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT				0x104 0x2F4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT		0x104 0x2F4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18			0x104 0x2F4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B			0x104 0x2F4 0x5D4 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06				0x104 0x2F4 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC			0x108 0x2F8 0x5D0 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3			0x108 0x2F8 0x588 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD			0x108 0x2F8 0x52C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN				0x108 0x2F8 0x5C8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN		0x108 0x2F8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19			0x108 0x2F8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B			0x108 0x2F8 0x5E0 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06				0x108 0x2F8 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3			0x10C 0x2FC 0x4C4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC				0x10C 0x2FC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B			0x10C 0x2FC 0x534 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK			0x10C 0x2FC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK			0x10C 0x2FC 0x424 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20			0x10C 0x2FC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0			0x10C 0x2FC 0x5E8 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05				0x10C 0x2FC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2			0x110 0x300 0x4C0 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO				0x110 0x300 0x430 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B			0x110 0x300 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT				0x110 0x300 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK				0x110 0x300 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21			0x110 0x300 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1			0x110 0x300 0x5EC 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05				0x110 0x300 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1			0x114 0x304 0x4BC 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA			0x114 0x304 0x4E0 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD			0x114 0x304 0x53C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK			0x114 0x304 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC				0x114 0x304 0x428 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22			0x114 0x304 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2			0x114 0x304 0x5F0 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04				0x114 0x304 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0			0x118 0x308 0x4B8 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL			0x118 0x308 0x4DC 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD			0x118 0x308 0x538 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK			0x118 0x308 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC				0x118 0x308 0x420 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23			0x118 0x308 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3			0x118 0x308 0x5F4 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04				0x118 0x308 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B			0x11C 0x30C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A			0x11C 0x30C 0x494 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX			0x11C 0x30C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY			0x11C 0x30C 0x3FC 0x3 0x3
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09			0x11C 0x30C 0x41C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24			0x11C 0x30C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD			0x11C 0x30C 0x5E4 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03				0x11C 0x30C 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS			0x120 0x310 0x4A4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A			0x120 0x310 0x498 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX			0x120 0x310 0x44C 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK				0x120 0x310 0x58C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08			0x120 0x310 0x418 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25			0x120 0x310 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK			0x120 0x310 0x5DC 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03				0x120 0x310 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3			0x124 0x314 0x4B4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B				0x124 0x314 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD			0x124 0x314 0x564 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC			0x124 0x314 0x5A4 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07			0x124 0x314 0x414 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26			0x124 0x314 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP				0x124 0x314 0x608 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02				0x124 0x314 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2			0x128 0x318 0x4B0 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B				0x128 0x318 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD			0x128 0x318 0x560 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK			0x128 0x318 0x590 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06			0x128 0x318 0x410 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27			0x128 0x318 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B			0x128 0x318 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02				0x128 0x318 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1			0x12C 0x31C 0x4AC 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT				0x12C 0x31C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0			0x12C 0x31C 0x50C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00			0x12C 0x31C 0x594 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05			0x12C 0x31C 0x40C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28			0x12C 0x31C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4			0x12C 0x31C 0x5F8 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01				0x12C 0x31C 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0			0x130 0x320 0x4A8 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT				0x130 0x320 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI			0x130 0x320 0x514 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00			0x130 0x320 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04			0x130 0x320 0x408 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29			0x130 0x320 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5			0x130 0x320 0x5FC 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01				0x130 0x320 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK			0x134 0x324 0x4C8 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT				0x134 0x324 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO			0x134 0x324 0x518 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK			0x134 0x324 0x5A8 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03			0x134 0x324 0x404 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30			0x134 0x324 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6			0x134 0x324 0x600 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00				0x134 0x324 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B			0x138 0x328 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT				0x138 0x328 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK			0x138 0x328 0x510 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC			0x138 0x328 0x5AC 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02			0x138 0x328 0x400 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31			0x138 0x328 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7			0x138 0x328 0x604 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00				0x138 0x328 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK				0x13C 0x32C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0				0x13C 0x32C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT				0x13C 0x32C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0				0x13C 0x32C 0x51C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00				0x13C 0x32C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00				0x13C 0x32C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1				0x13C 0x32C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE				0x140 0x330 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1				0x140 0x330 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT				0x140 0x330 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI				0x140 0x330 0x524 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01				0x140 0x330 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01				0x140 0x330 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2				0x140 0x330 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC				0x144 0x334 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2				0x144 0x334 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX				0x144 0x334 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO				0x144 0x334 0x528 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02				0x144 0x334 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02				0x144 0x334 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3				0x144 0x334 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC				0x148 0x338 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0				0x148 0x338 0x56C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX				0x148 0x338 0x44C 0x2 0x3
+#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK				0x148 0x338 0x520 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03				0x148 0x338 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03				0x148 0x338 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB			0x148 0x338 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00				0x14C 0x33C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1				0x14C 0x33C 0x570 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL				0x14C 0x33C 0x4D4 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00				0x14C 0x33C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04				0x14C 0x33C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04				0x14C 0x33C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00				0x14C 0x33C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01				0x150 0x340 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2				0x150 0x340 0x574 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA				0x150 0x340 0x4D8 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01				0x150 0x340 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05				0x150 0x340 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05				0x150 0x340 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01				0x150 0x340 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02				0x154 0x344 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0				0x154 0x344 0x57C 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A			0x154 0x344 0x478 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02				0x154 0x344 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06				0x154 0x344 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06				0x154 0x344 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02				0x154 0x344 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03				0x158 0x348 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1				0x158 0x348 0x580 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B			0x158 0x348 0x488 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03				0x158 0x348 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07				0x158 0x348 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07				0x158 0x348 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03				0x158 0x348 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04				0x15C 0x34C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2				0x15C 0x34C 0x584 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A			0x15C 0x34C 0x47C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD				0x15C 0x34C 0x53C 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08				0x15C 0x34C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08				0x15C 0x34C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04				0x15C 0x34C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05				0x160 0x350 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0				0x160 0x350 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B			0x160 0x350 0x48C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD				0x160 0x350 0x538 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09				0x160 0x350 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09				0x160 0x350 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05				0x160 0x350 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06				0x164 0x354 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1				0x164 0x354 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A			0x164 0x354 0x480 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03			0x164 0x354 0x598 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10				0x164 0x354 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10				0x164 0x354 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06				0x164 0x354 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07				0x168 0x358 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2				0x168 0x358 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B			0x168 0x358 0x490 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02			0x168 0x358 0x59C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11				0x168 0x358 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11				0x168 0x358 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07				0x168 0x358 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08				0x16C 0x35C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10				0x16C 0x35C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK			0x16C 0x35C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01			0x16C 0x35C 0x5A0 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12				0x16C 0x35C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12				0x16C 0x35C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08				0x16C 0x35C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09				0x170 0x360 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11				0x170 0x360 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO			0x170 0x360 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK				0x170 0x360 0x58C 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13				0x170 0x360 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13				0x170 0x360 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09				0x170 0x360 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10				0x174 0x364 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12				0x174 0x364 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV				0x174 0x364 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC				0x174 0x364 0x5A4 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14				0x174 0x364 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14				0x174 0x364 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10				0x174 0x364 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11				0x178 0x368 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13				0x178 0x368 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV				0x178 0x368 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK				0x178 0x368 0x590 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15				0x178 0x368 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15				0x178 0x368 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11				0x178 0x368 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12				0x17C 0x36C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14				0x17C 0x36C 0x644 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD				0x17C 0x36C 0x544 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00			0x17C 0x36C 0x594 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16				0x17C 0x36C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16				0x17C 0x36C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A			0x17C 0x36C 0x454 0x6 0x4
+
+#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13				0x180 0x370 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15				0x180 0x370 0x648 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD				0x180 0x370 0x540 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00			0x180 0x370 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17				0x180 0x370 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17				0x180 0x370 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B			0x180 0x370 0x464 0x6 0x4
+
+#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14				0x184 0x374 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16				0x184 0x374 0x64C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2				0x184 0x374 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK				0x184 0x374 0x5A8 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18				0x184 0x374 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18				0x184 0x374 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A			0x184 0x374 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15				0x188 0x378 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17				0x188 0x378 0x62C 0x1 0x3
+#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1				0x188 0x378 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC				0x188 0x378 0x5AC 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19				0x188 0x378 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19				0x188 0x378 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B			0x188 0x378 0x484 0x6 0x3
+
+#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16				0x18C 0x37C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0				0x18C 0x37C 0x51C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15				0x18C 0x37C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00			0x18C 0x37C 0x434 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20				0x18C 0x37C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20				0x18C 0x37C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17				0x190 0x380 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI				0x190 0x380 0x524 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14				0x190 0x380 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01			0x190 0x380 0x438 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21				0x190 0x380 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21				0x190 0x380 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18				0x194 0x384 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO				0x194 0x384 0x528 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13				0x194 0x384 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN				0x194 0x384 0x43C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22				0x194 0x384 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22				0x194 0x384 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19				0x198 0x388 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK				0x198 0x388 0x520 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12				0x198 0x388 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00			0x198 0x388 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23				0x198 0x388 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23				0x198 0x388 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20				0x19C 0x38C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3				0x19C 0x38C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11				0x19C 0x38C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01			0x19C 0x38C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24				0x19C 0x38C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24				0x19C 0x38C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX				0x19C 0x38C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21				0x1A0 0x390 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3				0x1A0 0x390 0x578 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10				0x1A0 0x390 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN				0x1A0 0x390 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25				0x1A0 0x390 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25				0x1A0 0x390 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX				0x1A0 0x390 0x450 0x6 0x3
+
+#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22				0x1A4 0x394 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3				0x1A4 0x394 0x588 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00				0x1A4 0x394 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK				0x1A4 0x394 0x448 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26				0x1A4 0x394 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26				0x1A4 0x394 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK				0x1A4 0x394 0x42C 0x6 0x1
+
+#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23				0x1A8 0x398 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3				0x1A8 0x398 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01				0x1A8 0x398 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER				0x1A8 0x398 0x440 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27				0x1A8 0x398 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27				0x1A8 0x398 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3				0x1A8 0x398 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD				0x1AC 0x39C 0x54C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK				0x1AC 0x39C 0x424 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN			0x1AC 0x39C 0x444 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28				0x1AC 0x39C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28				0x1AC 0x39C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B				0x1AC 0x39C 0x5D4 0x6 0x2
+
+#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B				0x1B0 0x3A0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD				0x1B0 0x3A0 0x548 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC				0x1B0 0x3A0 0x428 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT			0x1B0 0x3A0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29				0x1B0 0x3A0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29				0x1B0 0x3A0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP				0x1B0 0x3A0 0x5D8 0x6 0x3
+
+#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC				0x1B4 0x3A4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A			0x1B4 0x3A4 0x49C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC				0x1B4 0x3A4 0x420 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02				0x1B4 0x3A4 0x60C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30				0x1B4 0x3A4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30				0x1B4 0x3A4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT			0x1B4 0x3A4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO				0x1B8 0x3A8 0x430 0x0 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A			0x1B8 0x3A8 0x4A0 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK				0x1B8 0x3A8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03				0x1B8 0x3A8 0x610 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31				0x1B8 0x3A8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31				0x1B8 0x3A8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B			0x1B8 0x3A8 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD			0x1BC 0x3AC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A			0x1BC 0x3AC 0x458 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL			0x1BC 0x3AC 0x4DC 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04			0x1BC 0x3AC 0x614 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK			0x1BC 0x3AC 0x4F0 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12			0x1BC 0x3AC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B			0x1BC 0x3AC 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK			0x1C0 0x3B0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B			0x1C0 0x3B0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA			0x1C0 0x3B0 0x4E0 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05			0x1C0 0x3B0 0x618 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0			0x1C0 0x3B0 0x4EC 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13			0x1C0 0x3B0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B			0x1C0 0x3B0 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0			0x1C4 0x3B4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A			0x1C4 0x3B4 0x45C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B			0x1C4 0x3B4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06			0x1C4 0x3B4 0x61C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO			0x1C4 0x3B4 0x4F8 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14			0x1C4 0x3B4 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1			0x1C8 0x3B8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B			0x1C8 0x3B8 0x46C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B			0x1C8 0x3B8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07			0x1C8 0x3B8 0x620 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI			0x1C8 0x3B8 0x4F4 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15			0x1C8 0x3B8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2			0x1CC 0x3BC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A			0x1CC 0x3BC 0x460 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD			0x1CC 0x3BC 0x564 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08			0x1CC 0x3BC 0x624 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B			0x1CC 0x3BC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16			0x1CC 0x3BC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1				0x1CC 0x3BC 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3			0x1D0 0x3C0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B			0x1D0 0x3C0 0x470 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD			0x1D0 0x3C0 0x560 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09			0x1D0 0x3C0 0x628 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS			0x1D0 0x3C0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17			0x1D0 0x3C0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2				0x1D0 0x3C0 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3			0x1D4 0x3C4 0x5F4 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3			0x1D4 0x3C4 0x4C4 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A			0x1D4 0x3C4 0x454 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03			0x1D4 0x3C4 0x598 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD			0x1D4 0x3C4 0x544 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00			0x1D4 0x3C4 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2			0x1D8 0x3C8 0x5F0 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2			0x1D8 0x3C8 0x4C0 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B			0x1D8 0x3C8 0x464 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02			0x1D8 0x3C8 0x59C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD			0x1D8 0x3C8 0x540 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01			0x1D8 0x3C8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1			0x1DC 0x3CC 0x5EC 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1			0x1DC 0x3CC 0x4BC 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A			0x1DC 0x3CC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01			0x1DC 0x3CC 0x5A0 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX			0x1DC 0x3CC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02			0x1DC 0x3CC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT				0x1DC 0x3CC 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0			0x1E0 0x3D0 0x5E8 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0			0x1E0 0x3D0 0x4B8 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B			0x1E0 0x3D0 0x484 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK				0x1E0 0x3D0 0x58C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX			0x1E0 0x3D0 0x44C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03			0x1E0 0x3D0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY			0x1E0 0x3D0 0x3FC 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK			0x1E4 0x3D4 0x5DC 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK			0x1E4 0x3D4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL			0x1E4 0x3D4 0x4CC 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC			0x1E4 0x3D4 0x5A4 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B			0x1E4 0x3D4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04			0x1E4 0x3D4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP				0x1E4 0x3D4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD			0x1E8 0x3D8 0x5E4 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS			0x1E8 0x3D8 0x4A4 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA			0x1E8 0x3D8 0x4D0 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK			0x1E8 0x3D8 0x590 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B			0x1E8 0x3D8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05			0x1E8 0x3D8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B			0x1EC 0x3DC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B			0x1EC 0x3DC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B			0x1EC 0x3DC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00			0x1EC 0x3DC 0x594 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0			0x1EC 0x3DC 0x4FC 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06			0x1EC 0x3DC 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1				0x1F0 0x3E0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK			0x1F0 0x3E0 0x4C8 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B			0x1F0 0x3E0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00			0x1F0 0x3E0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK			0x1F0 0x3E0 0x500 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07			0x1F0 0x3E0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B			0x1F0 0x3E0 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4			0x1F4 0x3E4 0x5F8 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0			0x1F4 0x3E4 0x4A8 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD			0x1F4 0x3E4 0x55C 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK			0x1F4 0x3E4 0x5A8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO			0x1F4 0x3E4 0x508 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08			0x1F4 0x3E4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2				0x1F4 0x3E4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5			0x1F8 0x3E8 0x5FC 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1			0x1F8 0x3E8 0x4AC 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD			0x1F8 0x3E8 0x558 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC			0x1F8 0x3E8 0x5AC 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI			0x1F8 0x3E8 0x504 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09			0x1F8 0x3E8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6			0x1FC 0x3EC 0x600 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2			0x1FC 0x3EC 0x4B0 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD			0x1FC 0x3EC 0x52C 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA			0x1FC 0x3EC 0x4D8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2			0x1FC 0x3EC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10			0x1FC 0x3EC 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7			0x200 0x3F0 0x604 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3			0x200 0x3F0 0x4B4 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD			0x200 0x3F0 0x530 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL			0x200 0x3F0 0x4D4 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3			0x200 0x3F0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11			0x200 0x3F0 0x000 0x5 0x0
+
+#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 15/21] serial_lpuart: add clock enable if CONFIG_CLK is defined
  2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
                   ` (13 preceding siblings ...)
  2020-01-10 14:47 ` [PATCH v2 14/21] ARM: dts: imxrt1050: add dtsi file Giulio Benetti
@ 2020-01-10 14:47 ` Giulio Benetti
  2020-01-15 12:47   ` sbabic at denx.de
  2020-01-28  8:36   ` Lukasz Majewski
  14 siblings, 2 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:47 UTC (permalink / raw)
  To: u-boot

This driver assumes that lpuart clock is already enabled before probing
but using DM only lpuart won't be automatically enabled so add
clk_enable() when probing if CONFIG_CLK is defined. If clock is not
found, because DM is not used, let's emit a warning and proceed, because
serial clock could also be already enabled by non DM code. If clock is
found but cna't be enabled then return with error.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
V1->V2:
* moved error as warning if clk not found
---
 drivers/serial/serial_lpuart.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 4b0a964d1b..b2ec56172e 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -483,6 +483,22 @@ static int lpuart_serial_pending(struct udevice *dev, bool input)
 
 static int lpuart_serial_probe(struct udevice *dev)
 {
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk per_clk;
+	int ret;
+
+	ret = clk_get_by_name(dev, "per", &per_clk);
+	if (!ret) {
+		ret = clk_enable(&per_clk);
+		if (ret) {
+			dev_err(dev, "Failed to get per clk: %d\n", ret);
+			return ret;
+		}
+	} else {
+		dev_warn(dev, "Failed to get per clk: %d\n",  ret);
+	}
+#endif
+
 	if (is_lpuart32(dev))
 		return _lpuart32_serial_init(dev);
 	else
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 13/21] gpio: mxc_gpio: add support for i.MXRT1050
  2020-01-10 14:47 ` [PATCH v2 13/21] gpio: mxc_gpio: add support for i.MXRT1050 Giulio Benetti
@ 2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:27   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:46 UTC (permalink / raw)
  To: u-boot

> Add i.MXRT1050 support, there are 5 GPIO banks.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 07/21] clk: imx: pllv3: add set_rate() support
  2020-01-10 14:46 ` [PATCH v2 07/21] clk: imx: pllv3: add set_rate() support Giulio Benetti
@ 2020-01-15 12:46   ` sbabic at denx.de
  0 siblings, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:46 UTC (permalink / raw)
  To: u-boot

> Add generic set_rate() support.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 10/21] clk: imx: pfd: add set_rate()
  2020-01-10 14:47 ` [PATCH v2 10/21] clk: imx: pfd: add set_rate() Giulio Benetti
@ 2020-01-15 12:46   ` sbabic at denx.de
  0 siblings, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:46 UTC (permalink / raw)
  To: u-boot

> Implement set_rate() for pfd.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 05/21] clk: imx: pllv3: add enable() support
  2020-01-10 14:46 ` [PATCH v2 05/21] clk: imx: pllv3: add enable() support Giulio Benetti
@ 2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:14   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:46 UTC (permalink / raw)
  To: u-boot

> Before set_rate() pllv3 needs enable() to power the pll up.
> Add enable() taking into account different power_bit and
> different powerup_set, because some pll needs its power_bit to be
> set or reset to be powered on.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 09/21] clk: imx: pllv3: add support for PLLV3_AV type
  2020-01-10 14:46 ` [PATCH v2 09/21] clk: imx: pllv3: add support for PLLV3_AV type Giulio Benetti
@ 2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:20   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:46 UTC (permalink / raw)
  To: u-boot

> Add support for PLLV3 AV type.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 02/21] armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibility
  2020-01-10 14:46 ` [PATCH v2 02/21] armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibility Giulio Benetti
@ 2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:10   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:46 UTC (permalink / raw)
  To: u-boot

> Since some driver requires this function add it as an empty stub
> when DCACHE is OFF.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 01/21] spl: fix entry_point equal to load_addr
  2020-01-10 14:46 ` [PATCH v2 01/21] spl: fix entry_point equal to load_addr Giulio Benetti
@ 2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:09   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:46 UTC (permalink / raw)
  To: u-boot

> At the moment entry_point is set to image_get_load(header) that sets it
> to "load address" instead of "entry point", assuming entry_point is
> equal to load_addr, but it's not true. Then load_addr is set to
> "entry_point - header_size", but this is wrong too since load_addr is
> not an entry point.
> So use image_get_ep() for entry_point assignment and image_get_load()
> for load_addr assignment.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 11/21] clk: imx: add i.IMXRT1050 clk driver
  2020-01-10 14:47 ` [PATCH v2 11/21] clk: imx: add i.IMXRT1050 clk driver Giulio Benetti
@ 2020-01-15 12:46   ` sbabic at denx.de
  2020-01-28  8:23   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:46 UTC (permalink / raw)
  To: u-boot

> Add i.MXRT1050 clk driver support.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 15/21] serial_lpuart: add clock enable if CONFIG_CLK is defined
  2020-01-10 14:47 ` [PATCH v2 15/21] serial_lpuart: add clock enable if CONFIG_CLK is defined Giulio Benetti
@ 2020-01-15 12:47   ` sbabic at denx.de
  2020-01-28  8:36   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:47 UTC (permalink / raw)
  To: u-boot

> This driver assumes that lpuart clock is already enabled before probing
> but using DM only lpuart won't be automatically enabled so add
> clk_enable() when probing if CONFIG_CLK is defined. If clock is not
> found, because DM is not used, let's emit a warning and proceed, because
> serial clock could also be already enabled by non DM code. If clock is
> found but cna't be enabled then return with error.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 14/21] ARM: dts: imxrt1050: add dtsi file
  2020-01-10 14:47 ` [PATCH v2 14/21] ARM: dts: imxrt1050: add dtsi file Giulio Benetti
@ 2020-01-15 12:47   ` sbabic at denx.de
  2020-01-28  8:31   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:47 UTC (permalink / raw)
  To: u-boot

> Add dtsi file for i.MXRT1050.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 12/21] pinctrl: add i.MXRT driver
  2020-01-10 14:47 ` [PATCH v2 12/21] pinctrl: add i.MXRT driver Giulio Benetti
@ 2020-01-15 12:47   ` sbabic at denx.de
  2020-01-28  8:27   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:47 UTC (permalink / raw)
  To: u-boot

> Add i.MXRT pinctrl driver.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 04/21] clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB
  2020-01-10 14:46 ` [PATCH v2 04/21] clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB Giulio Benetti
@ 2020-01-15 12:47   ` sbabic at denx.de
  0 siblings, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:47 UTC (permalink / raw)
  To: u-boot

> div_mask is different for GENERIC and USB pll, so set it according.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 03/21] clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks
  2020-01-10 14:46 ` [PATCH v2 03/21] clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Giulio Benetti
@ 2020-01-15 12:47   ` sbabic at denx.de
  0 siblings, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:47 UTC (permalink / raw)
  To: u-boot

> Better to register the 2 clock as 2 different drivers because they work
> slightly differently depending on power_bit and powerup_set bits coming
> on next patches.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 08/21] clk: imx: pllv3: add PLLV3_SYS support
  2020-01-10 14:46 ` [PATCH v2 08/21] clk: imx: pllv3: add PLLV3_SYS support Giulio Benetti
@ 2020-01-15 12:47   ` sbabic at denx.de
  0 siblings, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:47 UTC (permalink / raw)
  To: u-boot

> Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping
> generic enable()/disable(). Add a different driver because ops are
> different respect to GENERIC/USB.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 06/21] clk: imx: pllv3: add disable() support
  2020-01-10 14:46 ` [PATCH v2 06/21] clk: imx: pllv3: add disable() support Giulio Benetti
@ 2020-01-15 12:47   ` sbabic at denx.de
  0 siblings, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:47 UTC (permalink / raw)
  To: u-boot

> Add disable() support.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 01/21] spl: fix entry_point equal to load_addr
  2020-01-10 14:46 ` [PATCH v2 01/21] spl: fix entry_point equal to load_addr Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
@ 2020-01-28  8:09   ` Lukasz Majewski
  2020-01-28 16:37     ` Giulio Benetti
  1 sibling, 1 reply; 54+ messages in thread
From: Lukasz Majewski @ 2020-01-28  8:09 UTC (permalink / raw)
  To: u-boot

Hi Giulio,

> At the moment entry_point is set to image_get_load(header) that sets
> it to "load address" instead of "entry point", assuming entry_point is
> equal to load_addr, but it's not true. Then load_addr is set to
> "entry_point - header_size", but this is wrong too since load_addr is
> not an entry point.
> 
> So use image_get_ep() for entry_point assignment and image_get_load()
> for load_addr assignment.
> 
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
>  common/spl/spl.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/common/spl/spl.c b/common/spl/spl.c
> index c1fce62b91..19085ad270 100644
> --- a/common/spl/spl.c
> +++ b/common/spl/spl.c
> @@ -284,9 +284,9 @@ int spl_parse_image_header(struct spl_image_info
> *spl_image, spl_image->entry_point = image_get_ep(header);
>  			spl_image->size =
> image_get_data_size(header); } else {
> -			spl_image->entry_point =
> image_get_load(header);
> +			spl_image->entry_point =
> image_get_ep(header); /* Load including the header */
> -			spl_image->load_addr =
> spl_image->entry_point -
> +			spl_image->load_addr =
> image_get_load(header) - header_size;
>  			spl_image->size =
> image_get_data_size(header) + header_size;

I'm concerned, that this change will silently break several boards -
the problem is with assumption that entry point is equal to load_addr.

It would be best to pull this change ASAP, so we would have a chance to
fix this by next release.


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 02/21] armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibility
  2020-01-10 14:46 ` [PATCH v2 02/21] armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibility Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
@ 2020-01-28  8:10   ` Lukasz Majewski
  2020-01-28 16:50     ` Giulio Benetti
  1 sibling, 1 reply; 54+ messages in thread
From: Lukasz Majewski @ 2020-01-28  8:10 UTC (permalink / raw)
  To: u-boot

Hi Giulio,

> Since some driver 

I would prefer more verbose commit message. Please share which driver
requires this change.

> requires this function add it as an empty stub
> when DCACHE is OFF.
> 
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
>  arch/arm/cpu/armv7m/cache.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
> index f4ba3ad50e..7353698557 100644
> --- a/arch/arm/cpu/armv7m/cache.c
> +++ b/arch/arm/cpu/armv7m/cache.c
> @@ -291,6 +291,12 @@ void flush_dcache_all(void)
>  void invalidate_dcache_all(void)
>  {
>  }
> +
> +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
> +				     enum dcache_option option)
> +{
> +}
> +
>  #endif
>  
>  #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 05/21] clk: imx: pllv3: add enable() support
  2020-01-10 14:46 ` [PATCH v2 05/21] clk: imx: pllv3: add enable() support Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
@ 2020-01-28  8:14   ` Lukasz Majewski
  2020-01-28 18:46     ` Giulio Benetti
  1 sibling, 1 reply; 54+ messages in thread
From: Lukasz Majewski @ 2020-01-28  8:14 UTC (permalink / raw)
  To: u-boot

Hi Giulio,

> Before set_rate() pllv3 needs enable() to power the pll up.
> Add enable() taking into account different power_bit and
> different powerup_set, because some pll needs its power_bit to be
> set or reset to be powered on.

I do guess that this code is similar to what we do have in the Linux
kernel (and which I've probably omitted as it was not needed in the
i.MX6Q use case)?

> 
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
>  drivers/clk/imx/clk-pllv3.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> index 02c75c37ea..d8cbe3dd4e 100644
> --- a/drivers/clk/imx/clk-pllv3.c
> +++ b/drivers/clk/imx/clk-pllv3.c
> @@ -16,9 +16,13 @@
>  #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC	"imx_clk_pllv3_generic"
>  #define UBOOT_DM_CLK_IMX_PLLV3_USB	"imx_clk_pllv3_usb"
>  
> +#define BM_PLL_POWER		(0x1 << 12)
> +
>  struct clk_pllv3 {
>  	struct clk	clk;
>  	void __iomem	*base;
> +	u32		power_bit;
> +	bool		powerup_set;
>  	u32		div_mask;
>  	u32		div_shift;
>  };
> @@ -35,8 +39,24 @@ static ulong clk_pllv3_generic_get_rate(struct clk
> *clk) return (div == 1) ? parent_rate * 22 : parent_rate * 20;
>  }
>  
> +static int clk_pllv3_generic_enable(struct clk *clk)
> +{
> +	struct clk_pllv3 *pll = to_clk_pllv3(clk);
> +	u32 val;
> +
> +	val = readl(pll->base);
> +	if (pll->powerup_set)
> +		val |= pll->power_bit;
> +	else
> +		val &= ~pll->power_bit;
> +	writel(val, pll->base);
> +
> +	return 0;
> +}
> +
>  static const struct clk_ops clk_pllv3_generic_ops = {
>  	.get_rate	= clk_pllv3_generic_get_rate,
> +	.enable		= clk_pllv3_generic_enable,
>  };
>  
>  struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
> @@ -52,14 +72,18 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type
> type, const char *name, if (!pll)
>  		return ERR_PTR(-ENOMEM);
>  
> +	pll->power_bit = BM_PLL_POWER;
> +
>  	switch (type) {
>  	case IMX_PLLV3_GENERIC:
>  		drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
>  		pll->div_shift = 0;
> +		pll->powerup_set = false;
>  		break;
>  	case IMX_PLLV3_USB:
>  		drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
>  		pll->div_shift = 1;
> +		pll->powerup_set = true;
>  		break;
>  	default:
>  		kfree(pll);




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 09/21] clk: imx: pllv3: add support for PLLV3_AV type
  2020-01-10 14:46 ` [PATCH v2 09/21] clk: imx: pllv3: add support for PLLV3_AV type Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
@ 2020-01-28  8:20   ` Lukasz Majewski
  2020-01-31 13:50     ` Giulio Benetti
  1 sibling, 1 reply; 54+ messages in thread
From: Lukasz Majewski @ 2020-01-28  8:20 UTC (permalink / raw)
  To: u-boot

Hi Giulio,

> Add support for PLLV3 AV type.

If this code has been ported from Linux kernel, then provide SHA1,
branch, and commit message.

Acked-by: Lukasz Majewski <lukma@denx.de>

> 
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
>  drivers/clk/imx/clk-pllv3.c | 76
> +++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> index d5087a104e..fc16416d5f 100644
> --- a/drivers/clk/imx/clk-pllv3.c
> +++ b/drivers/clk/imx/clk-pllv3.c
> @@ -6,6 +6,7 @@
>  
>  #include <common.h>
>  #include <asm/io.h>
> +#include <div64.h>
>  #include <malloc.h>
>  #include <clk-uclass.h>
>  #include <dm/device.h>
> @@ -16,6 +17,10 @@
>  #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC	"imx_clk_pllv3_generic"
>  #define UBOOT_DM_CLK_IMX_PLLV3_SYS	"imx_clk_pllv3_sys"
>  #define UBOOT_DM_CLK_IMX_PLLV3_USB	"imx_clk_pllv3_usb"
> +#define UBOOT_DM_CLK_IMX_PLLV3_AV	"imx_clk_pllv3_av"
> +
> +#define PLL_NUM_OFFSET		0x10
> +#define PLL_DENOM_OFFSET	0x20
>  
>  #define BM_PLL_POWER		(0x1 << 12)
>  #define BM_PLL_LOCK		(0x1 << 31)
> @@ -143,6 +148,65 @@ static const struct clk_ops clk_pllv3_sys_ops = {
>  	.set_rate	= clk_pllv3_sys_set_rate,
>  };
>  
> +static ulong clk_pllv3_av_get_rate(struct clk *clk)
> +{
> +	struct clk_pllv3 *pll = to_clk_pllv3(clk);
> +	unsigned long parent_rate = clk_get_parent_rate(clk);
> +	u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
> +	u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
> +	u32 div = readl(pll->base) & pll->div_mask;
> +	u64 temp64 = (u64)parent_rate;
> +
> +	temp64 *= mfn;
> +	do_div(temp64, mfd);
> +
> +	return parent_rate * div + (unsigned long)temp64;
> +}
> +
> +static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
> +{
> +	struct clk_pllv3 *pll = to_clk_pllv3(clk);
> +	unsigned long parent_rate = clk_get_parent_rate(clk);
> +	unsigned long min_rate = parent_rate * 27;
> +	unsigned long max_rate = parent_rate * 54;
> +	u32 val, div;
> +	u32 mfn, mfd = 1000000;
> +	u32 max_mfd = 0x3FFFFFFF;
> +	u64 temp64;
> +
> +	if (rate < min_rate || rate > max_rate)
> +		return -EINVAL;
> +
> +	if (parent_rate <= max_mfd)
> +		mfd = parent_rate;
> +
> +	div = rate / parent_rate;
> +	temp64 = (u64)(rate - div * parent_rate);
> +	temp64 *= mfd;
> +	do_div(temp64, parent_rate);
> +	mfn = temp64;
> +
> +	val = readl(pll->base);
> +	val &= ~pll->div_mask;
> +	val |= div;
> +	writel(val, pll->base);
> +	writel(mfn, pll->base + PLL_NUM_OFFSET);
> +	writel(mfd, pll->base + PLL_DENOM_OFFSET);
> +
> +	/* Wait for PLL to lock */
> +	while (!(readl(pll->base) & BM_PLL_LOCK))
> +		;
> +
> +	return 0;
> +}
> +
> +static const struct clk_ops clk_pllv3_av_ops = {
> +	.enable		= clk_pllv3_generic_enable,
> +	.disable	= clk_pllv3_generic_disable,
> +	.get_rate	= clk_pllv3_av_get_rate,
> +	.set_rate	= clk_pllv3_av_set_rate,
> +};
> +
>  struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
>  			  const char *parent_name, void __iomem
> *base, u32 div_mask)
> @@ -174,6 +238,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type
> type, const char *name, pll->div_shift = 1;
>  		pll->powerup_set = true;
>  		break;
> +	case IMX_PLLV3_AV:
> +		drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
> +		pll->div_shift = 0;
> +		pll->powerup_set = false;
> +		break;
>  	default:
>  		kfree(pll);
>  		return ERR_PTR(-ENOTSUPP);
> @@ -212,3 +281,10 @@ U_BOOT_DRIVER(clk_pllv3_usb) = {
>  	.ops	= &clk_pllv3_generic_ops,
>  	.flags = DM_FLAG_PRE_RELOC,
>  };
> +
> +U_BOOT_DRIVER(clk_pllv3_av) = {
> +	.name	= UBOOT_DM_CLK_IMX_PLLV3_AV,
> +	.id	= UCLASS_CLK,
> +	.ops	= &clk_pllv3_av_ops,
> +	.flags = DM_FLAG_PRE_RELOC,
> +};




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 11/21] clk: imx: add i.IMXRT1050 clk driver
  2020-01-10 14:47 ` [PATCH v2 11/21] clk: imx: add i.IMXRT1050 clk driver Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
@ 2020-01-28  8:23   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: Lukasz Majewski @ 2020-01-28  8:23 UTC (permalink / raw)
  To: u-boot

Hi Giulio,

> Add i.MXRT1050 clk driver support.
> 

Acked-by: Lukasz Majewski <lukma@denx.de>

> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
>  drivers/clk/imx/Kconfig                     |  16 ++
>  drivers/clk/imx/Makefile                    |   2 +
>  drivers/clk/imx/clk-imxrt1050.c             | 292
> ++++++++++++++++++++ include/dt-bindings/clock/imxrt1050-clock.h |
> 65 +++++ 4 files changed, 375 insertions(+)
>  create mode 100644 drivers/clk/imx/clk-imxrt1050.c
>  create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h
> 
> diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
> index 2f149ff6f8..059bc2fbb9 100644
> --- a/drivers/clk/imx/Kconfig
> +++ b/drivers/clk/imx/Kconfig
> @@ -68,3 +68,19 @@ config CLK_IMX8MP
>  	select CLK_CCF
>  	help
>  	  This enables support clock driver for i.MX8MP platforms.
> +
> +config SPL_CLK_IMXRT1050
> +	bool "SPL clock support for i.MXRT1050"
> +	depends on ARCH_IMXRT && SPL
> +	select SPL_CLK
> +	select SPL_CLK_CCF
> +	help
> +	  This enables SPL DM/DTS support for clock driver in
> i.MXRT1050 +
> +config CLK_IMXRT1050
> +	bool "Clock support for i.MXRT1050"
> +	depends on ARCH_IMXRT
> +	select CLK
> +	select CLK_CCF
> +	help
> +	  This enables support clock driver for i.MXRT1050 platforms.
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 255a87b18e..1e8a49d0f3 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -16,3 +16,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
> clk-pll14xx.o \ clk-composite-8m.o
>  obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
>  				clk-composite-8m.o
> +
> +obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
> diff --git a/drivers/clk/imx/clk-imxrt1050.c
> b/drivers/clk/imx/clk-imxrt1050.c new file mode 100644
> index 0000000000..44ca52c013
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imxrt1050.c
> @@ -0,0 +1,292 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright(C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <dt-bindings/clock/imxrt1050-clock.h>
> +
> +#include "clk.h"
> +
> +static ulong imxrt1050_clk_get_rate(struct clk *clk)
> +{
> +	struct clk *c;
> +	int ret;
> +
> +	debug("%s(#%lu)\n", __func__, clk->id);
> +
> +	ret = clk_get_by_id(clk->id, &c);
> +	if (ret)
> +		return ret;
> +
> +	return clk_get_rate(c);
> +}
> +
> +static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate)
> +{
> +	struct clk *c;
> +	int ret;
> +
> +	debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
> +
> +	ret = clk_get_by_id(clk->id, &c);
> +	if (ret)
> +		return ret;
> +
> +	return clk_set_rate(c, rate);
> +}
> +
> +static int __imxrt1050_clk_enable(struct clk *clk, bool enable)
> +{
> +	struct clk *c;
> +	int ret;
> +
> +	debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
> +
> +	ret = clk_get_by_id(clk->id, &c);
> +	if (ret)
> +		return ret;
> +
> +	if (enable)
> +		ret = clk_enable(c);
> +	else
> +		ret = clk_disable(c);
> +
> +	return ret;
> +}
> +
> +static int imxrt1050_clk_disable(struct clk *clk)
> +{
> +	return __imxrt1050_clk_enable(clk, 0);
> +}
> +
> +static int imxrt1050_clk_enable(struct clk *clk)
> +{
> +	return __imxrt1050_clk_enable(clk, 1);
> +}
> +
> +static struct clk_ops imxrt1050_clk_ops = {
> +	.set_rate = imxrt1050_clk_set_rate,
> +	.get_rate = imxrt1050_clk_get_rate,
> +	.enable = imxrt1050_clk_enable,
> +	.disable = imxrt1050_clk_disable,
> +};
> +
> +static const char * const pll_ref_sels[] = {"osc", "dummy", };
> +static const char * const pll1_bypass_sels[] = {"pll1_arm",
> "pll1_arm_ref_sel", }; +static const char * const pll2_bypass_sels[]
> = {"pll2_sys", "pll2_sys_ref_sel", }; +static const char * const
> pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
> +static const char * const pll5_bypass_sels[] = {"pll5_video",
> "pll5_video_ref_sel", }; + +static const char *const
> pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m",
> "arm_podf", }; +static const char *const periph_sels[] = {
> "pre_periph_sel", "todo", }; +static const char *const usdhc_sels[] =
> { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *const
> lpuart_sels[] = { "pll3_80m", "osc", }; +static const char *const
> semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; +static
> const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
> +static const char *const lcdif_sels[] = { "pll2_sys",
> "pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m",
> "pll2_pfd1_594m", "pll3_pfd1_664_62m"}; + +static int
> imxrt1050_clk_probe(struct udevice *dev) +{
> +	void *base;
> +
> +	/* Anatop clocks */
> +	base = (void *)ANATOP_BASE_ADDR;
> +
> +	clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
> +	       imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
> +			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> +	clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,
> +	       imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
> +			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> +	clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,
> +	       imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14,
> 2,
> +			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> +	clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,
> +	       imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
> +			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> +
> +	clk_dm(IMXRT1050_CLK_PLL1_ARM,
> +	       imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm",
> "pll1_arm_ref_sel",
> +			     base + 0x0, 0x7f));
> +	clk_dm(IMXRT1050_CLK_PLL2_SYS,
> +	       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys",
> "pll2_sys_ref_sel",
> +			     base + 0x30, 0x1));
> +	clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,
> +	       imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
> +			     "pll3_usb_otg_ref_sel",
> +			     base + 0x10, 0x1));
> +	clk_dm(IMXRT1050_CLK_PLL5_VIDEO,
> +	       imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video",
> "pll5_video_ref_sel",
> +			     base + 0xa0, 0x7f));
> +
> +	/* PLL bypass out */
> +	clk_dm(IMXRT1050_CLK_PLL1_BYPASS,
> +	       imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
> +				 pll1_bypass_sels,
> +				 ARRAY_SIZE(pll1_bypass_sels),
> +				 CLK_SET_RATE_PARENT));
> +	clk_dm(IMXRT1050_CLK_PLL2_BYPASS,
> +	       imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
> +				 pll2_bypass_sels,
> +				 ARRAY_SIZE(pll2_bypass_sels),
> +				 CLK_SET_RATE_PARENT));
> +	clk_dm(IMXRT1050_CLK_PLL3_BYPASS,
> +	       imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
> +				 pll3_bypass_sels,
> +				 ARRAY_SIZE(pll3_bypass_sels),
> +				 CLK_SET_RATE_PARENT));
> +	clk_dm(IMXRT1050_CLK_PLL5_BYPASS,
> +	       imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
> +				 pll5_bypass_sels,
> +				 ARRAY_SIZE(pll5_bypass_sels),
> +				 CLK_SET_RATE_PARENT));
> +
> +	clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,
> +	       imx_clk_divider("video_post_div_sel", "pll5_video",
> +			       base + 0xa0, 19, 2));
> +	clk_dm(IMXRT1050_CLK_VIDEO_DIV,
> +	       imx_clk_divider("video_div", "video_post_div_sel",
> +			       base + 0x170, 30, 2));
> +
> +	clk_dm(IMXRT1050_CLK_PLL3_80M,
> +	       imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",
> 1, 6)); +
> +	clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,
> +	       imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base +
> 0x100, 0));
> +	clk_dm(IMXRT1050_CLK_PLL2_PFD1_594M,
> +	       imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base +
> 0x100, 1));
> +	clk_dm(IMXRT1050_CLK_PLL2_PFD2_396M,
> +	       imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base +
> 0x100, 2));
> +	clk_dm(IMXRT1050_CLK_PLL3_PFD1_664_62M,
> +	       imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base
> + 0xf0,
> +			   1));
> +	clk_dm(IMXRT1050_CLK_PLL3_PFD3_454_74M,
> +	       imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base
> + 0xf0,
> +			   3));
> +
> +	/* CCM clocks */
> +	base = dev_read_addr_ptr(dev);
> +	if (base == (void *)FDT_ADDR_T_NONE)
> +		return -EINVAL;
> +
> +	clk_dm(IMXRT1050_CLK_ARM_PODF,
> +	       imx_clk_divider("arm_podf", "pll1_arm",
> +			       base + 0x10, 0, 3));
> +
> +	clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,
> +	       imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
> +			   pre_periph_sels,
> ARRAY_SIZE(pre_periph_sels)));
> +	clk_dm(IMXRT1050_CLK_PERIPH_SEL,
> +	       imx_clk_mux("periph_sel", base + 0x14, 25, 1,
> +			   periph_sels, ARRAY_SIZE(periph_sels)));
> +	clk_dm(IMXRT1050_CLK_USDHC1_SEL,
> +	       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
> +			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
> +	clk_dm(IMXRT1050_CLK_USDHC2_SEL,
> +	       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
> +			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
> +	clk_dm(IMXRT1050_CLK_LPUART_SEL,
> +	       imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
> +			   lpuart_sels, ARRAY_SIZE(lpuart_sels)));
> +	clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,
> +	       imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
> +			   semc_alt_sels,
> ARRAY_SIZE(semc_alt_sels)));
> +	clk_dm(IMXRT1050_CLK_SEMC_SEL,
> +	       imx_clk_mux("semc_sel", base + 0x14, 6, 1,
> +			   semc_sels, ARRAY_SIZE(semc_sels)));
> +	clk_dm(IMXRT1050_CLK_LCDIF_SEL,
> +	       imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
> +			   lcdif_sels, ARRAY_SIZE(lcdif_sels)));
> +
> +	clk_dm(IMXRT1050_CLK_AHB_PODF,
> +	       imx_clk_divider("ahb_podf", "periph_sel",
> +			       base + 0x14, 10, 3));
> +	clk_dm(IMXRT1050_CLK_USDHC1_PODF,
> +	       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
> +			       base + 0x24, 11, 3));
> +	clk_dm(IMXRT1050_CLK_USDHC2_PODF,
> +	       imx_clk_divider("usdhc2_podf", "usdhc2_sel",
> +			       base + 0x24, 16, 3));
> +	clk_dm(IMXRT1050_CLK_LPUART_PODF,
> +	       imx_clk_divider("lpuart_podf", "lpuart_sel",
> +			       base + 0x24, 0, 6));
> +	clk_dm(IMXRT1050_CLK_SEMC_PODF,
> +	       imx_clk_divider("semc_podf", "semc_sel",
> +			       base + 0x14, 16, 3));
> +	clk_dm(IMXRT1050_CLK_LCDIF_PRED,
> +	       imx_clk_divider("lcdif_pred", "lcdif_sel",
> +			       base + 0x38, 12, 3));
> +	clk_dm(IMXRT1050_CLK_LCDIF_PODF,
> +	       imx_clk_divider("lcdif_podf", "lcdif_pred",
> +			       base + 0x18, 23, 3));
> +
> +	clk_dm(IMXRT1050_CLK_USDHC1,
> +	       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80,
> 2));
> +	clk_dm(IMXRT1050_CLK_USDHC2,
> +	       imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80,
> 4));
> +	clk_dm(IMXRT1050_CLK_LPUART1,
> +	       imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c,
> 24));
> +	clk_dm(IMXRT1050_CLK_SEMC,
> +	       imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
> +	clk_dm(IMXRT1050_CLK_LCDIF,
> +	       imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70,
> 28)); +
> +#ifdef CONFIG_SPL_BUILD
> +	struct clk *clk, *clk1;
> +
> +	/* bypass pll1 before setting its rate */
> +	clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
> +	clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
> +	clk_set_parent(clk1, clk);
> +
> +	clk_get_by_id(IMXRT1050_CLK_PLL1_ARM, &clk);
> +	clk_enable(clk);
> +	clk_set_rate(clk, 1056000000UL);
> +
> +	clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
> +	clk_set_parent(clk1, clk);
> +
> +	clk_get_by_id(IMXRT1050_CLK_SEMC_SEL, &clk1);
> +	clk_get_by_id(IMXRT1050_CLK_SEMC_ALT_SEL, &clk);
> +	clk_set_parent(clk1, clk);
> +
> +	clk_get_by_id(IMXRT1050_CLK_PLL2_SYS, &clk);
> +	clk_enable(clk);
> +	clk_set_rate(clk, 528000000UL);
> +
> +	clk_get_by_id(IMXRT1050_CLK_PLL2_BYPASS, &clk1);
> +	clk_set_parent(clk1, clk);
> +
> +	/* Configure PLL3_USB_OTG to 480MHz */
> +	clk_get_by_id(IMXRT1050_CLK_PLL3_USB_OTG, &clk);
> +	clk_enable(clk);
> +	clk_set_rate(clk, 480000000UL);
> +
> +	clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1);
> +	clk_set_parent(clk1, clk);
> +
> +#endif
> +
> +	return 0;
> +}
> +
> +static const struct udevice_id imxrt1050_clk_ids[] = {
> +	{ .compatible = "fsl,imxrt1050-ccm" },
> +	{ },
> +};
> +
> +U_BOOT_DRIVER(imxrt1050_clk) = {
> +	.name = "clk_imxrt1050",
> +	.id = UCLASS_CLK,
> +	.of_match = imxrt1050_clk_ids,
> +	.ops = &imxrt1050_clk_ops,
> +	.probe = imxrt1050_clk_probe,
> +	.flags = DM_FLAG_PRE_RELOC,
> +};
> diff --git a/include/dt-bindings/clock/imxrt1050-clock.h
> b/include/dt-bindings/clock/imxrt1050-clock.h new file mode 100644
> index 0000000000..c174f90c1a
> --- /dev/null
> +++ b/include/dt-bindings/clock/imxrt1050-clock.h
> @@ -0,0 +1,65 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright(C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H
> +#define __DT_BINDINGS_CLOCK_IMXRT1050_H
> +
> +#define IMXRT1050_CLK_DUMMY			0
> +#define IMXRT1050_CLK_CKIL			1
> +#define IMXRT1050_CLK_CKIH			2
> +#define IMXRT1050_CLK_OSC			3
> +#define IMXRT1050_CLK_PLL2_PFD0_352M		4
> +#define IMXRT1050_CLK_PLL2_PFD1_594M		5
> +#define IMXRT1050_CLK_PLL2_PFD2_396M		6
> +#define IMXRT1050_CLK_PLL3_PFD0_720M		7
> +#define IMXRT1050_CLK_PLL3_PFD1_664_62M		8
> +#define IMXRT1050_CLK_PLL3_PFD2_508_24M		9
> +#define IMXRT1050_CLK_PLL3_PFD3_454_74M		10
> +#define IMXRT1050_CLK_PLL2_198M			11
> +#define IMXRT1050_CLK_PLL3_120M			12
> +#define IMXRT1050_CLK_PLL3_80M			13
> +#define IMXRT1050_CLK_PLL3_60M			14
> +#define IMXRT1050_CLK_PLL1_BYPASS		15
> +#define IMXRT1050_CLK_PLL2_BYPASS		16
> +#define IMXRT1050_CLK_PLL3_BYPASS		17
> +#define IMXRT1050_CLK_PLL5_BYPASS		19
> +#define IMXRT1050_CLK_PLL1_REF_SEL		20
> +#define IMXRT1050_CLK_PLL2_REF_SEL		21
> +#define IMXRT1050_CLK_PLL3_REF_SEL		22
> +#define IMXRT1050_CLK_PLL5_REF_SEL		23
> +#define IMXRT1050_CLK_PRE_PERIPH_SEL		24
> +#define IMXRT1050_CLK_PERIPH_SEL		25
> +#define IMXRT1050_CLK_SEMC_ALT_SEL		26
> +#define IMXRT1050_CLK_SEMC_SEL			27
> +#define IMXRT1050_CLK_USDHC1_SEL		28
> +#define IMXRT1050_CLK_USDHC2_SEL		29
> +#define IMXRT1050_CLK_LPUART_SEL		30
> +#define IMXRT1050_CLK_LCDIF_SEL			31
> +#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL	32
> +#define IMXRT1050_CLK_VIDEO_DIV			33
> +#define IMXRT1050_CLK_ARM_PODF			34
> +#define IMXRT1050_CLK_LPUART_PODF		35
> +#define IMXRT1050_CLK_USDHC1_PODF		36
> +#define IMXRT1050_CLK_USDHC2_PODF		37
> +#define IMXRT1050_CLK_SEMC_PODF			38
> +#define IMXRT1050_CLK_AHB_PODF			39
> +#define IMXRT1050_CLK_LCDIF_PRED		40
> +#define IMXRT1050_CLK_LCDIF_PODF		41
> +#define IMXRT1050_CLK_USDHC1			42
> +#define IMXRT1050_CLK_USDHC2			43
> +#define IMXRT1050_CLK_LPUART1			44
> +#define IMXRT1050_CLK_SEMC			45
> +#define IMXRT1050_CLK_LCDIF			46
> +#define IMXRT1050_CLK_PLL1_ARM			47
> +#define IMXRT1050_CLK_PLL2_SYS			48
> +#define IMXRT1050_CLK_PLL3_USB_OTG		49
> +#define IMXRT1050_CLK_PLL4_AUDIO		50
> +#define IMXRT1050_CLK_PLL5_VIDEO		51
> +#define IMXRT1050_CLK_PLL6_ENET			52
> +#define IMXRT1050_CLK_PLL7_USB_HOST		53
> +#define IMXRT1050_CLK_END			54
> +
> +#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */




Best regards,

Lukasz Majewski

--

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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* [PATCH v2 12/21] pinctrl: add i.MXRT driver
  2020-01-10 14:47 ` [PATCH v2 12/21] pinctrl: add i.MXRT driver Giulio Benetti
  2020-01-15 12:47   ` sbabic at denx.de
@ 2020-01-28  8:27   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: Lukasz Majewski @ 2020-01-28  8:27 UTC (permalink / raw)
  To: u-boot

Hi Giulio,

> Add i.MXRT pinctrl driver.

Please add information from where this code was ported (SHA1, branch,
commit name).

Nit tip:

- Please use patman, which will give you a warning if somethinf with
  the commit or commit message is broken.

> 
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
>  drivers/pinctrl/nxp/Kconfig         | 14 ++++++++++
>  drivers/pinctrl/nxp/Makefile        |  1 +
>  drivers/pinctrl/nxp/pinctrl-imxrt.c | 40
> +++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+)
>  create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c
> 
> diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
> index f2e67ca231..ec55351e61 100644
> --- a/drivers/pinctrl/nxp/Kconfig
> +++ b/drivers/pinctrl/nxp/Kconfig
> @@ -99,6 +99,20 @@ config PINCTRL_MXS
>  	  familiy, e.g. i.MX28. This feature depends on device tree
>  	  configuration.
>  
> +config PINCTRL_IMXRT
> +	bool "IMXRT pinctrl driver"
> +	depends on ARCH_IMXRT && PINCTRL_FULL
> +	select DEVRES
> +	select PINCTRL_IMX
> +	help
> +	  Say Y here to enable the imxrt pinctrl driver
> +
> +	  This provides a simple pinctrl driver for i.MXRT SoC
> familiy.
> +	  This feature depends on device tree configuration. This
> driver
> +	  is different from the linux one, this is a simple
> implementation,
> +	  only parses the 'fsl,pins' property and configure related
> +	  registers.
> +
>  config PINCTRL_VYBRID
>  	bool "Vybrid (vf610) pinctrl driver"
>  	depends on ARCH_VF610 && PINCTRL_FULL
> diff --git a/drivers/pinctrl/nxp/Makefile
> b/drivers/pinctrl/nxp/Makefile index b86448aac9..066ca75b65 100644
> --- a/drivers/pinctrl/nxp/Makefile
> +++ b/drivers/pinctrl/nxp/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_IMX8)		+=
> pinctrl-imx8.o obj-$(CONFIG_PINCTRL_IMX8M)		+=
> pinctrl-imx8m.o obj-$(CONFIG_PINCTRL_MXS)		+=
> pinctrl-mxs.o obj-$(CONFIG_PINCTRL_VYBRID)		+=
> pinctrl-vf610.o +obj-$(CONFIG_PINCTRL_IMXRT)		+=
> pinctrl-imxrt.o diff --git a/drivers/pinctrl/nxp/pinctrl-imxrt.c
> b/drivers/pinctrl/nxp/pinctrl-imxrt.c new file mode 100644
> index 0000000000..4a93941927
> --- /dev/null
> +++ b/drivers/pinctrl/nxp/pinctrl-imxrt.c
> @@ -0,0 +1,40 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +
> +#include "pinctrl-imx.h"
> +
> +static struct imx_pinctrl_soc_info imxrt_pinctrl_soc_info = {
> +	.flags = ZERO_OFFSET_VALID,
> +};
> +
> +static int imxrt_pinctrl_probe(struct udevice *dev)
> +{
> +	struct imx_pinctrl_soc_info *info =
> +		(struct imx_pinctrl_soc_info
> *)dev_get_driver_data(dev); +
> +	return imx_pinctrl_probe(dev, info);
> +}
> +
> +static const struct udevice_id imxrt_pinctrl_match[] = {
> +	{ .compatible = "fsl,imxrt-iomuxc",
> +	  .data = (ulong)&imxrt_pinctrl_soc_info },
> +	{ /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(imxrt_pinctrl) = {
> +	.name = "imxrt-pinctrl",
> +	.id = UCLASS_PINCTRL,
> +	.of_match = of_match_ptr(imxrt_pinctrl_match),
> +	.probe = imxrt_pinctrl_probe,
> +	.remove = imx_pinctrl_remove,
> +	.priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
> +	.ops = &imx_pinctrl_ops,
> +	.flags = DM_FLAG_PRE_RELOC,
> +};

Reviewed-by: Lukasz Majewski <lukma@denx.de>

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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* [PATCH v2 13/21] gpio: mxc_gpio: add support for i.MXRT1050
  2020-01-10 14:47 ` [PATCH v2 13/21] gpio: mxc_gpio: add support for i.MXRT1050 Giulio Benetti
  2020-01-15 12:46   ` sbabic at denx.de
@ 2020-01-28  8:27   ` Lukasz Majewski
  1 sibling, 0 replies; 54+ messages in thread
From: Lukasz Majewski @ 2020-01-28  8:27 UTC (permalink / raw)
  To: u-boot

On Fri, 10 Jan 2020 15:47:03 +0100
Giulio Benetti <giulio.benetti@benettiengineering.com> wrote:

> Add i.MXRT1050 support, there are 5 GPIO banks.
> 
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> V1->V2:
> * introduced this patch
> ---
>  drivers/gpio/mxc_gpio.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
> index 6592d141d3..c924e52f07 100644
> --- a/drivers/gpio/mxc_gpio.c
> +++ b/drivers/gpio/mxc_gpio.c
> @@ -41,14 +41,15 @@ static unsigned long gpio_ports[] = {
>  #if defined(CONFIG_MX25) || defined(CONFIG_MX27) ||
> defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6)
> || \ defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
> -		defined(CONFIG_ARCH_IMX8)
> +		defined(CONFIG_ARCH_IMX8) ||
> defined(CONFIG_IMXRT1050) [3] = GPIO4_BASE_ADDR,
>  #endif
>  #if defined(CONFIG_MX27) || defined(CONFIG_MX53) ||
> defined(CONFIG_MX6) || \ defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
> || \
> -		defined(CONFIG_ARCH_IMX8)
> +		defined(CONFIG_ARCH_IMX8) ||
> defined(CONFIG_IMXRT1050) [4] = GPIO5_BASE_ADDR,
> -#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) ||
> defined(CONFIG_IMX8M)) +#if !(defined(CONFIG_MX6UL) ||
> defined(CONFIG_MX6ULL) || \
> +		defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT1050))
>  	[5] = GPIO6_BASE_ADDR,
>  #endif
>  #endif

Reviewed-by: Lukasz Majewski <lukma@denx.de>


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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* [PATCH v2 14/21] ARM: dts: imxrt1050: add dtsi file
  2020-01-10 14:47 ` [PATCH v2 14/21] ARM: dts: imxrt1050: add dtsi file Giulio Benetti
  2020-01-15 12:47   ` sbabic at denx.de
@ 2020-01-28  8:31   ` Lukasz Majewski
  2020-01-28 18:48     ` Giulio Benetti
  1 sibling, 1 reply; 54+ messages in thread
From: Lukasz Majewski @ 2020-01-28  8:31 UTC (permalink / raw)
  To: u-boot

Hi Giulio,

> Add dtsi file for i.MXRT1050.
> 

Please add information from where this code was ported (as I've pointed
out in other mails).

Also a tip:

To avoid extra dtsi maintenance burden, there are u-boot*.dtsi files
(in e.g. arch/arm/dts/) which add extra properties (U-boot specific).

In that way "original" dtsi (from e.g. Linux) are kept separated from
U-Boot adjustments).


> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
>  arch/arm/dts/imxrt1050.dtsi                  | 146 +++
>  include/dt-bindings/pinctrl/pins-imxrt1050.h | 993
> +++++++++++++++++++ 2 files changed, 1139 insertions(+)
>  create mode 100644 arch/arm/dts/imxrt1050.dtsi
>  create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h
> 
> diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
> new file mode 100644
> index 0000000000..b1d98e6feb
> --- /dev/null
> +++ b/arch/arm/dts/imxrt1050.dtsi
> @@ -0,0 +1,146 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#include "skeleton.dtsi"
> +#include "armv7-m.dtsi"
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/imxrt1050-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/memory/imxrt-sdram.h>
> +
> +/ {
> +	aliases {
> +		gpio0 = &gpio1;
> +		gpio1 = &gpio2;
> +		gpio2 = &gpio3;
> +		gpio3 = &gpio4;
> +		gpio4 = &gpio5;
> +		mmc0 = &usdhc1;
> +		serial0 = &lpuart1;
> +	};
> +
> +	clocks {
> +		u-boot,dm-spl;
> +
> +		osc {
> +			u-boot,dm-spl;
> +			compatible = "fsl,imx-osc", "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <24000000>;
> +		};
> +	};
> +
> +	soc {
> +		u-boot,dm-spl;
> +
> +		semc: semc at 402f0000 {
> +			u-boot,dm-spl;
> +			compatible = "fsl,imxrt-semc";
> +			reg = <0x402f0000 0x4000>;
> +			clocks = <&clks IMXRT1050_CLK_SEMC>;
> +			pinctrl-0 = <&pinctrl_semc>;
> +			pinctrl-names = "default";
> +			status = "okay";
> +		};
> +
> +		lpuart1: serial at 40184000 {
> +			compatible = "fsl,imxrt-lpuart";
> +			reg = <0x40184000 0x4000>;
> +			interrupts = <GIC_SPI 20
> IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks IMXRT1050_CLK_LPUART1>;
> +			clock-names = "per";
> +			status = "disabled";
> +		};
> +
> +		iomuxc: iomuxc at 401f8000 {
> +			compatible = "fsl,imxrt-iomuxc";
> +			reg = <0x401f8000 0x4000>;
> +			fsl,mux_mask = <0x7>;
> +		};
> +
> +		clks: ccm at 400fc000 {
> +			u-boot,dm-spl;
> +			compatible = "fsl,imxrt1050-ccm";
> +			reg = <0x400fc000 0x4000>;
> +			interrupts = <GIC_SPI 95
> IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 96
> IRQ_TYPE_LEVEL_HIGH>;
> +			#clock-cells = <1>;
> +		};
> +
> +		usdhc1: usdhc at 402c0000 {
> +			u-boot,dm-spl;
> +			compatible = "fsl,imxrt-usdhc";
> +			reg = <0x402c0000 0x10000>;
> +			interrupts = <GIC_SPI 110
> IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks IMXRT1050_CLK_USDHC1>;
> +			clock-names = "per";
> +			bus-width = <4>;
> +			fsl,tuning-start-tap = <20>;
> +			fsl,tuning-step= <2>;
> +			status = "disabled";
> +		};
> +
> +		gpio1: gpio at 401b8000 {
> +			u-boot,dm-spl;
> +			compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> +			reg = <0x401b8000 0x4000>;
> +			interrupts = <GIC_SPI 80
> IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 81
> IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpio2: gpio at 401bc000 {
> +			u-boot,dm-spl;
> +			compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> +			reg = <0x401bc000 0x4000>;
> +			interrupts = <GIC_SPI 82
> IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpio3: gpio at 401c0000 {
> +			u-boot,dm-spl;
> +			compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> +			reg = <0x401c0000 0x4000>;
> +			interrupts = <GIC_SPI 84
> IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpio4: gpio at 401c4000 {
> +			u-boot,dm-spl;
> +			compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> +			reg = <0x401c4000 0x4000>;
> +			interrupts = <GIC_SPI 86
> IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 87
> IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpio5: gpio at 400c0000 {
> +			u-boot,dm-spl;
> +			compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> +			reg = <0x400c0000 0x4000>;
> +			interrupts = <GIC_SPI 88
> IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +	};
> +};
> diff --git a/include/dt-bindings/pinctrl/pins-imxrt1050.h
> b/include/dt-bindings/pinctrl/pins-imxrt1050.h new file mode 100644
> index 0000000000..a29031ab3d
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/pins-imxrt1050.h
> @@ -0,0 +1,993 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
> +#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
> +
> +#define IMX_PAD_SION	0x40000000
> +
> +/*
> + * The pin function ID is a tuple of
> + * <mux_reg conf_reg input_reg mux_mode input_val>
> + */
> +
> +#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
> 	0x014 0x204 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A
> 0x014 0x204 0x494 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK
> 0x014 0x204 0x500 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2
> 	0x014 0x204 0x60C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00
> 	0x014 0x204 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00
> 0x014 0x204 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
> 0x018 0x208 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B
> 0x018 0x208 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0
> 	0x018 0x208 0x4FC 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3
> 	0x018 0x208 0x610 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01
> 	0x018 0x208 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01
> 0x018 0x208 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
> 0x01C 0x20C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A
> 0x01C 0x20C 0x498 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO
> 0x01C 0x20C 0x508 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4
> 	0x01C 0x20C 0x614 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02
> 	0x01C 0x20C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02
> 0x01C 0x20C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
> 0x020 0x210 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B
> 0x020 0x210 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI
> 0x020 0x210 0x504 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5
> 	0x020 0x210 0x618 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03
> 	0x020 0x210 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03
> 0x020 0x210 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
> 0x024 0x214 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A
> 0x024 0x214 0x49C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA			0x024
> 0x214 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6
> 	0x024 0x214 0x61C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04
> 	0x024 0x214 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04
> 0x024 0x214 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
> 0x028 0x218 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B
> 0x028 0x218 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC			0x028
> 0x218 0x5C4 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7
> 	0x028 0x218 0x620 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05
> 	0x028 0x218 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05
> 0x028 0x218 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
> 0x02C 0x21C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A
> 0x02C 0x21C 0x478 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK			0x02C
> 0x21C 0x5C0 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8
> 	0x02C 0x21C 0x624 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06
> 	0x02C 0x21C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06
> 0x02C 0x21C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
> 0x030 0x220 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B
> 0x030 0x220 0x488 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK
> 0x030 0x220 0x5B0 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9
> 	0x030 0x220 0x628 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07
> 	0x030 0x220 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07
> 0x030 0x220 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
> 0x034 0x224 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A
> 0x034 0x224 0x47C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA			0x034
> 0x224 0x5B8 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17			0x034
> 0x224 0x62C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08
> 	0x034 0x224 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08
> 0x034 0x224 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
> 	0x038 0x228 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B
> 0x038 0x228 0x48C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC			0x038
> 0x228 0x5BC 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX
> 	0x038 0x228 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09
> 	0x038 0x228 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09
> 0x038 0x228 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
> 	0x03C 0x22C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A
> 0x03C 0x22C 0x480 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK			0x03C
> 0x22C 0x5B4 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX
> 	0x03C 0x22C 0x450 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10
> 	0x03C 0x22C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10
> 0x03C 0x22C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
> 	0x040 0x230 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B
> 0x040 0x230 0x490 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA
> 0x040 0x230 0x4E8 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B
> 0x040 0x230 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11
> 	0x040 0x230 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11
> 0x040 0x230 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
> 	0x044 0x234 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24			0x044
> 0x234 0x640 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL
> 0x044 0x234 0x4E4 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP
> 0x044 0x234 0x5D8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A
> 0x044 0x234 0x454 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12
> 0x044 0x234 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
> 	0x048 0x238 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25			0x048
> 0x238 0x650 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD
> 	0x048 0x238 0x53C 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT
> 0x048 0x238 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B
> 0x048 0x238 0x464 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13
> 0x048 0x238 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
> 	0x04C 0x23C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19			0x04C
> 0x23C 0x654 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD
> 	0x04C 0x23C 0x538 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT
> 0x04C 0x23C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1
> 	0x04C 0x23C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14
> 0x04C 0x23C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
> 	0x050 0x240 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20			0x050
> 0x240 0x634 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B
> 0x050 0x240 0x534 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT
> 0x050 0x240 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0
> 	0x050 0x240 0x57C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15
> 0x050 0x240 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
> 	0x054 0x244 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21			0x054
> 0x244 0x658 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B
> 0x054 0x244 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN
> 0x054 0x244 0x5C8 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1
> 	0x054 0x244 0x580 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16
> 0x054 0x244 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
> 	0x058 0x248 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A
> 0x058 0x248 0x4A0 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B
> 0x058 0x248 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX
> 	0x058 0x248 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2
> 	0x058 0x248 0x584 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17
> 0x058 0x248 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
> 	0x05C 0x24C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B
> 0x05C 0x24C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B
> 0x05C 0x24C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX
> 	0x05C 0x24C 0x44C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3
> 	0x05C 0x24C 0x588 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18
> 0x05C 0x24C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL
> 0x05C 0x24C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
> 	0x060 0x250 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A
> 0x060 0x250 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD
> 	0x060 0x250 0x544 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01
> 0x060 0x250 0x438 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0
> 	0x060 0x250 0x56C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19
> 0x060 0x250 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5
> 0x060 0x250 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
> 	0x064 0x254 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B
> 0x064 0x254 0x484 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD
> 	0x064 0x254 0x540 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00
> 0x064 0x254 0x434 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0
> 	0x064 0x254 0x570 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20
> 0x064 0x254 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
> 0x068 0x258 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A
> 0x068 0x258 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA
> 0x068 0x258 0x4E0 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01
> 0x068 0x258 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2
> 	0x068 0x258 0x574 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21
> 0x068 0x258 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
> 0x06C 0x25C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B
> 0x06C 0x25C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL
> 0x06C 0x25C 0x4DC 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00
> 0x06C 0x25C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3
> 	0x06C 0x25C 0x578 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22
> 0x06C 0x25C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
> 	0x070 0x260 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A
> 0x070 0x260 0x458 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD
> 	0x070 0x260 0x54C 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN
> 0x070 0x260 0x43C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2
> 0x070 0x260 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23
> 0x070 0x260 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
> 0x074 0x264 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B
> 0x074 0x264 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD
> 	0x074 0x264 0x548 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN
> 0x074 0x264 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1
> 0x074 0x264 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24
> 0x074 0x264 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
> 0x078 0x268 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A
> 0x078 0x268 0x45C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD
> 	0x078 0x268 0x554 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK
> 	0x078 0x268 0x448 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK			0x078
> 0x268 0x42C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25
> 0x078 0x268 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
> 0x07C 0x26C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B
> 0x07C 0x26C 0x46C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD
> 	0x07C 0x26C 0x550 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER
> 0x07C 0x26C 0x440 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12
> 	0x07C 0x26C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26
> 0x07C 0x26C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
> 0x080 0x270 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A
> 0x080 0x270 0x460 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B
> 0x080 0x270 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK
> 0x080 0x270 0x4F0 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13
> 	0x080 0x270 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27
> 0x080 0x270 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
> 0x084 0x274 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B
> 0x084 0x274 0x470 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B
> 0x084 0x274 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO
> 0x084 0x274 0x4F8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14
> 	0x084 0x274 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28
> 0x084 0x274 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
> 0x088 0x278 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A
> 0x088 0x278 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B
> 0x088 0x278 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI
> 0x088 0x278 0x4F4 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15
> 	0x088 0x278 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29
> 0x088 0x278 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
> 0x08C 0x27C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B
> 0x08C 0x27C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B
> 0x08C 0x27C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0
> 	0x08C 0x27C 0x4EC 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23
> 0x08C 0x27C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30
> 0x08C 0x27C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
> 0x090 0x280 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A
> 0x090 0x280 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD
> 	0x090 0x280 0x55C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1
> 	0x090 0x280 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22
> 0x090 0x280 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31
> 0x090 0x280 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
> 0x094 0x284 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B
> 0x094 0x284 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD
> 	0x094 0x284 0x558 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY
> 0x094 0x284 0x3FC 0x3 0x4 +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21
> 0x094 0x284 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18
> 0x094 0x284 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
> 0x098 0x288 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A
> 0x098 0x288 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B
> 0x098 0x288 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA			0x098
> 0x288 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20
> 0x098 0x288 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19
> 0x098 0x288 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
> 0x09C 0x28C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B
> 0x09C 0x28C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT
> 0x09C 0x28C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC			0x09C
> 0x28C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19
> 0x09C 0x28C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20
> 0x09C 0x28C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
> 0x0A0 0x290 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18			0x0A0
> 0x290 0x630 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1
> 0x0A0 0x290 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK			0x0A0
> 0x290 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18
> 0x0A0 0x290 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21
> 0x0A0 0x290 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B
> 	0x0A0 0x290 0x5D4 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
> 0x0A4 0x294 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22			0x0A4
> 0x294 0x638 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2
> 0x0A4 0x294 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA			0x0A4
> 0x294 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17
> 0x0A4 0x294 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22
> 0x0A4 0x294 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP
> 0x0A4 0x294 0x5D8 0x6 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
> 0x0A8 0x298 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23			0x0A8
> 0x298 0x63C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3
> 0x0A8 0x298 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK
> 0x0A8 0x298 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16
> 0x0A8 0x298 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23
> 0x0A8 0x298 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP
> 0x0A8 0x298 0x608 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
> 0x0AC 0x29C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A
> 0x0AC 0x29C 0x454 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD
> 	0x0AC 0x29C 0x564 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK			0x0AC
> 0x29C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD
> 0x0AC 0x29C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24
> 0x0AC 0x29C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT
> 0x0AC 0x29C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
> 0x0B0 0x2A0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B
> 0x0B0 0x2A0 0x464 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD
> 	0x0B0 0x2A0 0x560 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC			0x0B0
> 0x2A0 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B
> 0x0B0 0x2A0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25
> 0x0B0 0x2A0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B
> 	0x0B0 0x2A0 0x5E0 0x6 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY
> 0x0B4 0x2A4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2
> 0x0B4 0x2A4 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2
> 	0x0B4 0x2A4 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC
> 	0x0B4 0x2A4 0x5CC 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC
> 0x0B4 0x2A4 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26
> 0x0B4 0x2A4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B
> 0x0B4 0x2A4 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0
> 0x0B8 0x2A8 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1
> 0x0B8 0x2A8 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3
> 	0x0B8 0x2A8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR			0x0B8
> 0x2A8 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO
> 0x0B8 0x2A8 0x430 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27
> 0x0B8 0x2A8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT
> 0x0B8 0x2A8 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A
> 0x0BC 0x2AC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14
> 0x0BC 0x2AC 0x644 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K
> 0x0BC 0x2AC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID
> 0x0BC 0x2AC 0x3F8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS
> 0x0BC 0x2AC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00			0x0BC
> 0x2AC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B
> 0x0BC 0x2AC 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK			0x0BC
> 0x2AC 0x510 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B
> 0x0C0 0x2B0 0x484 0x0 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15
> 0x0C0 0x2B0 0x648 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M
> 0x0C0 0x2B0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID
> 0x0C0 0x2B0 0x3F4 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS
> 0x0C0 0x2B0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01			0x0C0
> 0x2B0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B
> 	0x0C0 0x2B0 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO			0x0C0
> 0x2B0 0x518 0x7 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX
> 0x0C4 0x2B4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16
> 0x0C4 0x2B4 0x64C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD
> 0x0C4 0x2B4 0x554 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR
> 0x0C4 0x2B4 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X
> 0x0C4 0x2B4 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02			0x0C4
> 0x2B4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ
> 0x0C4 0x2B4 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI			0x0C4
> 0x2B4 0x514 0x7 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX
> 0x0C8 0x2B8 0x450 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17
> 0x0C8 0x2B8 0x62C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD
> 0x0C8 0x2B8 0x550 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC
> 0x0C8 0x2B8 0x5D0 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X
> 0x0C8 0x2B8 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03			0x0C8
> 0x2B8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M
> 0x0C8 0x2B8 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0
> 0x0C8 0x2B8 0x50C 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00
> 0x0CC 0x2BC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT
> 	0x0CC 0x2BC 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03
> 0x0CC 0x2BC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC
> 0x0CC 0x2BC 0x5C4 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09			0x0CC
> 0x2BC 0x41C 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04			0x0CC
> 0x2BC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00
> 0x0CC 0x2BC 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1
> 0x0CC 0x2BC 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01
> 0x0D0 0x2C0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT
> 0x0D0 0x2C0 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02
> 0x0D0 0x2C0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK
> 0x0D0 0x2C0 0x5C0 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08			0x0D0
> 0x2C0 0x418 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05			0x0D0
> 0x2C0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17
> 0x0D0 0x2C0 0x62C 0x6 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2
> 0x0D0 0x2C0 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS
> 0x0D4 0x2C4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1
> 0x0D4 0x2C4 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK
> 0x0D4 0x2C4 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK
> 0x0D4 0x2C4 0x5B4 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07			0x0D4
> 0x2C4 0x414 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06			0x0D4
> 0x2C4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18
> 0x0D4 0x2C4 0x630 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3
> 0x0D4 0x2C4 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK
> 0x0D8 0x2C8 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2
> 0x0D8 0x2C8 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER			0x0D8
> 0x2C8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC
> 0x0D8 0x2C8 0x5BC 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06			0x0D8
> 0x2C8 0x410 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07			0x0D8
> 0x2C8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19
> 0x0D8 0x2C8 0x654 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT
> 0x0D8 0x2C8 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD
> 0x0DC 0x2CC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3
> 0x0DC 0x2CC 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03
> 0x0DC 0x2CC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA
> 0x0DC 0x2CC 0x5B8 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05			0x0DC
> 0x2CC 0x40C 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08			0x0DC
> 0x2CC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20
> 0x0DC 0x2CC 0x634 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN
> 0x0DC 0x2CC 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI
> 0x0E0 0x2D0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A
> 0x0E0 0x2D0 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02
> 0x0E0 0x2D0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA
> 0x0E0 0x2D0 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04			0x0E0
> 0x2D0 0x408 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09			0x0E0
> 0x2D0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21
> 0x0E0 0x2D0 0x658 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK
> 0x0E0 0x2D0 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO
> 0x0E4 0x2D4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A
> 0x0E4 0x2D4 0x454 0x1 0x3 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS
> 0x0E4 0x2D4 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK
> 	0x0E4 0x2D4 0x5B0 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03			0x0E4
> 0x2D4 0x404 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10			0x0E4
> 0x2D4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22
> 0x0E4 0x2D4 0x638 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT
> 0x0E4 0x2D4 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB			0x0E8
> 0x2D8 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B
> 0x0E8 0x2D8 0x464 0x1 0x3 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL
> 0x0E8 0x2D8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B
> 0x0E8 0x2D8 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02			0x0E8
> 0x2D8 0x400 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11			0x0E8
> 0x2D8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23
> 0x0E8 0x2D8 0x63C 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN
> 0x0E8 0x2D8 0x444 0x7 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL			0x0EC
> 0x2DC 0x4E4 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY
> 0x0EC 0x2DC 0x3FC 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
> 0x0EC 0x2DC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B
> 0x0EC 0x2DC 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X
> 0x0EC 0x2DC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12			0x0EC
> 0x2DC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT
> 0x0EC 0x2DC 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI
> 0x0EC 0x2DC 0x568 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA			0x0F0
> 0x2E0 0x4E8 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK
> 0x0F0 0x2E0 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
> 0x0F0 0x2E0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B
> 	0x0F0 0x2E0 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X
> 0x0F0 0x2E0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13			0x0F0
> 0x2E0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN
> 0x0F0 0x2E0 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M
> 0x0F0 0x2E0 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC
> 0x0F4 0x2E4 0x5CC 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24
> 0x0F4 0x2E4 0x640 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B
> 0x0F4 0x2E4 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT
> 0x0F4 0x2E4 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC
> 	0x0F4 0x2E4 0x428 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14			0x0F4
> 0x2E4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX
> 0x0F4 0x2E4 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR
> 0x0F8 0x2E8 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25
> 0x0F8 0x2E8 0x650 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B
> 0x0F8 0x2E8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN
> 0x0F8 0x2E8 0x444 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC
> 	0x0F8 0x2E8 0x420 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15			0x0F8
> 0x2E8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX
> 0x0F8 0x2E8 0x450 0x6 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB
> 0x0F8 0x2E8 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID
> 0x0FC 0x2EC 0x3F8 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0
> 0x0FC 0x2EC 0x57C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B
> 0x0FC 0x2EC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL			0x0FC
> 0x2EC 0x4CC 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B
> 0x0FC 0x2EC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16			0x0FC
> 0x2EC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP
> 	0x0FC 0x2EC 0x5D8 0x6 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07
> 	0x0FC 0x2EC 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR
> 0x100 0x2F0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1
> 0x100 0x2F0 0x580 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B
> 0x100 0x2F0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA			0x100
> 0x2F0 0x4D0 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY
> 0x100 0x2F0 0x3FC 0x4 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17			0x100
> 0x2F0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT
> 0x100 0x2F0 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07
> 	0x100 0x2F0 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID
> 0x104 0x2F4 0x3F4 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2
> 0x104 0x2F4 0x584 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD
> 0x104 0x2F4 0x530 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT
> 	0x104 0x2F4 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT
> 0x104 0x2F4 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18			0x104
> 0x2F4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B
> 0x104 0x2F4 0x5D4 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06
> 	0x104 0x2F4 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC
> 0x108 0x2F8 0x5D0 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3
> 0x108 0x2F8 0x588 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD
> 0x108 0x2F8 0x52C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN
> 0x108 0x2F8 0x5C8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN
> 0x108 0x2F8 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19			0x108
> 0x2F8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B
> 0x108 0x2F8 0x5E0 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06
> 	0x108 0x2F8 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3
> 0x10C 0x2FC 0x4C4 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC
> 0x10C 0x2FC 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B
> 0x10C 0x2FC 0x534 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK
> 0x10C 0x2FC 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK			0x10C
> 0x2FC 0x424 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20			0x10C
> 0x2FC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0
> 0x10C 0x2FC 0x5E8 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05
> 	0x10C 0x2FC 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2
> 0x110 0x300 0x4C0 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO
> 	0x110 0x300 0x430 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B
> 0x110 0x300 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT
> 	0x110 0x300 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK
> 0x110 0x300 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21			0x110
> 0x300 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1
> 0x110 0x300 0x5EC 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05
> 	0x110 0x300 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1
> 0x114 0x304 0x4BC 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA			0x114
> 0x304 0x4E0 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD
> 0x114 0x304 0x53C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK			0x114
> 0x304 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC
> 	0x114 0x304 0x428 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22			0x114
> 0x304 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2
> 0x114 0x304 0x5F0 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04
> 	0x114 0x304 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0
> 0x118 0x308 0x4B8 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL			0x118
> 0x308 0x4DC 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD
> 0x118 0x308 0x538 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK
> 0x118 0x308 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC
> 	0x118 0x308 0x420 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23			0x118
> 0x308 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3
> 0x118 0x308 0x5F4 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04
> 	0x118 0x308 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B
> 0x11C 0x30C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A
> 0x11C 0x30C 0x494 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX
> 0x11C 0x30C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY
> 0x11C 0x30C 0x3FC 0x3 0x3 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09			0x11C
> 0x30C 0x41C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24			0x11C
> 0x30C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD			0x11C
> 0x30C 0x5E4 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03
> 	0x11C 0x30C 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS
> 0x120 0x310 0x4A4 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A
> 0x120 0x310 0x498 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX
> 0x120 0x310 0x44C 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK
> 	0x120 0x310 0x58C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08			0x120
> 0x310 0x418 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25			0x120
> 0x310 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK			0x120
> 0x310 0x5DC 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03
> 	0x120 0x310 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3
> 0x124 0x314 0x4B4 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B
> 0x124 0x314 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD
> 0x124 0x314 0x564 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC
> 0x124 0x314 0x5A4 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07			0x124
> 0x314 0x414 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26			0x124
> 0x314 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP
> 	0x124 0x314 0x608 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02
> 	0x124 0x314 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2
> 0x128 0x318 0x4B0 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B
> 	0x128 0x318 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD
> 0x128 0x318 0x560 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK
> 0x128 0x318 0x590 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06			0x128
> 0x318 0x410 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27			0x128
> 0x318 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B
> 0x128 0x318 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02
> 	0x128 0x318 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1
> 0x12C 0x31C 0x4AC 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT
> 	0x12C 0x31C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0
> 0x12C 0x31C 0x50C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00
> 0x12C 0x31C 0x594 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05			0x12C
> 0x31C 0x40C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28			0x12C
> 0x31C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4
> 0x12C 0x31C 0x5F8 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01
> 	0x12C 0x31C 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0
> 0x130 0x320 0x4A8 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT
> 	0x130 0x320 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI			0x130
> 0x320 0x514 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00
> 0x130 0x320 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04			0x130
> 0x320 0x408 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29			0x130
> 0x320 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5
> 0x130 0x320 0x5FC 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01
> 	0x130 0x320 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK
> 0x134 0x324 0x4C8 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT
> 	0x134 0x324 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO			0x134
> 0x324 0x518 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK
> 0x134 0x324 0x5A8 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03			0x134
> 0x324 0x404 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30			0x134
> 0x324 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6
> 0x134 0x324 0x600 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00
> 	0x134 0x324 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B
> 0x138 0x328 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT
> 	0x138 0x328 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK			0x138
> 0x328 0x510 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC
> 0x138 0x328 0x5AC 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02			0x138
> 0x328 0x400 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31			0x138
> 0x328 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7
> 0x138 0x328 0x604 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00
> 	0x138 0x328 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK
> 0x13C 0x32C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0
> 0x13C 0x32C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT
> 0x13C 0x32C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0
> 0x13C 0x32C 0x51C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00
> 0x13C 0x32C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00
> 0x13C 0x32C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1
> 0x13C 0x32C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE
> 0x140 0x330 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1
> 0x140 0x330 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT
> 0x140 0x330 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI
> 0x140 0x330 0x524 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01
> 0x140 0x330 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01
> 0x140 0x330 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2
> 0x140 0x330 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC
> 0x144 0x334 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2
> 0x144 0x334 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX
> 0x144 0x334 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO
> 0x144 0x334 0x528 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02
> 0x144 0x334 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02
> 0x144 0x334 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3
> 0x144 0x334 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC
> 0x148 0x338 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0
> 0x148 0x338 0x56C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX
> 0x148 0x338 0x44C 0x2 0x3 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK
> 0x148 0x338 0x520 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03
> 0x148 0x338 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03
> 0x148 0x338 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB
> 0x148 0x338 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00
> 0x14C 0x33C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1
> 0x14C 0x33C 0x570 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL
> 0x14C 0x33C 0x4D4 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00
> 0x14C 0x33C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04
> 0x14C 0x33C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04
> 0x14C 0x33C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00
> 	0x14C 0x33C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01
> 0x150 0x340 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2
> 0x150 0x340 0x574 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA
> 0x150 0x340 0x4D8 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01
> 0x150 0x340 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05
> 0x150 0x340 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05
> 0x150 0x340 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01
> 	0x150 0x340 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02
> 0x154 0x344 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0
> 0x154 0x344 0x57C 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A
> 0x154 0x344 0x478 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02
> 0x154 0x344 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06
> 0x154 0x344 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06
> 0x154 0x344 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02
> 	0x154 0x344 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03
> 0x158 0x348 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1
> 0x158 0x348 0x580 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B
> 0x158 0x348 0x488 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03
> 0x158 0x348 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07
> 0x158 0x348 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07
> 0x158 0x348 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03
> 	0x158 0x348 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04
> 0x15C 0x34C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2
> 0x15C 0x34C 0x584 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A
> 0x15C 0x34C 0x47C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD
> 0x15C 0x34C 0x53C 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08
> 0x15C 0x34C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08
> 0x15C 0x34C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04
> 	0x15C 0x34C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05
> 0x160 0x350 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0
> 0x160 0x350 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B
> 0x160 0x350 0x48C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD
> 0x160 0x350 0x538 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09
> 0x160 0x350 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09
> 0x160 0x350 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05
> 	0x160 0x350 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06
> 0x164 0x354 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1
> 0x164 0x354 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A
> 0x164 0x354 0x480 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03
> 0x164 0x354 0x598 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10
> 0x164 0x354 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10
> 0x164 0x354 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06
> 	0x164 0x354 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07
> 0x168 0x358 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2
> 0x168 0x358 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B
> 0x168 0x358 0x490 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02
> 0x168 0x358 0x59C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11
> 0x168 0x358 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11
> 0x168 0x358 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07
> 	0x168 0x358 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08
> 0x16C 0x35C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10
> 	0x16C 0x35C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK			0x16C
> 0x35C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01
> 0x16C 0x35C 0x5A0 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12
> 0x16C 0x35C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12
> 0x16C 0x35C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08
> 	0x16C 0x35C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09
> 0x170 0x360 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11
> 	0x170 0x360 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO			0x170
> 0x360 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK
> 0x170 0x360 0x58C 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13
> 0x170 0x360 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13
> 0x170 0x360 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09
> 	0x170 0x360 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10
> 0x174 0x364 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12
> 	0x174 0x364 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV
> 	0x174 0x364 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC
> 	0x174 0x364 0x5A4 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14
> 0x174 0x364 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14
> 0x174 0x364 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10
> 	0x174 0x364 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11
> 0x178 0x368 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13
> 	0x178 0x368 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV
> 	0x178 0x368 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK
> 	0x178 0x368 0x590 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15
> 0x178 0x368 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15
> 0x178 0x368 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11
> 	0x178 0x368 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12
> 0x17C 0x36C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14
> 	0x17C 0x36C 0x644 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD
> 0x17C 0x36C 0x544 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00
> 0x17C 0x36C 0x594 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16
> 0x17C 0x36C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16
> 0x17C 0x36C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A
> 0x17C 0x36C 0x454 0x6 0x4 + +#define
> MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13
> 0x180 0x370 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15
> 	0x180 0x370 0x648 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD
> 0x180 0x370 0x540 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00
> 0x180 0x370 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17
> 0x180 0x370 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17
> 0x180 0x370 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B
> 0x180 0x370 0x464 0x6 0x4 + +#define
> MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14
> 0x184 0x374 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16
> 	0x184 0x374 0x64C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2
> 0x184 0x374 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK
> 	0x184 0x374 0x5A8 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18
> 0x184 0x374 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18
> 0x184 0x374 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A
> 0x184 0x374 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15
> 0x188 0x378 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17
> 	0x188 0x378 0x62C 0x1 0x3 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1
> 0x188 0x378 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC
> 	0x188 0x378 0x5AC 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19
> 0x188 0x378 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19
> 0x188 0x378 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B
> 0x188 0x378 0x484 0x6 0x3 + +#define
> MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16
> 0x18C 0x37C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0
> 0x18C 0x37C 0x51C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15
> 0x18C 0x37C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00
> 0x18C 0x37C 0x434 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20
> 0x18C 0x37C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20
> 0x18C 0x37C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17
> 0x190 0x380 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI
> 0x190 0x380 0x524 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14
> 0x190 0x380 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01
> 0x190 0x380 0x438 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21
> 0x190 0x380 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21
> 0x190 0x380 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18
> 0x194 0x384 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO
> 0x194 0x384 0x528 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13
> 0x194 0x384 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN
> 0x194 0x384 0x43C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22
> 0x194 0x384 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22
> 0x194 0x384 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19
> 0x198 0x388 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK
> 0x198 0x388 0x520 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12
> 0x198 0x388 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00
> 0x198 0x388 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23
> 0x198 0x388 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23
> 0x198 0x388 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20
> 0x19C 0x38C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3
> 0x19C 0x38C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11
> 0x19C 0x38C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01
> 0x19C 0x38C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24
> 0x19C 0x38C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24
> 0x19C 0x38C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX
> 0x19C 0x38C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21
> 0x1A0 0x390 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3
> 0x1A0 0x390 0x578 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10
> 0x1A0 0x390 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN
> 0x1A0 0x390 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25
> 0x1A0 0x390 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25
> 0x1A0 0x390 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX
> 0x1A0 0x390 0x450 0x6 0x3 + +#define
> MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22
> 0x1A4 0x394 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3
> 0x1A4 0x394 0x588 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00
> 0x1A4 0x394 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK
> 0x1A4 0x394 0x448 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26
> 0x1A4 0x394 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26
> 0x1A4 0x394 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK
> 	0x1A4 0x394 0x42C 0x6 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23
> 0x1A8 0x398 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3
> 0x1A8 0x398 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01
> 0x1A8 0x398 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER
> 0x1A8 0x398 0x440 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27
> 0x1A8 0x398 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27
> 0x1A8 0x398 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3
> 0x1A8 0x398 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD
> 0x1AC 0x39C 0x54C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK
> 0x1AC 0x39C 0x424 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN
> 0x1AC 0x39C 0x444 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28
> 0x1AC 0x39C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28
> 0x1AC 0x39C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
> 0x1AC 0x39C 0x5D4 0x6 0x2 + +#define
> MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B
> 0x1B0 0x3A0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD
> 0x1B0 0x3A0 0x548 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC
> 0x1B0 0x3A0 0x428 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT
> 	0x1B0 0x3A0 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29
> 0x1B0 0x3A0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29
> 0x1B0 0x3A0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP
> 0x1B0 0x3A0 0x5D8 0x6 0x3 + +#define
> MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC
> 0x1B4 0x3A4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A
> 0x1B4 0x3A4 0x49C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC
> 0x1B4 0x3A4 0x420 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02
> 	0x1B4 0x3A4 0x60C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30
> 0x1B4 0x3A4 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30
> 0x1B4 0x3A4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
> 0x1B4 0x3A4 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO
> 0x1B8 0x3A8 0x430 0x0 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A
> 0x1B8 0x3A8 0x4A0 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK
> 0x1B8 0x3A8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03
> 	0x1B8 0x3A8 0x610 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31
> 0x1B8 0x3A8 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31
> 0x1B8 0x3A8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B
> 0x1B8 0x3A8 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD			0x1BC
> 0x3AC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A
> 0x1BC 0x3AC 0x458 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL			0x1BC
> 0x3AC 0x4DC 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04
> 0x1BC 0x3AC 0x614 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK			0x1BC
> 0x3AC 0x4F0 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12			0x1BC
> 0x3AC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B
> 0x1BC 0x3AC 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK			0x1C0
> 0x3B0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B
> 0x1C0 0x3B0 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA			0x1C0
> 0x3B0 0x4E0 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05
> 0x1C0 0x3B0 0x618 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0
> 0x1C0 0x3B0 0x4EC 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13			0x1C0
> 0x3B0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B
> 0x1C0 0x3B0 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
> 0x1C4 0x3B4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A
> 0x1C4 0x3B4 0x45C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B
> 0x1C4 0x3B4 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06
> 0x1C4 0x3B4 0x61C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO			0x1C4
> 0x3B4 0x4F8 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14			0x1C4
> 0x3B4 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
> 0x1C8 0x3B8 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B
> 0x1C8 0x3B8 0x46C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B
> 0x1C8 0x3B8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07
> 0x1C8 0x3B8 0x620 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI			0x1C8
> 0x3B8 0x4F4 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15			0x1C8
> 0x3B8 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
> 0x1CC 0x3BC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A
> 0x1CC 0x3BC 0x460 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD
> 0x1CC 0x3BC 0x564 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08
> 0x1CC 0x3BC 0x624 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B
> 0x1CC 0x3BC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16			0x1CC
> 0x3BC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1
> 	0x1CC 0x3BC 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
> 0x1D0 0x3C0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B
> 0x1D0 0x3C0 0x470 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD
> 0x1D0 0x3C0 0x560 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09
> 0x1D0 0x3C0 0x628 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS
> 0x1D0 0x3C0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17			0x1D0
> 0x3C0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2
> 	0x1D0 0x3C0 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3
> 0x1D4 0x3C4 0x5F4 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3
> 0x1D4 0x3C4 0x4C4 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A
> 0x1D4 0x3C4 0x454 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03
> 0x1D4 0x3C4 0x598 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD
> 0x1D4 0x3C4 0x544 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00			0x1D4
> 0x3C4 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2
> 0x1D8 0x3C8 0x5F0 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2
> 0x1D8 0x3C8 0x4C0 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B
> 0x1D8 0x3C8 0x464 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02
> 0x1D8 0x3C8 0x59C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD
> 0x1D8 0x3C8 0x540 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01			0x1D8
> 0x3C8 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1
> 0x1DC 0x3CC 0x5EC 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1
> 0x1DC 0x3CC 0x4BC 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A
> 0x1DC 0x3CC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01
> 0x1DC 0x3CC 0x5A0 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX
> 0x1DC 0x3CC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02			0x1DC
> 0x3CC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT
> 0x1DC 0x3CC 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0
> 0x1E0 0x3D0 0x5E8 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0
> 0x1E0 0x3D0 0x4B8 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B
> 0x1E0 0x3D0 0x484 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK
> 	0x1E0 0x3D0 0x58C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX
> 0x1E0 0x3D0 0x44C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03			0x1E0
> 0x3D0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY
> 0x1E0 0x3D0 0x3FC 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK			0x1E4
> 0x3D4 0x5DC 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK
> 0x1E4 0x3D4 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL			0x1E4
> 0x3D4 0x4CC 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC
> 0x1E4 0x3D4 0x5A4 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B
> 0x1E4 0x3D4 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04			0x1E4
> 0x3D4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP
> 0x1E4 0x3D4 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD			0x1E8
> 0x3D8 0x5E4 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS
> 0x1E8 0x3D8 0x4A4 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA			0x1E8
> 0x3D8 0x4D0 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK
> 0x1E8 0x3D8 0x590 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B
> 0x1E8 0x3D8 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05			0x1E8
> 0x3D8 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B
> 0x1EC 0x3DC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B
> 0x1EC 0x3DC 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B
> 0x1EC 0x3DC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00
> 0x1EC 0x3DC 0x594 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0
> 0x1EC 0x3DC 0x4FC 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06			0x1EC
> 0x3DC 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1
> 	0x1F0 0x3E0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK
> 0x1F0 0x3E0 0x4C8 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B
> 0x1F0 0x3E0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00
> 0x1F0 0x3E0 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK			0x1F0
> 0x3E0 0x500 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07			0x1F0
> 0x3E0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B
> 0x1F0 0x3E0 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4
> 0x1F4 0x3E4 0x5F8 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0
> 0x1F4 0x3E4 0x4A8 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD
> 0x1F4 0x3E4 0x55C 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK
> 0x1F4 0x3E4 0x5A8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO			0x1F4
> 0x3E4 0x508 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08			0x1F4
> 0x3E4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2
> 	0x1F4 0x3E4 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5
> 0x1F8 0x3E8 0x5FC 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1
> 0x1F8 0x3E8 0x4AC 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD
> 0x1F8 0x3E8 0x558 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC
> 0x1F8 0x3E8 0x5AC 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI			0x1F8
> 0x3E8 0x504 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09			0x1F8
> 0x3E8 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6
> 0x1FC 0x3EC 0x600 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2
> 0x1FC 0x3EC 0x4B0 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD
> 0x1FC 0x3EC 0x52C 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA			0x1FC
> 0x3EC 0x4D8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2
> 0x1FC 0x3EC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10			0x1FC
> 0x3EC 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7
> 0x200 0x3F0 0x604 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3
> 0x200 0x3F0 0x4B4 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD
> 0x200 0x3F0 0x530 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL			0x200
> 0x3F0 0x4D4 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3
> 0x200 0x3F0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11			0x200
> 0x3F0 0x000 0x5 0x0 + +#endif /*
> _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 15/21] serial_lpuart: add clock enable if CONFIG_CLK is defined
  2020-01-10 14:47 ` [PATCH v2 15/21] serial_lpuart: add clock enable if CONFIG_CLK is defined Giulio Benetti
  2020-01-15 12:47   ` sbabic at denx.de
@ 2020-01-28  8:36   ` Lukasz Majewski
  2020-01-28 18:49     ` Giulio Benetti
  1 sibling, 1 reply; 54+ messages in thread
From: Lukasz Majewski @ 2020-01-28  8:36 UTC (permalink / raw)
  To: u-boot

Hi Giulio,

> This driver assumes that lpuart clock is already enabled before
> probing but using DM only lpuart won't be automatically enabled so add
> clk_enable() when probing if CONFIG_CLK is defined. If clock is not
> found, because DM is not used, let's emit a warning and proceed,
> because serial clock could also be already enabled by non DM code. If
> clock is found but cna't be enabled then return with error.
		     ^^^^ - can't

> 
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> V1->V2:
> * moved error as warning if clk not found
> ---
>  drivers/serial/serial_lpuart.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/serial/serial_lpuart.c
> b/drivers/serial/serial_lpuart.c index 4b0a964d1b..b2ec56172e 100644
> --- a/drivers/serial/serial_lpuart.c
> +++ b/drivers/serial/serial_lpuart.c
> @@ -483,6 +483,22 @@ static int lpuart_serial_pending(struct udevice
> *dev, bool input) 
>  static int lpuart_serial_probe(struct udevice *dev)
>  {
> +#if CONFIG_IS_ENABLED(CLK)
> +	struct clk per_clk;
> +	int ret;
> +
> +	ret = clk_get_by_name(dev, "per", &per_clk);
> +	if (!ret) {
> +		ret = clk_enable(&per_clk);
> +		if (ret) {
> +			dev_err(dev, "Failed to get per clk: %d\n",
> ret);
> +			return ret;
> +		}
> +	} else {
> +		dev_warn(dev, "Failed to get per clk: %d\n",  ret);
		^^^^^^ - please change to debug() as some devices may
		enable CONFIG_CLK, but did not yet support (have
		implemented) this clock in CCF.

> +	}
> +#endif
> +
>  	if (is_lpuart32(dev))
>  		return _lpuart32_serial_init(dev);
>  	else




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 01/21] spl: fix entry_point equal to load_addr
  2020-01-28  8:09   ` Lukasz Majewski
@ 2020-01-28 16:37     ` Giulio Benetti
  2020-01-29  8:33       ` Lukasz Majewski
  0 siblings, 1 reply; 54+ messages in thread
From: Giulio Benetti @ 2020-01-28 16:37 UTC (permalink / raw)
  To: u-boot

Hi Lukasz,

all patch series has already been applied, anyway I answer to your 
suggestions since something was missing and I'm going to create a patch 
for that.

So...

On 1/28/20 9:09 AM, Lukasz Majewski wrote:
> Hi Giulio,
> 
>> At the moment entry_point is set to image_get_load(header) that sets
>> it to "load address" instead of "entry point", assuming entry_point is
>> equal to load_addr, but it's not true. Then load_addr is set to
>> "entry_point - header_size", but this is wrong too since load_addr is
>> not an entry point.
>>
>> So use image_get_ep() for entry_point assignment and image_get_load()
>> for load_addr assignment.
>>
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>>   common/spl/spl.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/common/spl/spl.c b/common/spl/spl.c
>> index c1fce62b91..19085ad270 100644
>> --- a/common/spl/spl.c
>> +++ b/common/spl/spl.c
>> @@ -284,9 +284,9 @@ int spl_parse_image_header(struct spl_image_info
>> *spl_image, spl_image->entry_point = image_get_ep(header);
>>   			spl_image->size =
>> image_get_data_size(header); } else {
>> -			spl_image->entry_point =
>> image_get_load(header);
>> +			spl_image->entry_point =
>> image_get_ep(header); /* Load including the header */
>> -			spl_image->load_addr =
>> spl_image->entry_point -
>> +			spl_image->load_addr =
>> image_get_load(header) - header_size;
>>   			spl_image->size =
>> image_get_data_size(header) + header_size;
> 
> I'm concerned, that this change will silently break several boards -
> the problem is with assumption that entry point is equal to load_addr.
> 
> It would be best to pull this change ASAP, so we would have a chance to
> fix this by next release.

It's been committed after Patrice fixed a lot of boards:
https://gitlab.denx.de/u-boot/u-boot/commit/38a6cce65737096b836d43a22f09b7a54c9d020c
and
https://gitlab.denx.de/u-boot/u-boot/commit/74bb4570a952b06fecfafc5b961a5cb5147ec544

Indeed at the first moment it's been committed by Tom Rini and started 
to cause boot failure as you were worried for, then it's been reverted, 
then it's been re-applied after applying Patrice series.

Best regards
-- 
Giulio Benetti
Benetti Engineering sas

> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 02/21] armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibility
  2020-01-28  8:10   ` Lukasz Majewski
@ 2020-01-28 16:50     ` Giulio Benetti
  2020-01-29  8:36       ` Lukasz Majewski
  0 siblings, 1 reply; 54+ messages in thread
From: Giulio Benetti @ 2020-01-28 16:50 UTC (permalink / raw)
  To: u-boot

On 1/28/20 9:10 AM, Lukasz Majewski wrote:
> Hi Giulio,
> 
>> Since some driver
> 
> I would prefer more verbose commit message. Please share which driver
> requires this change.

Yes, you were right, this is a quite dumb commit log.

Now commit log can't be changed, anyway this is the list of drivers that 
use it:
drivers/video/mvebu_lcd.c
drivers/video/mxsfb.c (that I'm going to use soon)
drivers/video/bcm2835.c
drivers/video/fsl_dcu_fb.c
drivers/video/tegra.c
drivers/video/imx/mxc_ipuv3_fb.c

drivers/net/zynq_gem.c
drivers/net/mvneta.c
drivers/net/mvpp2.c

And this function prototype is provided by arch/arm/include/asm/system.h

Everything came out when I've tried to build mxsfb.c.

But after this e-mail I've dug deeper and see that sometimes 
mmu_set_region_dcache_behaviour() call is guarded by 
CONFIG_IS_ENABLED(SYS_DCACHE_OFF) and sometimes i.e. 
arch/arm/cpu/armv8/cache_v8.c that function is defined both implemented 
and empty according to CONFIG_IS_ENABLED(SYS_DCACHE_OFF). So one chance 
is to put a check to guard against CONFIG_IS_ENABLED(SYS_DCACHE_OFF) on 
every call(the files listed above), otherwise, where is guarded we 
should remove the guard and adding missing 
mmu_set_region_dcache_behaviour() empty implementation. ~5 files to 
touch, but if you say it's worth, I can do patches for that, and I don't 
see any drawbacks expect having a standard way on dealing with the cache 
function.

What about that?

Kind regards
-- 
Giulio Benetti
Benetti Engineering sas

>> requires this function add it as an empty stub
>> when DCACHE is OFF.
>>
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>>   arch/arm/cpu/armv7m/cache.c | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
>> index f4ba3ad50e..7353698557 100644
>> --- a/arch/arm/cpu/armv7m/cache.c
>> +++ b/arch/arm/cpu/armv7m/cache.c
>> @@ -291,6 +291,12 @@ void flush_dcache_all(void)
>>   void invalidate_dcache_all(void)
>>   {
>>   }
>> +
>> +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
>> +				     enum dcache_option option)
>> +{
>> +}
>> +
>>   #endif
>>   
>>   #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 05/21] clk: imx: pllv3: add enable() support
  2020-01-28  8:14   ` Lukasz Majewski
@ 2020-01-28 18:46     ` Giulio Benetti
  0 siblings, 0 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-28 18:46 UTC (permalink / raw)
  To: u-boot

On 1/28/20 9:14 AM, Lukasz Majewski wrote:
> Hi Giulio,
> 
>> Before set_rate() pllv3 needs enable() to power the pll up.
>> Add enable() taking into account different power_bit and
>> different powerup_set, because some pll needs its power_bit to be
>> set or reset to be powered on.
> 
> I do guess that this code is similar to what we do have in the Linux
> kernel (and which I've probably omitted as it was not needed in the
> i.MX6Q use case)?

Exactly, in i.MXRT case need a different enabling sequence and this can 
be useful for other i.MX families.

Best regards
-- 
Giulio Benetti
Benetti Engineering sas

>>
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>>   drivers/clk/imx/clk-pllv3.c | 24 ++++++++++++++++++++++++
>>   1 file changed, 24 insertions(+)
>>
>> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
>> index 02c75c37ea..d8cbe3dd4e 100644
>> --- a/drivers/clk/imx/clk-pllv3.c
>> +++ b/drivers/clk/imx/clk-pllv3.c
>> @@ -16,9 +16,13 @@
>>   #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC	"imx_clk_pllv3_generic"
>>   #define UBOOT_DM_CLK_IMX_PLLV3_USB	"imx_clk_pllv3_usb"
>>   
>> +#define BM_PLL_POWER		(0x1 << 12)
>> +
>>   struct clk_pllv3 {
>>   	struct clk	clk;
>>   	void __iomem	*base;
>> +	u32		power_bit;
>> +	bool		powerup_set;
>>   	u32		div_mask;
>>   	u32		div_shift;
>>   };
>> @@ -35,8 +39,24 @@ static ulong clk_pllv3_generic_get_rate(struct clk
>> *clk) return (div == 1) ? parent_rate * 22 : parent_rate * 20;
>>   }
>>   
>> +static int clk_pllv3_generic_enable(struct clk *clk)
>> +{
>> +	struct clk_pllv3 *pll = to_clk_pllv3(clk);
>> +	u32 val;
>> +
>> +	val = readl(pll->base);
>> +	if (pll->powerup_set)
>> +		val |= pll->power_bit;
>> +	else
>> +		val &= ~pll->power_bit;
>> +	writel(val, pll->base);
>> +
>> +	return 0;
>> +}
>> +
>>   static const struct clk_ops clk_pllv3_generic_ops = {
>>   	.get_rate	= clk_pllv3_generic_get_rate,
>> +	.enable		= clk_pllv3_generic_enable,
>>   };
>>   
>>   struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
>> @@ -52,14 +72,18 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type
>> type, const char *name, if (!pll)
>>   		return ERR_PTR(-ENOMEM);
>>   
>> +	pll->power_bit = BM_PLL_POWER;
>> +
>>   	switch (type) {
>>   	case IMX_PLLV3_GENERIC:
>>   		drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
>>   		pll->div_shift = 0;
>> +		pll->powerup_set = false;
>>   		break;
>>   	case IMX_PLLV3_USB:
>>   		drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
>>   		pll->div_shift = 1;
>> +		pll->powerup_set = true;
>>   		break;
>>   	default:
>>   		kfree(pll);
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 14/21] ARM: dts: imxrt1050: add dtsi file
  2020-01-28  8:31   ` Lukasz Majewski
@ 2020-01-28 18:48     ` Giulio Benetti
  0 siblings, 0 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-28 18:48 UTC (permalink / raw)
  To: u-boot

On 1/28/20 9:31 AM, Lukasz Majewski wrote:
> Hi Giulio,
> 
>> Add dtsi file for i.MXRT1050.
>>
> 
> Please add information from where this code was ported (as I've pointed
> out in other mails).

This is not ported, this is the original one. :-)

> Also a tip:
> 
> To avoid extra dtsi maintenance burden, there are u-boot*.dtsi files
> (in e.g. arch/arm/dts/) which add extra properties (U-boot specific).
> 
> In that way "original" dtsi (from e.g. Linux) are kept separated from
> U-Boot adjustments).

Yes, next patch has -uboot.dtsi that includes this.

Best regards
-- 
Giulio Benetti
Benetti Engineering sas

> 
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>>   arch/arm/dts/imxrt1050.dtsi                  | 146 +++
>>   include/dt-bindings/pinctrl/pins-imxrt1050.h | 993
>> +++++++++++++++++++ 2 files changed, 1139 insertions(+)
>>   create mode 100644 arch/arm/dts/imxrt1050.dtsi
>>   create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h
>>
>> diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
>> new file mode 100644
>> index 0000000000..b1d98e6feb
>> --- /dev/null
>> +++ b/arch/arm/dts/imxrt1050.dtsi
>> @@ -0,0 +1,146 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * Copyright (C) 2019
>> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>> + */
>> +
>> +#include "skeleton.dtsi"
>> +#include "armv7-m.dtsi"
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/imxrt1050-clock.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/memory/imxrt-sdram.h>
>> +
>> +/ {
>> +	aliases {
>> +		gpio0 = &gpio1;
>> +		gpio1 = &gpio2;
>> +		gpio2 = &gpio3;
>> +		gpio3 = &gpio4;
>> +		gpio4 = &gpio5;
>> +		mmc0 = &usdhc1;
>> +		serial0 = &lpuart1;
>> +	};
>> +
>> +	clocks {
>> +		u-boot,dm-spl;
>> +
>> +		osc {
>> +			u-boot,dm-spl;
>> +			compatible = "fsl,imx-osc", "fixed-clock";
>> +			#clock-cells = <0>;
>> +			clock-frequency = <24000000>;
>> +		};
>> +	};
>> +
>> +	soc {
>> +		u-boot,dm-spl;
>> +
>> +		semc: semc at 402f0000 {
>> +			u-boot,dm-spl;
>> +			compatible = "fsl,imxrt-semc";
>> +			reg = <0x402f0000 0x4000>;
>> +			clocks = <&clks IMXRT1050_CLK_SEMC>;
>> +			pinctrl-0 = <&pinctrl_semc>;
>> +			pinctrl-names = "default";
>> +			status = "okay";
>> +		};
>> +
>> +		lpuart1: serial at 40184000 {
>> +			compatible = "fsl,imxrt-lpuart";
>> +			reg = <0x40184000 0x4000>;
>> +			interrupts = <GIC_SPI 20
>> IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&clks IMXRT1050_CLK_LPUART1>;
>> +			clock-names = "per";
>> +			status = "disabled";
>> +		};
>> +
>> +		iomuxc: iomuxc at 401f8000 {
>> +			compatible = "fsl,imxrt-iomuxc";
>> +			reg = <0x401f8000 0x4000>;
>> +			fsl,mux_mask = <0x7>;
>> +		};
>> +
>> +		clks: ccm at 400fc000 {
>> +			u-boot,dm-spl;
>> +			compatible = "fsl,imxrt1050-ccm";
>> +			reg = <0x400fc000 0x4000>;
>> +			interrupts = <GIC_SPI 95
>> IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 96
>> IRQ_TYPE_LEVEL_HIGH>;
>> +			#clock-cells = <1>;
>> +		};
>> +
>> +		usdhc1: usdhc at 402c0000 {
>> +			u-boot,dm-spl;
>> +			compatible = "fsl,imxrt-usdhc";
>> +			reg = <0x402c0000 0x10000>;
>> +			interrupts = <GIC_SPI 110
>> IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&clks IMXRT1050_CLK_USDHC1>;
>> +			clock-names = "per";
>> +			bus-width = <4>;
>> +			fsl,tuning-start-tap = <20>;
>> +			fsl,tuning-step= <2>;
>> +			status = "disabled";
>> +		};
>> +
>> +		gpio1: gpio at 401b8000 {
>> +			u-boot,dm-spl;
>> +			compatible = "fsl,imxrt-gpio",
>> "fsl,imx35-gpio";
>> +			reg = <0x401b8000 0x4000>;
>> +			interrupts = <GIC_SPI 80
>> IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 81
>> IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +		};
>> +
>> +		gpio2: gpio at 401bc000 {
>> +			u-boot,dm-spl;
>> +			compatible = "fsl,imxrt-gpio",
>> "fsl,imx35-gpio";
>> +			reg = <0x401bc000 0x4000>;
>> +			interrupts = <GIC_SPI 82
>> IRQ_TYPE_LEVEL_HIGH>,
>> +				<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +		};
>> +
>> +		gpio3: gpio at 401c0000 {
>> +			u-boot,dm-spl;
>> +			compatible = "fsl,imxrt-gpio",
>> "fsl,imx35-gpio";
>> +			reg = <0x401c0000 0x4000>;
>> +			interrupts = <GIC_SPI 84
>> IRQ_TYPE_LEVEL_HIGH>,
>> +				<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +		};
>> +
>> +		gpio4: gpio at 401c4000 {
>> +			u-boot,dm-spl;
>> +			compatible = "fsl,imxrt-gpio",
>> "fsl,imx35-gpio";
>> +			reg = <0x401c4000 0x4000>;
>> +			interrupts = <GIC_SPI 86
>> IRQ_TYPE_LEVEL_HIGH>,
>> +					<GIC_SPI 87
>> IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +		};
>> +
>> +		gpio5: gpio at 400c0000 {
>> +			u-boot,dm-spl;
>> +			compatible = "fsl,imxrt-gpio",
>> "fsl,imx35-gpio";
>> +			reg = <0x400c0000 0x4000>;
>> +			interrupts = <GIC_SPI 88
>> IRQ_TYPE_LEVEL_HIGH>,
>> +				<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +		};
>> +	};
>> +};
>> diff --git a/include/dt-bindings/pinctrl/pins-imxrt1050.h
>> b/include/dt-bindings/pinctrl/pins-imxrt1050.h new file mode 100644
>> index 0000000000..a29031ab3d
>> --- /dev/null
>> +++ b/include/dt-bindings/pinctrl/pins-imxrt1050.h
>> @@ -0,0 +1,993 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2019
>> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
>> +#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
>> +
>> +#define IMX_PAD_SION	0x40000000
>> +
>> +/*
>> + * The pin function ID is a tuple of
>> + * <mux_reg conf_reg input_reg mux_mode input_val>
>> + */
>> +
>> +#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
>> 	0x014 0x204 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A
>> 0x014 0x204 0x494 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK
>> 0x014 0x204 0x500 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2
>> 	0x014 0x204 0x60C 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00
>> 	0x014 0x204 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00
>> 0x014 0x204 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
>> 0x018 0x208 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B
>> 0x018 0x208 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0
>> 	0x018 0x208 0x4FC 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3
>> 	0x018 0x208 0x610 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01
>> 	0x018 0x208 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01
>> 0x018 0x208 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
>> 0x01C 0x20C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A
>> 0x01C 0x20C 0x498 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO
>> 0x01C 0x20C 0x508 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4
>> 	0x01C 0x20C 0x614 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02
>> 	0x01C 0x20C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02
>> 0x01C 0x20C 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
>> 0x020 0x210 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B
>> 0x020 0x210 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI
>> 0x020 0x210 0x504 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5
>> 	0x020 0x210 0x618 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03
>> 	0x020 0x210 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03
>> 0x020 0x210 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
>> 0x024 0x214 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A
>> 0x024 0x214 0x49C 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA			0x024
>> 0x214 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6
>> 	0x024 0x214 0x61C 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04
>> 	0x024 0x214 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04
>> 0x024 0x214 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
>> 0x028 0x218 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B
>> 0x028 0x218 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC			0x028
>> 0x218 0x5C4 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7
>> 	0x028 0x218 0x620 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05
>> 	0x028 0x218 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05
>> 0x028 0x218 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
>> 0x02C 0x21C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A
>> 0x02C 0x21C 0x478 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK			0x02C
>> 0x21C 0x5C0 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8
>> 	0x02C 0x21C 0x624 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06
>> 	0x02C 0x21C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06
>> 0x02C 0x21C 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
>> 0x030 0x220 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B
>> 0x030 0x220 0x488 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK
>> 0x030 0x220 0x5B0 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9
>> 	0x030 0x220 0x628 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07
>> 	0x030 0x220 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07
>> 0x030 0x220 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
>> 0x034 0x224 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A
>> 0x034 0x224 0x47C 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA			0x034
>> 0x224 0x5B8 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17			0x034
>> 0x224 0x62C 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08
>> 	0x034 0x224 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08
>> 0x034 0x224 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
>> 	0x038 0x228 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B
>> 0x038 0x228 0x48C 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC			0x038
>> 0x228 0x5BC 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX
>> 	0x038 0x228 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09
>> 	0x038 0x228 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09
>> 0x038 0x228 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
>> 	0x03C 0x22C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A
>> 0x03C 0x22C 0x480 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK			0x03C
>> 0x22C 0x5B4 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX
>> 	0x03C 0x22C 0x450 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10
>> 	0x03C 0x22C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10
>> 0x03C 0x22C 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
>> 	0x040 0x230 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B
>> 0x040 0x230 0x490 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA
>> 0x040 0x230 0x4E8 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B
>> 0x040 0x230 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11
>> 	0x040 0x230 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11
>> 0x040 0x230 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
>> 	0x044 0x234 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24			0x044
>> 0x234 0x640 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL
>> 0x044 0x234 0x4E4 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP
>> 0x044 0x234 0x5D8 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A
>> 0x044 0x234 0x454 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12
>> 0x044 0x234 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
>> 	0x048 0x238 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25			0x048
>> 0x238 0x650 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD
>> 	0x048 0x238 0x53C 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT
>> 0x048 0x238 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B
>> 0x048 0x238 0x464 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13
>> 0x048 0x238 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
>> 	0x04C 0x23C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19			0x04C
>> 0x23C 0x654 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD
>> 	0x04C 0x23C 0x538 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT
>> 0x04C 0x23C 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1
>> 	0x04C 0x23C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14
>> 0x04C 0x23C 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
>> 	0x050 0x240 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20			0x050
>> 0x240 0x634 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B
>> 0x050 0x240 0x534 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT
>> 0x050 0x240 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0
>> 	0x050 0x240 0x57C 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15
>> 0x050 0x240 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
>> 	0x054 0x244 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21			0x054
>> 0x244 0x658 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B
>> 0x054 0x244 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN
>> 0x054 0x244 0x5C8 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1
>> 	0x054 0x244 0x580 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16
>> 0x054 0x244 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
>> 	0x058 0x248 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A
>> 0x058 0x248 0x4A0 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B
>> 0x058 0x248 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX
>> 	0x058 0x248 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2
>> 	0x058 0x248 0x584 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17
>> 0x058 0x248 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
>> 	0x05C 0x24C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B
>> 0x05C 0x24C 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B
>> 0x05C 0x24C 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX
>> 	0x05C 0x24C 0x44C 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3
>> 	0x05C 0x24C 0x588 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18
>> 0x05C 0x24C 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL
>> 0x05C 0x24C 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
>> 	0x060 0x250 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A
>> 0x060 0x250 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD
>> 	0x060 0x250 0x544 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01
>> 0x060 0x250 0x438 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0
>> 	0x060 0x250 0x56C 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19
>> 0x060 0x250 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5
>> 0x060 0x250 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
>> 	0x064 0x254 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B
>> 0x064 0x254 0x484 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD
>> 	0x064 0x254 0x540 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00
>> 0x064 0x254 0x434 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0
>> 	0x064 0x254 0x570 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20
>> 0x064 0x254 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
>> 0x068 0x258 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A
>> 0x068 0x258 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA
>> 0x068 0x258 0x4E0 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01
>> 0x068 0x258 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2
>> 	0x068 0x258 0x574 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21
>> 0x068 0x258 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
>> 0x06C 0x25C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B
>> 0x06C 0x25C 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL
>> 0x06C 0x25C 0x4DC 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00
>> 0x06C 0x25C 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3
>> 	0x06C 0x25C 0x578 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22
>> 0x06C 0x25C 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
>> 	0x070 0x260 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A
>> 0x070 0x260 0x458 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD
>> 	0x070 0x260 0x54C 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN
>> 0x070 0x260 0x43C 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2
>> 0x070 0x260 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23
>> 0x070 0x260 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
>> 0x074 0x264 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B
>> 0x074 0x264 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD
>> 	0x074 0x264 0x548 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN
>> 0x074 0x264 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1
>> 0x074 0x264 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24
>> 0x074 0x264 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
>> 0x078 0x268 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A
>> 0x078 0x268 0x45C 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD
>> 	0x078 0x268 0x554 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK
>> 	0x078 0x268 0x448 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK			0x078
>> 0x268 0x42C 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25
>> 0x078 0x268 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
>> 0x07C 0x26C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B
>> 0x07C 0x26C 0x46C 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD
>> 	0x07C 0x26C 0x550 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER
>> 0x07C 0x26C 0x440 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12
>> 	0x07C 0x26C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26
>> 0x07C 0x26C 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
>> 0x080 0x270 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A
>> 0x080 0x270 0x460 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B
>> 0x080 0x270 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK
>> 0x080 0x270 0x4F0 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13
>> 	0x080 0x270 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27
>> 0x080 0x270 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
>> 0x084 0x274 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B
>> 0x084 0x274 0x470 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B
>> 0x084 0x274 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO
>> 0x084 0x274 0x4F8 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14
>> 	0x084 0x274 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28
>> 0x084 0x274 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
>> 0x088 0x278 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A
>> 0x088 0x278 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B
>> 0x088 0x278 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI
>> 0x088 0x278 0x4F4 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15
>> 	0x088 0x278 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29
>> 0x088 0x278 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
>> 0x08C 0x27C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B
>> 0x08C 0x27C 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B
>> 0x08C 0x27C 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0
>> 	0x08C 0x27C 0x4EC 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23
>> 0x08C 0x27C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30
>> 0x08C 0x27C 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
>> 0x090 0x280 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A
>> 0x090 0x280 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD
>> 	0x090 0x280 0x55C 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1
>> 	0x090 0x280 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22
>> 0x090 0x280 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31
>> 0x090 0x280 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
>> 0x094 0x284 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B
>> 0x094 0x284 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD
>> 	0x094 0x284 0x558 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY
>> 0x094 0x284 0x3FC 0x3 0x4 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21
>> 0x094 0x284 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18
>> 0x094 0x284 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
>> 0x098 0x288 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A
>> 0x098 0x288 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B
>> 0x098 0x288 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA			0x098
>> 0x288 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20
>> 0x098 0x288 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19
>> 0x098 0x288 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
>> 0x09C 0x28C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B
>> 0x09C 0x28C 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT
>> 0x09C 0x28C 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC			0x09C
>> 0x28C 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19
>> 0x09C 0x28C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20
>> 0x09C 0x28C 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
>> 0x0A0 0x290 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18			0x0A0
>> 0x290 0x630 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1
>> 0x0A0 0x290 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK			0x0A0
>> 0x290 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18
>> 0x0A0 0x290 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21
>> 0x0A0 0x290 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B
>> 	0x0A0 0x290 0x5D4 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
>> 0x0A4 0x294 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22			0x0A4
>> 0x294 0x638 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2
>> 0x0A4 0x294 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA			0x0A4
>> 0x294 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17
>> 0x0A4 0x294 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22
>> 0x0A4 0x294 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP
>> 0x0A4 0x294 0x5D8 0x6 0x1 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
>> 0x0A8 0x298 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23			0x0A8
>> 0x298 0x63C 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3
>> 0x0A8 0x298 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK
>> 0x0A8 0x298 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16
>> 0x0A8 0x298 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23
>> 0x0A8 0x298 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP
>> 0x0A8 0x298 0x608 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
>> 0x0AC 0x29C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A
>> 0x0AC 0x29C 0x454 0x1 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD
>> 	0x0AC 0x29C 0x564 0x2 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK			0x0AC
>> 0x29C 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD
>> 0x0AC 0x29C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24
>> 0x0AC 0x29C 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT
>> 0x0AC 0x29C 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
>> 0x0B0 0x2A0 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B
>> 0x0B0 0x2A0 0x464 0x1 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD
>> 	0x0B0 0x2A0 0x560 0x2 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC			0x0B0
>> 0x2A0 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B
>> 0x0B0 0x2A0 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25
>> 0x0B0 0x2A0 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B
>> 	0x0B0 0x2A0 0x5E0 0x6 0x1 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY
>> 0x0B4 0x2A4 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2
>> 0x0B4 0x2A4 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2
>> 	0x0B4 0x2A4 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC
>> 	0x0B4 0x2A4 0x5CC 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC
>> 0x0B4 0x2A4 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26
>> 0x0B4 0x2A4 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B
>> 0x0B4 0x2A4 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0
>> 0x0B8 0x2A8 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1
>> 0x0B8 0x2A8 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3
>> 	0x0B8 0x2A8 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR			0x0B8
>> 0x2A8 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO
>> 0x0B8 0x2A8 0x430 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27
>> 0x0B8 0x2A8 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT
>> 0x0B8 0x2A8 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A
>> 0x0BC 0x2AC 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14
>> 0x0BC 0x2AC 0x644 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K
>> 0x0BC 0x2AC 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID
>> 0x0BC 0x2AC 0x3F8 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS
>> 0x0BC 0x2AC 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00			0x0BC
>> 0x2AC 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B
>> 0x0BC 0x2AC 0x000 0x6 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK			0x0BC
>> 0x2AC 0x510 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B
>> 0x0C0 0x2B0 0x484 0x0 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15
>> 0x0C0 0x2B0 0x648 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M
>> 0x0C0 0x2B0 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID
>> 0x0C0 0x2B0 0x3F4 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS
>> 0x0C0 0x2B0 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01			0x0C0
>> 0x2B0 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B
>> 	0x0C0 0x2B0 0x000 0x6 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO			0x0C0
>> 0x2B0 0x518 0x7 0x1 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX
>> 0x0C4 0x2B4 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16
>> 0x0C4 0x2B4 0x64C 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD
>> 0x0C4 0x2B4 0x554 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR
>> 0x0C4 0x2B4 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X
>> 0x0C4 0x2B4 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02			0x0C4
>> 0x2B4 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ
>> 0x0C4 0x2B4 0x000 0x6 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI			0x0C4
>> 0x2B4 0x514 0x7 0x1 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX
>> 0x0C8 0x2B8 0x450 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17
>> 0x0C8 0x2B8 0x62C 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD
>> 0x0C8 0x2B8 0x550 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC
>> 0x0C8 0x2B8 0x5D0 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X
>> 0x0C8 0x2B8 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03			0x0C8
>> 0x2B8 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M
>> 0x0C8 0x2B8 0x000 0x6 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0
>> 0x0C8 0x2B8 0x50C 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00
>> 0x0CC 0x2BC 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT
>> 	0x0CC 0x2BC 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03
>> 0x0CC 0x2BC 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC
>> 0x0CC 0x2BC 0x5C4 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09			0x0CC
>> 0x2BC 0x41C 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04			0x0CC
>> 0x2BC 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00
>> 0x0CC 0x2BC 0x000 0x6 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1
>> 0x0CC 0x2BC 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01
>> 0x0D0 0x2C0 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT
>> 0x0D0 0x2C0 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02
>> 0x0D0 0x2C0 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK
>> 0x0D0 0x2C0 0x5C0 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08			0x0D0
>> 0x2C0 0x418 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05			0x0D0
>> 0x2C0 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17
>> 0x0D0 0x2C0 0x62C 0x6 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2
>> 0x0D0 0x2C0 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS
>> 0x0D4 0x2C4 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1
>> 0x0D4 0x2C4 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK
>> 0x0D4 0x2C4 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK
>> 0x0D4 0x2C4 0x5B4 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07			0x0D4
>> 0x2C4 0x414 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06			0x0D4
>> 0x2C4 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18
>> 0x0D4 0x2C4 0x630 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3
>> 0x0D4 0x2C4 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK
>> 0x0D8 0x2C8 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2
>> 0x0D8 0x2C8 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER			0x0D8
>> 0x2C8 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC
>> 0x0D8 0x2C8 0x5BC 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06			0x0D8
>> 0x2C8 0x410 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07			0x0D8
>> 0x2C8 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19
>> 0x0D8 0x2C8 0x654 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT
>> 0x0D8 0x2C8 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD
>> 0x0DC 0x2CC 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3
>> 0x0DC 0x2CC 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03
>> 0x0DC 0x2CC 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA
>> 0x0DC 0x2CC 0x5B8 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05			0x0DC
>> 0x2CC 0x40C 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08			0x0DC
>> 0x2CC 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20
>> 0x0DC 0x2CC 0x634 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN
>> 0x0DC 0x2CC 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI
>> 0x0E0 0x2D0 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A
>> 0x0E0 0x2D0 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02
>> 0x0E0 0x2D0 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA
>> 0x0E0 0x2D0 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04			0x0E0
>> 0x2D0 0x408 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09			0x0E0
>> 0x2D0 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21
>> 0x0E0 0x2D0 0x658 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK
>> 0x0E0 0x2D0 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO
>> 0x0E4 0x2D4 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A
>> 0x0E4 0x2D4 0x454 0x1 0x3 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS
>> 0x0E4 0x2D4 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK
>> 	0x0E4 0x2D4 0x5B0 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03			0x0E4
>> 0x2D4 0x404 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10			0x0E4
>> 0x2D4 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22
>> 0x0E4 0x2D4 0x638 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT
>> 0x0E4 0x2D4 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB			0x0E8
>> 0x2D8 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B
>> 0x0E8 0x2D8 0x464 0x1 0x3 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL
>> 0x0E8 0x2D8 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B
>> 0x0E8 0x2D8 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02			0x0E8
>> 0x2D8 0x400 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11			0x0E8
>> 0x2D8 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23
>> 0x0E8 0x2D8 0x63C 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN
>> 0x0E8 0x2D8 0x444 0x7 0x1 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL			0x0EC
>> 0x2DC 0x4E4 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY
>> 0x0EC 0x2DC 0x3FC 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
>> 0x0EC 0x2DC 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B
>> 0x0EC 0x2DC 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X
>> 0x0EC 0x2DC 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12			0x0EC
>> 0x2DC 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT
>> 0x0EC 0x2DC 0x000 0x6 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI
>> 0x0EC 0x2DC 0x568 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA			0x0F0
>> 0x2E0 0x4E8 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK
>> 0x0F0 0x2E0 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
>> 0x0F0 0x2E0 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B
>> 	0x0F0 0x2E0 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X
>> 0x0F0 0x2E0 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13			0x0F0
>> 0x2E0 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN
>> 0x0F0 0x2E0 0x000 0x6 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M
>> 0x0F0 0x2E0 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC
>> 0x0F4 0x2E4 0x5CC 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24
>> 0x0F4 0x2E4 0x640 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B
>> 0x0F4 0x2E4 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT
>> 0x0F4 0x2E4 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC
>> 	0x0F4 0x2E4 0x428 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14			0x0F4
>> 0x2E4 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX
>> 0x0F4 0x2E4 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR
>> 0x0F8 0x2E8 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25
>> 0x0F8 0x2E8 0x650 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B
>> 0x0F8 0x2E8 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN
>> 0x0F8 0x2E8 0x444 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC
>> 	0x0F8 0x2E8 0x420 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15			0x0F8
>> 0x2E8 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX
>> 0x0F8 0x2E8 0x450 0x6 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB
>> 0x0F8 0x2E8 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID
>> 0x0FC 0x2EC 0x3F8 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0
>> 0x0FC 0x2EC 0x57C 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B
>> 0x0FC 0x2EC 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL			0x0FC
>> 0x2EC 0x4CC 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B
>> 0x0FC 0x2EC 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16			0x0FC
>> 0x2EC 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP
>> 	0x0FC 0x2EC 0x5D8 0x6 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07
>> 	0x0FC 0x2EC 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR
>> 0x100 0x2F0 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1
>> 0x100 0x2F0 0x580 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B
>> 0x100 0x2F0 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA			0x100
>> 0x2F0 0x4D0 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY
>> 0x100 0x2F0 0x3FC 0x4 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17			0x100
>> 0x2F0 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT
>> 0x100 0x2F0 0x000 0x6 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07
>> 	0x100 0x2F0 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID
>> 0x104 0x2F4 0x3F4 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2
>> 0x104 0x2F4 0x584 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD
>> 0x104 0x2F4 0x530 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT
>> 	0x104 0x2F4 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT
>> 0x104 0x2F4 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18			0x104
>> 0x2F4 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B
>> 0x104 0x2F4 0x5D4 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06
>> 	0x104 0x2F4 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC
>> 0x108 0x2F8 0x5D0 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3
>> 0x108 0x2F8 0x588 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD
>> 0x108 0x2F8 0x52C 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN
>> 0x108 0x2F8 0x5C8 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN
>> 0x108 0x2F8 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19			0x108
>> 0x2F8 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B
>> 0x108 0x2F8 0x5E0 0x6 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06
>> 	0x108 0x2F8 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3
>> 0x10C 0x2FC 0x4C4 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC
>> 0x10C 0x2FC 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B
>> 0x10C 0x2FC 0x534 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK
>> 0x10C 0x2FC 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK			0x10C
>> 0x2FC 0x424 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20			0x10C
>> 0x2FC 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0
>> 0x10C 0x2FC 0x5E8 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05
>> 	0x10C 0x2FC 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2
>> 0x110 0x300 0x4C0 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO
>> 	0x110 0x300 0x430 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B
>> 0x110 0x300 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT
>> 	0x110 0x300 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK
>> 0x110 0x300 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21			0x110
>> 0x300 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1
>> 0x110 0x300 0x5EC 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05
>> 	0x110 0x300 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1
>> 0x114 0x304 0x4BC 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA			0x114
>> 0x304 0x4E0 0x1 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD
>> 0x114 0x304 0x53C 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK			0x114
>> 0x304 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC
>> 	0x114 0x304 0x428 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22			0x114
>> 0x304 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2
>> 0x114 0x304 0x5F0 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04
>> 	0x114 0x304 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0
>> 0x118 0x308 0x4B8 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL			0x118
>> 0x308 0x4DC 0x1 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD
>> 0x118 0x308 0x538 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK
>> 0x118 0x308 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC
>> 	0x118 0x308 0x420 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23			0x118
>> 0x308 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3
>> 0x118 0x308 0x5F4 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04
>> 	0x118 0x308 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B
>> 0x11C 0x30C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A
>> 0x11C 0x30C 0x494 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX
>> 0x11C 0x30C 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY
>> 0x11C 0x30C 0x3FC 0x3 0x3 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09			0x11C
>> 0x30C 0x41C 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24			0x11C
>> 0x30C 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD			0x11C
>> 0x30C 0x5E4 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03
>> 	0x11C 0x30C 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS
>> 0x120 0x310 0x4A4 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A
>> 0x120 0x310 0x498 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX
>> 0x120 0x310 0x44C 0x2 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK
>> 	0x120 0x310 0x58C 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08			0x120
>> 0x310 0x418 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25			0x120
>> 0x310 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK			0x120
>> 0x310 0x5DC 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03
>> 	0x120 0x310 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3
>> 0x124 0x314 0x4B4 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B
>> 0x124 0x314 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD
>> 0x124 0x314 0x564 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC
>> 0x124 0x314 0x5A4 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07			0x124
>> 0x314 0x414 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26			0x124
>> 0x314 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP
>> 	0x124 0x314 0x608 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02
>> 	0x124 0x314 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2
>> 0x128 0x318 0x4B0 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B
>> 	0x128 0x318 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD
>> 0x128 0x318 0x560 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK
>> 0x128 0x318 0x590 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06			0x128
>> 0x318 0x410 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27			0x128
>> 0x318 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B
>> 0x128 0x318 0x000 0x6 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02
>> 	0x128 0x318 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1
>> 0x12C 0x31C 0x4AC 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT
>> 	0x12C 0x31C 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0
>> 0x12C 0x31C 0x50C 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00
>> 0x12C 0x31C 0x594 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05			0x12C
>> 0x31C 0x40C 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28			0x12C
>> 0x31C 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4
>> 0x12C 0x31C 0x5F8 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01
>> 	0x12C 0x31C 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0
>> 0x130 0x320 0x4A8 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT
>> 	0x130 0x320 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI			0x130
>> 0x320 0x514 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00
>> 0x130 0x320 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04			0x130
>> 0x320 0x408 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29			0x130
>> 0x320 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5
>> 0x130 0x320 0x5FC 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01
>> 	0x130 0x320 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK
>> 0x134 0x324 0x4C8 0x0 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT
>> 	0x134 0x324 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO			0x134
>> 0x324 0x518 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK
>> 0x134 0x324 0x5A8 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03			0x134
>> 0x324 0x404 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30			0x134
>> 0x324 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6
>> 0x134 0x324 0x600 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00
>> 	0x134 0x324 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B
>> 0x138 0x328 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT
>> 	0x138 0x328 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK			0x138
>> 0x328 0x510 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC
>> 0x138 0x328 0x5AC 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02			0x138
>> 0x328 0x400 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31			0x138
>> 0x328 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7
>> 0x138 0x328 0x604 0x6 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00
>> 	0x138 0x328 0x000 0x7 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK
>> 0x13C 0x32C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0
>> 0x13C 0x32C 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT
>> 0x13C 0x32C 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0
>> 0x13C 0x32C 0x51C 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00
>> 0x13C 0x32C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00
>> 0x13C 0x32C 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1
>> 0x13C 0x32C 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE
>> 0x140 0x330 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1
>> 0x140 0x330 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT
>> 0x140 0x330 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI
>> 0x140 0x330 0x524 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01
>> 0x140 0x330 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01
>> 0x140 0x330 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2
>> 0x140 0x330 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC
>> 0x144 0x334 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2
>> 0x144 0x334 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX
>> 0x144 0x334 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO
>> 0x144 0x334 0x528 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02
>> 0x144 0x334 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02
>> 0x144 0x334 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3
>> 0x144 0x334 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC
>> 0x148 0x338 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0
>> 0x148 0x338 0x56C 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX
>> 0x148 0x338 0x44C 0x2 0x3 +#define
>> MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK
>> 0x148 0x338 0x520 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03
>> 0x148 0x338 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03
>> 0x148 0x338 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB
>> 0x148 0x338 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00
>> 0x14C 0x33C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1
>> 0x14C 0x33C 0x570 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL
>> 0x14C 0x33C 0x4D4 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00
>> 0x14C 0x33C 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04
>> 0x14C 0x33C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04
>> 0x14C 0x33C 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00
>> 	0x14C 0x33C 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01
>> 0x150 0x340 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2
>> 0x150 0x340 0x574 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA
>> 0x150 0x340 0x4D8 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01
>> 0x150 0x340 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05
>> 0x150 0x340 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05
>> 0x150 0x340 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01
>> 	0x150 0x340 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02
>> 0x154 0x344 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0
>> 0x154 0x344 0x57C 0x1 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A
>> 0x154 0x344 0x478 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02
>> 0x154 0x344 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06
>> 0x154 0x344 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06
>> 0x154 0x344 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02
>> 	0x154 0x344 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03
>> 0x158 0x348 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1
>> 0x158 0x348 0x580 0x1 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B
>> 0x158 0x348 0x488 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03
>> 0x158 0x348 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07
>> 0x158 0x348 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07
>> 0x158 0x348 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03
>> 	0x158 0x348 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04
>> 0x15C 0x34C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2
>> 0x15C 0x34C 0x584 0x1 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A
>> 0x15C 0x34C 0x47C 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD
>> 0x15C 0x34C 0x53C 0x3 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08
>> 0x15C 0x34C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08
>> 0x15C 0x34C 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04
>> 	0x15C 0x34C 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05
>> 0x160 0x350 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0
>> 0x160 0x350 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B
>> 0x160 0x350 0x48C 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD
>> 0x160 0x350 0x538 0x3 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09
>> 0x160 0x350 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09
>> 0x160 0x350 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05
>> 	0x160 0x350 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06
>> 0x164 0x354 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1
>> 0x164 0x354 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A
>> 0x164 0x354 0x480 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03
>> 0x164 0x354 0x598 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10
>> 0x164 0x354 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10
>> 0x164 0x354 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06
>> 	0x164 0x354 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07
>> 0x168 0x358 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2
>> 0x168 0x358 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B
>> 0x168 0x358 0x490 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02
>> 0x168 0x358 0x59C 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11
>> 0x168 0x358 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11
>> 0x168 0x358 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07
>> 	0x168 0x358 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08
>> 0x16C 0x35C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10
>> 	0x16C 0x35C 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK			0x16C
>> 0x35C 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01
>> 0x16C 0x35C 0x5A0 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12
>> 0x16C 0x35C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12
>> 0x16C 0x35C 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08
>> 	0x16C 0x35C 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09
>> 0x170 0x360 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11
>> 	0x170 0x360 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO			0x170
>> 0x360 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK
>> 0x170 0x360 0x58C 0x3 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13
>> 0x170 0x360 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13
>> 0x170 0x360 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09
>> 	0x170 0x360 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10
>> 0x174 0x364 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12
>> 	0x174 0x364 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV
>> 	0x174 0x364 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC
>> 	0x174 0x364 0x5A4 0x3 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14
>> 0x174 0x364 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14
>> 0x174 0x364 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10
>> 	0x174 0x364 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11
>> 0x178 0x368 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13
>> 	0x178 0x368 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV
>> 	0x178 0x368 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK
>> 	0x178 0x368 0x590 0x3 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15
>> 0x178 0x368 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15
>> 0x178 0x368 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11
>> 	0x178 0x368 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12
>> 0x17C 0x36C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14
>> 	0x17C 0x36C 0x644 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD
>> 0x17C 0x36C 0x544 0x2 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00
>> 0x17C 0x36C 0x594 0x3 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16
>> 0x17C 0x36C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16
>> 0x17C 0x36C 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A
>> 0x17C 0x36C 0x454 0x6 0x4 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13
>> 0x180 0x370 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15
>> 	0x180 0x370 0x648 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD
>> 0x180 0x370 0x540 0x2 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00
>> 0x180 0x370 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17
>> 0x180 0x370 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17
>> 0x180 0x370 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B
>> 0x180 0x370 0x464 0x6 0x4 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14
>> 0x184 0x374 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16
>> 	0x184 0x374 0x64C 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2
>> 0x184 0x374 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK
>> 	0x184 0x374 0x5A8 0x3 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18
>> 0x184 0x374 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18
>> 0x184 0x374 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A
>> 0x184 0x374 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15
>> 0x188 0x378 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17
>> 	0x188 0x378 0x62C 0x1 0x3 +#define
>> MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1
>> 0x188 0x378 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC
>> 	0x188 0x378 0x5AC 0x3 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19
>> 0x188 0x378 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19
>> 0x188 0x378 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B
>> 0x188 0x378 0x484 0x6 0x3 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16
>> 0x18C 0x37C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0
>> 0x18C 0x37C 0x51C 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15
>> 0x18C 0x37C 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00
>> 0x18C 0x37C 0x434 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20
>> 0x18C 0x37C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20
>> 0x18C 0x37C 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17
>> 0x190 0x380 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI
>> 0x190 0x380 0x524 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14
>> 0x190 0x380 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01
>> 0x190 0x380 0x438 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21
>> 0x190 0x380 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21
>> 0x190 0x380 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18
>> 0x194 0x384 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO
>> 0x194 0x384 0x528 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13
>> 0x194 0x384 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN
>> 0x194 0x384 0x43C 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22
>> 0x194 0x384 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22
>> 0x194 0x384 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19
>> 0x198 0x388 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK
>> 0x198 0x388 0x520 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12
>> 0x198 0x388 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00
>> 0x198 0x388 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23
>> 0x198 0x388 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23
>> 0x198 0x388 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20
>> 0x19C 0x38C 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3
>> 0x19C 0x38C 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11
>> 0x19C 0x38C 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01
>> 0x19C 0x38C 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24
>> 0x19C 0x38C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24
>> 0x19C 0x38C 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX
>> 0x19C 0x38C 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21
>> 0x1A0 0x390 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3
>> 0x1A0 0x390 0x578 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10
>> 0x1A0 0x390 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN
>> 0x1A0 0x390 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25
>> 0x1A0 0x390 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25
>> 0x1A0 0x390 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX
>> 0x1A0 0x390 0x450 0x6 0x3 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22
>> 0x1A4 0x394 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3
>> 0x1A4 0x394 0x588 0x1 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00
>> 0x1A4 0x394 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK
>> 0x1A4 0x394 0x448 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26
>> 0x1A4 0x394 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26
>> 0x1A4 0x394 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK
>> 	0x1A4 0x394 0x42C 0x6 0x1 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23
>> 0x1A8 0x398 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3
>> 0x1A8 0x398 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01
>> 0x1A8 0x398 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER
>> 0x1A8 0x398 0x440 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27
>> 0x1A8 0x398 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27
>> 0x1A8 0x398 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3
>> 0x1A8 0x398 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD
>> 0x1AC 0x39C 0x54C 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK
>> 0x1AC 0x39C 0x424 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN
>> 0x1AC 0x39C 0x444 0x3 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28
>> 0x1AC 0x39C 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28
>> 0x1AC 0x39C 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
>> 0x1AC 0x39C 0x5D4 0x6 0x2 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B
>> 0x1B0 0x3A0 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD
>> 0x1B0 0x3A0 0x548 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC
>> 0x1B0 0x3A0 0x428 0x2 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT
>> 	0x1B0 0x3A0 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29
>> 0x1B0 0x3A0 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29
>> 0x1B0 0x3A0 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP
>> 0x1B0 0x3A0 0x5D8 0x6 0x3 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC
>> 0x1B4 0x3A4 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A
>> 0x1B4 0x3A4 0x49C 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC
>> 0x1B4 0x3A4 0x420 0x2 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02
>> 	0x1B4 0x3A4 0x60C 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30
>> 0x1B4 0x3A4 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30
>> 0x1B4 0x3A4 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
>> 0x1B4 0x3A4 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO
>> 0x1B8 0x3A8 0x430 0x0 0x2 +#define
>> MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A
>> 0x1B8 0x3A8 0x4A0 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK
>> 0x1B8 0x3A8 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03
>> 	0x1B8 0x3A8 0x610 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31
>> 0x1B8 0x3A8 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31
>> 0x1B8 0x3A8 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B
>> 0x1B8 0x3A8 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD			0x1BC
>> 0x3AC 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A
>> 0x1BC 0x3AC 0x458 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL			0x1BC
>> 0x3AC 0x4DC 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04
>> 0x1BC 0x3AC 0x614 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK			0x1BC
>> 0x3AC 0x4F0 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12			0x1BC
>> 0x3AC 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B
>> 0x1BC 0x3AC 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK			0x1C0
>> 0x3B0 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B
>> 0x1C0 0x3B0 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA			0x1C0
>> 0x3B0 0x4E0 0x2 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05
>> 0x1C0 0x3B0 0x618 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0
>> 0x1C0 0x3B0 0x4EC 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13			0x1C0
>> 0x3B0 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B
>> 0x1C0 0x3B0 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
>> 0x1C4 0x3B4 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A
>> 0x1C4 0x3B4 0x45C 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B
>> 0x1C4 0x3B4 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06
>> 0x1C4 0x3B4 0x61C 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO			0x1C4
>> 0x3B4 0x4F8 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14			0x1C4
>> 0x3B4 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
>> 0x1C8 0x3B8 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B
>> 0x1C8 0x3B8 0x46C 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B
>> 0x1C8 0x3B8 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07
>> 0x1C8 0x3B8 0x620 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI			0x1C8
>> 0x3B8 0x4F4 0x4 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15			0x1C8
>> 0x3B8 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
>> 0x1CC 0x3BC 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A
>> 0x1CC 0x3BC 0x460 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD
>> 0x1CC 0x3BC 0x564 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08
>> 0x1CC 0x3BC 0x624 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B
>> 0x1CC 0x3BC 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16			0x1CC
>> 0x3BC 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1
>> 	0x1CC 0x3BC 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
>> 0x1D0 0x3C0 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B
>> 0x1D0 0x3C0 0x470 0x1 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD
>> 0x1D0 0x3C0 0x560 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09
>> 0x1D0 0x3C0 0x628 0x3 0x1 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS
>> 0x1D0 0x3C0 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17			0x1D0
>> 0x3C0 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2
>> 	0x1D0 0x3C0 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3
>> 0x1D4 0x3C4 0x5F4 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3
>> 0x1D4 0x3C4 0x4C4 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A
>> 0x1D4 0x3C4 0x454 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03
>> 0x1D4 0x3C4 0x598 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD
>> 0x1D4 0x3C4 0x544 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00			0x1D4
>> 0x3C4 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2
>> 0x1D8 0x3C8 0x5F0 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2
>> 0x1D8 0x3C8 0x4C0 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B
>> 0x1D8 0x3C8 0x464 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02
>> 0x1D8 0x3C8 0x59C 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD
>> 0x1D8 0x3C8 0x540 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01			0x1D8
>> 0x3C8 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1
>> 0x1DC 0x3CC 0x5EC 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1
>> 0x1DC 0x3CC 0x4BC 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A
>> 0x1DC 0x3CC 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01
>> 0x1DC 0x3CC 0x5A0 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX
>> 0x1DC 0x3CC 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02			0x1DC
>> 0x3CC 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT
>> 0x1DC 0x3CC 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0
>> 0x1E0 0x3D0 0x5E8 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0
>> 0x1E0 0x3D0 0x4B8 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B
>> 0x1E0 0x3D0 0x484 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK
>> 	0x1E0 0x3D0 0x58C 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX
>> 0x1E0 0x3D0 0x44C 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03			0x1E0
>> 0x3D0 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY
>> 0x1E0 0x3D0 0x3FC 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK			0x1E4
>> 0x3D4 0x5DC 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK
>> 0x1E4 0x3D4 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL			0x1E4
>> 0x3D4 0x4CC 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC
>> 0x1E4 0x3D4 0x5A4 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B
>> 0x1E4 0x3D4 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04			0x1E4
>> 0x3D4 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP
>> 0x1E4 0x3D4 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD			0x1E8
>> 0x3D8 0x5E4 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS
>> 0x1E8 0x3D8 0x4A4 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA			0x1E8
>> 0x3D8 0x4D0 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK
>> 0x1E8 0x3D8 0x590 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B
>> 0x1E8 0x3D8 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05			0x1E8
>> 0x3D8 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B
>> 0x1EC 0x3DC 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B
>> 0x1EC 0x3DC 0x000 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B
>> 0x1EC 0x3DC 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00
>> 0x1EC 0x3DC 0x594 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0
>> 0x1EC 0x3DC 0x4FC 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06			0x1EC
>> 0x3DC 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1
>> 	0x1F0 0x3E0 0x000 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK
>> 0x1F0 0x3E0 0x4C8 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B
>> 0x1F0 0x3E0 0x000 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00
>> 0x1F0 0x3E0 0x000 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK			0x1F0
>> 0x3E0 0x500 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07			0x1F0
>> 0x3E0 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B
>> 0x1F0 0x3E0 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4
>> 0x1F4 0x3E4 0x5F8 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0
>> 0x1F4 0x3E4 0x4A8 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD
>> 0x1F4 0x3E4 0x55C 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK
>> 0x1F4 0x3E4 0x5A8 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO			0x1F4
>> 0x3E4 0x508 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08			0x1F4
>> 0x3E4 0x000 0x5 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2
>> 	0x1F4 0x3E4 0x000 0x6 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5
>> 0x1F8 0x3E8 0x5FC 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1
>> 0x1F8 0x3E8 0x4AC 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD
>> 0x1F8 0x3E8 0x558 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC
>> 0x1F8 0x3E8 0x5AC 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI			0x1F8
>> 0x3E8 0x504 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09			0x1F8
>> 0x3E8 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6
>> 0x1FC 0x3EC 0x600 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2
>> 0x1FC 0x3EC 0x4B0 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD
>> 0x1FC 0x3EC 0x52C 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA			0x1FC
>> 0x3EC 0x4D8 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2
>> 0x1FC 0x3EC 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10			0x1FC
>> 0x3EC 0x000 0x5 0x0 + +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7
>> 0x200 0x3F0 0x604 0x0 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3
>> 0x200 0x3F0 0x4B4 0x1 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD
>> 0x200 0x3F0 0x530 0x2 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL			0x200
>> 0x3F0 0x4D4 0x3 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3
>> 0x200 0x3F0 0x000 0x4 0x0 +#define
>> MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11			0x200
>> 0x3F0 0x000 0x5 0x0 + +#endif /*
>> _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 15/21] serial_lpuart: add clock enable if CONFIG_CLK is defined
  2020-01-28  8:36   ` Lukasz Majewski
@ 2020-01-28 18:49     ` Giulio Benetti
  2020-01-31 13:39       ` [PATCH] serial_lpuart: make clock failure less verbose Giulio Benetti
  0 siblings, 1 reply; 54+ messages in thread
From: Giulio Benetti @ 2020-01-28 18:49 UTC (permalink / raw)
  To: u-boot

Hi Lukasz,

On 1/28/20 9:36 AM, Lukasz Majewski wrote:
> Hi Giulio,
> 
>> This driver assumes that lpuart clock is already enabled before
>> probing but using DM only lpuart won't be automatically enabled so add
>> clk_enable() when probing if CONFIG_CLK is defined. If clock is not
>> found, because DM is not used, let's emit a warning and proceed,
>> because serial clock could also be already enabled by non DM code. If
>> clock is found but cna't be enabled then return with error.
> 		     ^^^^ - can't

It's too late now, but...

>>
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>> V1->V2:
>> * moved error as warning if clk not found
>> ---
>>   drivers/serial/serial_lpuart.c | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/drivers/serial/serial_lpuart.c
>> b/drivers/serial/serial_lpuart.c index 4b0a964d1b..b2ec56172e 100644
>> --- a/drivers/serial/serial_lpuart.c
>> +++ b/drivers/serial/serial_lpuart.c
>> @@ -483,6 +483,22 @@ static int lpuart_serial_pending(struct udevice
>> *dev, bool input)
>>   static int lpuart_serial_probe(struct udevice *dev)
>>   {
>> +#if CONFIG_IS_ENABLED(CLK)
>> +	struct clk per_clk;
>> +	int ret;
>> +
>> +	ret = clk_get_by_name(dev, "per", &per_clk);
>> +	if (!ret) {
>> +		ret = clk_enable(&per_clk);
>> +		if (ret) {
>> +			dev_err(dev, "Failed to get per clk: %d\n",
>> ret);
>> +			return ret;
>> +		}
>> +	} else {
>> +		dev_warn(dev, "Failed to get per clk: %d\n",  ret);
> 		^^^^^^ - please change to debug() as some devices may
> 		enable CONFIG_CLK, but did not yet support (have
> 		implemented) this clock in CCF.

...not for this, I'm going to send a patch changing this string.

Best regards
-- 
Giulio Benetti
Benetti Engineering sas

>> +	}
>> +#endif
>> +
>>   	if (is_lpuart32(dev))
>>   		return _lpuart32_serial_init(dev);
>>   	else
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 01/21] spl: fix entry_point equal to load_addr
  2020-01-28 16:37     ` Giulio Benetti
@ 2020-01-29  8:33       ` Lukasz Majewski
  0 siblings, 0 replies; 54+ messages in thread
From: Lukasz Majewski @ 2020-01-29  8:33 UTC (permalink / raw)
  To: u-boot

On Tue, 28 Jan 2020 17:37:17 +0100
Giulio Benetti <giulio.benetti@benettiengineering.com> wrote:

> Hi Lukasz,
> 
> all patch series has already been applied, anyway I answer to your 
> suggestions since something was missing and I'm going to create a
> patch for that.
> 
> So...
> 
> On 1/28/20 9:09 AM, Lukasz Majewski wrote:
> > Hi Giulio,
> >   
> >> At the moment entry_point is set to image_get_load(header) that
> >> sets it to "load address" instead of "entry point", assuming
> >> entry_point is equal to load_addr, but it's not true. Then
> >> load_addr is set to "entry_point - header_size", but this is wrong
> >> too since load_addr is not an entry point.
> >>
> >> So use image_get_ep() for entry_point assignment and
> >> image_get_load() for load_addr assignment.
> >>
> >> Signed-off-by: Giulio Benetti
> >> <giulio.benetti@benettiengineering.com> ---
> >>   common/spl/spl.c | 4 ++--
> >>   1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/common/spl/spl.c b/common/spl/spl.c
> >> index c1fce62b91..19085ad270 100644
> >> --- a/common/spl/spl.c
> >> +++ b/common/spl/spl.c
> >> @@ -284,9 +284,9 @@ int spl_parse_image_header(struct
> >> spl_image_info *spl_image, spl_image->entry_point =
> >> image_get_ep(header); spl_image->size =
> >> image_get_data_size(header); } else {
> >> -			spl_image->entry_point =
> >> image_get_load(header);
> >> +			spl_image->entry_point =
> >> image_get_ep(header); /* Load including the header */
> >> -			spl_image->load_addr =
> >> spl_image->entry_point -
> >> +			spl_image->load_addr =
> >> image_get_load(header) - header_size;
> >>   			spl_image->size =
> >> image_get_data_size(header) + header_size;  
> > 
> > I'm concerned, that this change will silently break several boards -
> > the problem is with assumption that entry point is equal to
> > load_addr.
> > 
> > It would be best to pull this change ASAP, so we would have a
> > chance to fix this by next release.  
> 
> It's been committed after Patrice fixed a lot of boards:
> https://gitlab.denx.de/u-boot/u-boot/commit/38a6cce65737096b836d43a22f09b7a54c9d020c
> and
> https://gitlab.denx.de/u-boot/u-boot/commit/74bb4570a952b06fecfafc5b961a5cb5147ec544
> 
> Indeed at the first moment it's been committed by Tom Rini and
> started to cause boot failure as you were worried for, then it's been
> reverted, then it's been re-applied after applying Patrice series.
> 

Ach... Ok. No problem then.

> Best regards




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v2 02/21] armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibility
  2020-01-28 16:50     ` Giulio Benetti
@ 2020-01-29  8:36       ` Lukasz Majewski
  0 siblings, 0 replies; 54+ messages in thread
From: Lukasz Majewski @ 2020-01-29  8:36 UTC (permalink / raw)
  To: u-boot

On Tue, 28 Jan 2020 17:50:03 +0100
Giulio Benetti <giulio.benetti@benettiengineering.com> wrote:

> On 1/28/20 9:10 AM, Lukasz Majewski wrote:
> > Hi Giulio,
> >   
> >> Since some driver  
> > 
> > I would prefer more verbose commit message. Please share which
> > driver requires this change.  
> 
> Yes, you were right, this is a quite dumb commit log.
> 
> Now commit log can't be changed, anyway this is the list of drivers
> that use it:
> drivers/video/mvebu_lcd.c
> drivers/video/mxsfb.c (that I'm going to use soon)
> drivers/video/bcm2835.c
> drivers/video/fsl_dcu_fb.c
> drivers/video/tegra.c
> drivers/video/imx/mxc_ipuv3_fb.c
> 
> drivers/net/zynq_gem.c
> drivers/net/mvneta.c
> drivers/net/mvpp2.c
> 
> And this function prototype is provided by
> arch/arm/include/asm/system.h
> 
> Everything came out when I've tried to build mxsfb.c.
> 
> But after this e-mail I've dug deeper and see that sometimes 
> mmu_set_region_dcache_behaviour() call is guarded by 
> CONFIG_IS_ENABLED(SYS_DCACHE_OFF) and sometimes i.e. 
> arch/arm/cpu/armv8/cache_v8.c that function is defined both
> implemented and empty according to CONFIG_IS_ENABLED(SYS_DCACHE_OFF).
> So one chance is to put a check to guard against
> CONFIG_IS_ENABLED(SYS_DCACHE_OFF) on every call(the files listed
> above), otherwise, where is guarded we should remove the guard and
> adding missing mmu_set_region_dcache_behaviour() empty
> implementation. ~5 files to touch, but if you say it's worth, I can
> do patches for that, and I don't see any drawbacks expect having a
> standard way on dealing with the cache function.
> 
> What about that?

IMHO, it would be best to to this change when you decide to add support
for DCACHE/ICACHE on this SoC.

> 
> Kind regards




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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* [PATCH] serial_lpuart: make clock failure less verbose
  2020-01-28 18:49     ` Giulio Benetti
@ 2020-01-31 13:39       ` Giulio Benetti
  2020-01-31 18:14         ` Simon Glass
  2020-03-10 15:31         ` sbabic at denx.de
  0 siblings, 2 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-31 13:39 UTC (permalink / raw)
  To: u-boot

Some device may enable CONFIG_CLK but not still support this clock in
CC, so better use debug() in place of dev_warn() otherwise a lot of
boards will throw useless dev_warn()s.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
 drivers/serial/serial_lpuart.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index ccb3ce6701..1087dc3b65 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -498,7 +498,7 @@ static int lpuart_serial_probe(struct udevice *dev)
 			return ret;
 		}
 	} else {
-		dev_warn(dev, "Failed to get per clk: %d\n",  ret);
+		debug("%s: Failed to get per clk: %d\n", __func__, ret);
 	}
 #endif
 
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v2 09/21] clk: imx: pllv3: add support for PLLV3_AV type
  2020-01-28  8:20   ` Lukasz Majewski
@ 2020-01-31 13:50     ` Giulio Benetti
  0 siblings, 0 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-01-31 13:50 UTC (permalink / raw)
  To: u-boot

Hi Lukasz,

On 1/28/20 9:20 AM, Lukasz Majewski wrote:
> Hi Giulio,
> 
>> Add support for PLLV3 AV type.
> 
> If this code has been ported from Linux kernel, then provide SHA1,
> branch, and commit message.

Oh sorry,

Code taken from Linux with below commit:
"ARM: imx: add common clock support for pllv3"
(sha1: a3f6b9dbf2a964b85f0523e577807d6f63d6b29d)

Hope this way is ok, I imitated other commit logs in u-boot.

Best regards
-- 
Giulio Benetti
Benetti Engineering sas

> Acked-by: Lukasz Majewski <lukma@denx.de>
> 
>>
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>>   drivers/clk/imx/clk-pllv3.c | 76
>> +++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+)
>>
>> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
>> index d5087a104e..fc16416d5f 100644
>> --- a/drivers/clk/imx/clk-pllv3.c
>> +++ b/drivers/clk/imx/clk-pllv3.c
>> @@ -6,6 +6,7 @@
>>   
>>   #include <common.h>
>>   #include <asm/io.h>
>> +#include <div64.h>
>>   #include <malloc.h>
>>   #include <clk-uclass.h>
>>   #include <dm/device.h>
>> @@ -16,6 +17,10 @@
>>   #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC	"imx_clk_pllv3_generic"
>>   #define UBOOT_DM_CLK_IMX_PLLV3_SYS	"imx_clk_pllv3_sys"
>>   #define UBOOT_DM_CLK_IMX_PLLV3_USB	"imx_clk_pllv3_usb"
>> +#define UBOOT_DM_CLK_IMX_PLLV3_AV	"imx_clk_pllv3_av"
>> +
>> +#define PLL_NUM_OFFSET		0x10
>> +#define PLL_DENOM_OFFSET	0x20
>>   
>>   #define BM_PLL_POWER		(0x1 << 12)
>>   #define BM_PLL_LOCK		(0x1 << 31)
>> @@ -143,6 +148,65 @@ static const struct clk_ops clk_pllv3_sys_ops = {
>>   	.set_rate	= clk_pllv3_sys_set_rate,
>>   };
>>   
>> +static ulong clk_pllv3_av_get_rate(struct clk *clk)
>> +{
>> +	struct clk_pllv3 *pll = to_clk_pllv3(clk);
>> +	unsigned long parent_rate = clk_get_parent_rate(clk);
>> +	u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
>> +	u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
>> +	u32 div = readl(pll->base) & pll->div_mask;
>> +	u64 temp64 = (u64)parent_rate;
>> +
>> +	temp64 *= mfn;
>> +	do_div(temp64, mfd);
>> +
>> +	return parent_rate * div + (unsigned long)temp64;
>> +}
>> +
>> +static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
>> +{
>> +	struct clk_pllv3 *pll = to_clk_pllv3(clk);
>> +	unsigned long parent_rate = clk_get_parent_rate(clk);
>> +	unsigned long min_rate = parent_rate * 27;
>> +	unsigned long max_rate = parent_rate * 54;
>> +	u32 val, div;
>> +	u32 mfn, mfd = 1000000;
>> +	u32 max_mfd = 0x3FFFFFFF;
>> +	u64 temp64;
>> +
>> +	if (rate < min_rate || rate > max_rate)
>> +		return -EINVAL;
>> +
>> +	if (parent_rate <= max_mfd)
>> +		mfd = parent_rate;
>> +
>> +	div = rate / parent_rate;
>> +	temp64 = (u64)(rate - div * parent_rate);
>> +	temp64 *= mfd;
>> +	do_div(temp64, parent_rate);
>> +	mfn = temp64;
>> +
>> +	val = readl(pll->base);
>> +	val &= ~pll->div_mask;
>> +	val |= div;
>> +	writel(val, pll->base);
>> +	writel(mfn, pll->base + PLL_NUM_OFFSET);
>> +	writel(mfd, pll->base + PLL_DENOM_OFFSET);
>> +
>> +	/* Wait for PLL to lock */
>> +	while (!(readl(pll->base) & BM_PLL_LOCK))
>> +		;
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct clk_ops clk_pllv3_av_ops = {
>> +	.enable		= clk_pllv3_generic_enable,
>> +	.disable	= clk_pllv3_generic_disable,
>> +	.get_rate	= clk_pllv3_av_get_rate,
>> +	.set_rate	= clk_pllv3_av_set_rate,
>> +};
>> +
>>   struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
>>   			  const char *parent_name, void __iomem
>> *base, u32 div_mask)
>> @@ -174,6 +238,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type
>> type, const char *name, pll->div_shift = 1;
>>   		pll->powerup_set = true;
>>   		break;
>> +	case IMX_PLLV3_AV:
>> +		drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
>> +		pll->div_shift = 0;
>> +		pll->powerup_set = false;
>> +		break;
>>   	default:
>>   		kfree(pll);
>>   		return ERR_PTR(-ENOTSUPP);
>> @@ -212,3 +281,10 @@ U_BOOT_DRIVER(clk_pllv3_usb) = {
>>   	.ops	= &clk_pllv3_generic_ops,
>>   	.flags = DM_FLAG_PRE_RELOC,
>>   };
>> +
>> +U_BOOT_DRIVER(clk_pllv3_av) = {
>> +	.name	= UBOOT_DM_CLK_IMX_PLLV3_AV,
>> +	.id	= UCLASS_CLK,
>> +	.ops	= &clk_pllv3_av_ops,
>> +	.flags = DM_FLAG_PRE_RELOC,
>> +};
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH] serial_lpuart: make clock failure less verbose
  2020-01-31 13:39       ` [PATCH] serial_lpuart: make clock failure less verbose Giulio Benetti
@ 2020-01-31 18:14         ` Simon Glass
  2020-01-31 20:24           ` Giulio Benetti
  2020-03-10 15:31         ` sbabic at denx.de
  1 sibling, 1 reply; 54+ messages in thread
From: Simon Glass @ 2020-01-31 18:14 UTC (permalink / raw)
  To: u-boot

On Fri, 31 Jan 2020 at 06:39, Giulio Benetti
<giulio.benetti@benettiengineering.com> wrote:
>
> Some device may enable CONFIG_CLK but not still support this clock in
> CC, so better use debug() in place of dev_warn() otherwise a lot of
> boards will throw useless dev_warn()s.
>
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
>  drivers/serial/serial_lpuart.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH] serial_lpuart: make clock failure less verbose
  2020-01-31 18:14         ` Simon Glass
@ 2020-01-31 20:24           ` Giulio Benetti
  2020-02-01 12:48             ` Lukasz Majewski
  0 siblings, 1 reply; 54+ messages in thread
From: Giulio Benetti @ 2020-01-31 20:24 UTC (permalink / raw)
  To: u-boot

Hi Lukasz,

On 1/31/20 7:14 PM, Simon Glass wrote:
> On Fri, 31 Jan 2020 at 06:39, Giulio Benetti
> <giulio.benetti@benettiengineering.com> wrote:
>>
>> Some device may enable CONFIG_CLK but not still support this clock in
>> CC, so better use debug() in place of dev_warn() otherwise a lot of

    ^^ this must be CCF. Can you correct commit log while applying?

Thanks in advance
-- 
Giulio Benetti
Benetti Engineering sas

>> boards will throw useless dev_warn()s.
>>
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>>   drivers/serial/serial_lpuart.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH] serial_lpuart: make clock failure less verbose
  2020-01-31 20:24           ` Giulio Benetti
@ 2020-02-01 12:48             ` Lukasz Majewski
  2020-02-10 22:17               ` Giulio Benetti
  0 siblings, 1 reply; 54+ messages in thread
From: Lukasz Majewski @ 2020-02-01 12:48 UTC (permalink / raw)
  To: u-boot

Hi Giulio,

> Hi Lukasz,
> 
> On 1/31/20 7:14 PM, Simon Glass wrote:
> > On Fri, 31 Jan 2020 at 06:39, Giulio Benetti
> > <giulio.benetti@benettiengineering.com> wrote:  
> >>
> >> Some device may enable CONFIG_CLK but not still support this clock
> >> in CC, so better use debug() in place of dev_warn() otherwise a
> >> lot of  
> 
>     ^^ this must be CCF. Can you correct commit log while applying?

I think that Stefano (or Tom) will apply this patch (as it is related to
i.MX SoC's uart).

> 
> Thanks in advance




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH] serial_lpuart: make clock failure less verbose
  2020-02-01 12:48             ` Lukasz Majewski
@ 2020-02-10 22:17               ` Giulio Benetti
  0 siblings, 0 replies; 54+ messages in thread
From: Giulio Benetti @ 2020-02-10 22:17 UTC (permalink / raw)
  To: u-boot

+Cc Stefano

On 2/1/20 1:48 PM, Lukasz Majewski wrote:
> Hi Giulio,
> 
>> Hi Lukasz,
>>
>> On 1/31/20 7:14 PM, Simon Glass wrote:
>>> On Fri, 31 Jan 2020 at 06:39, Giulio Benetti
>>> <giulio.benetti@benettiengineering.com> wrote:
>>>>
>>>> Some device may enable CONFIG_CLK but not still support this clock
>>>> in CC, so better use debug() in place of dev_warn() otherwise a
>>>> lot of
>>
>>      ^^ this must be CCF. Can you correct commit log while applying?
> 
> I think that Stefano (or Tom) will apply this patch (as it is related to
> i.MX SoC's uart).
> 
>>
>> Thanks in advance
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
> 

-- 
Giulio Benetti
Benetti Engineering sas

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH] serial_lpuart: make clock failure less verbose
  2020-01-31 13:39       ` [PATCH] serial_lpuart: make clock failure less verbose Giulio Benetti
  2020-01-31 18:14         ` Simon Glass
@ 2020-03-10 15:31         ` sbabic at denx.de
  1 sibling, 0 replies; 54+ messages in thread
From: sbabic at denx.de @ 2020-03-10 15:31 UTC (permalink / raw)
  To: u-boot

> Some device may enable CONFIG_CLK but not still support this clock in
> CC, so better use debug() in place of dev_warn() otherwise a lot of
> boards will throw useless dev_warn()s.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 54+ messages in thread

end of thread, other threads:[~2020-03-10 15:31 UTC | newest]

Thread overview: 54+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-10 14:46 [PATCH v2 00/21] Add i.MXRT family support Giulio Benetti
2020-01-10 14:46 ` [PATCH v2 01/21] spl: fix entry_point equal to load_addr Giulio Benetti
2020-01-15 12:46   ` sbabic at denx.de
2020-01-28  8:09   ` Lukasz Majewski
2020-01-28 16:37     ` Giulio Benetti
2020-01-29  8:33       ` Lukasz Majewski
2020-01-10 14:46 ` [PATCH v2 02/21] armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibility Giulio Benetti
2020-01-15 12:46   ` sbabic at denx.de
2020-01-28  8:10   ` Lukasz Majewski
2020-01-28 16:50     ` Giulio Benetti
2020-01-29  8:36       ` Lukasz Majewski
2020-01-10 14:46 ` [PATCH v2 03/21] clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Giulio Benetti
2020-01-15 12:47   ` sbabic at denx.de
2020-01-10 14:46 ` [PATCH v2 04/21] clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB Giulio Benetti
2020-01-15 12:47   ` sbabic at denx.de
2020-01-10 14:46 ` [PATCH v2 05/21] clk: imx: pllv3: add enable() support Giulio Benetti
2020-01-15 12:46   ` sbabic at denx.de
2020-01-28  8:14   ` Lukasz Majewski
2020-01-28 18:46     ` Giulio Benetti
2020-01-10 14:46 ` [PATCH v2 06/21] clk: imx: pllv3: add disable() support Giulio Benetti
2020-01-15 12:47   ` sbabic at denx.de
2020-01-10 14:46 ` [PATCH v2 07/21] clk: imx: pllv3: add set_rate() support Giulio Benetti
2020-01-15 12:46   ` sbabic at denx.de
2020-01-10 14:46 ` [PATCH v2 08/21] clk: imx: pllv3: add PLLV3_SYS support Giulio Benetti
2020-01-15 12:47   ` sbabic at denx.de
2020-01-10 14:46 ` [PATCH v2 09/21] clk: imx: pllv3: add support for PLLV3_AV type Giulio Benetti
2020-01-15 12:46   ` sbabic at denx.de
2020-01-28  8:20   ` Lukasz Majewski
2020-01-31 13:50     ` Giulio Benetti
2020-01-10 14:47 ` [PATCH v2 10/21] clk: imx: pfd: add set_rate() Giulio Benetti
2020-01-15 12:46   ` sbabic at denx.de
2020-01-10 14:47 ` [PATCH v2 11/21] clk: imx: add i.IMXRT1050 clk driver Giulio Benetti
2020-01-15 12:46   ` sbabic at denx.de
2020-01-28  8:23   ` Lukasz Majewski
2020-01-10 14:47 ` [PATCH v2 12/21] pinctrl: add i.MXRT driver Giulio Benetti
2020-01-15 12:47   ` sbabic at denx.de
2020-01-28  8:27   ` Lukasz Majewski
2020-01-10 14:47 ` [PATCH v2 13/21] gpio: mxc_gpio: add support for i.MXRT1050 Giulio Benetti
2020-01-15 12:46   ` sbabic at denx.de
2020-01-28  8:27   ` Lukasz Majewski
2020-01-10 14:47 ` [PATCH v2 14/21] ARM: dts: imxrt1050: add dtsi file Giulio Benetti
2020-01-15 12:47   ` sbabic at denx.de
2020-01-28  8:31   ` Lukasz Majewski
2020-01-28 18:48     ` Giulio Benetti
2020-01-10 14:47 ` [PATCH v2 15/21] serial_lpuart: add clock enable if CONFIG_CLK is defined Giulio Benetti
2020-01-15 12:47   ` sbabic at denx.de
2020-01-28  8:36   ` Lukasz Majewski
2020-01-28 18:49     ` Giulio Benetti
2020-01-31 13:39       ` [PATCH] serial_lpuart: make clock failure less verbose Giulio Benetti
2020-01-31 18:14         ` Simon Glass
2020-01-31 20:24           ` Giulio Benetti
2020-02-01 12:48             ` Lukasz Majewski
2020-02-10 22:17               ` Giulio Benetti
2020-03-10 15:31         ` sbabic at denx.de

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