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From: Roger Pau Monne <roger.pau@citrix.com>
To: <xen-devel@lists.xenproject.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
	Paul Durrant <paul@xen.org>, Wei Liu <wl@xen.org>,
	Jan Beulich <jbeulich@suse.com>,
	Roger Pau Monne <roger.pau@citrix.com>
Subject: [Xen-devel] [PATCH v2 2/3] x86/hvm: rework HVMOP_flush_tlbs
Date: Fri, 10 Jan 2020 17:04:03 +0100	[thread overview]
Message-ID: <20200110160404.15573-3-roger.pau@citrix.com> (raw)
In-Reply-To: <20200110160404.15573-1-roger.pau@citrix.com>

Current implementation of hvm_flush_vcpu_tlb is highly inefficient.

First of all the call to flush_tlb_mask is completely useless when
trying to flush the TLB of HVM guests, as this TLB flush is executed in
root mode, and hence doesn't flush any guest state cache.

Secondly, calling paging_update_cr3 albeit correct, is much more
expensive than strictly required. Instead a TLB flush can be achieved by
calling hvm_asid_flush_vcpu on each pCPU that has a domain vCPU state
currently loaded. This call will invalidate the current non-root
context, thus forcing a clean cache state on vmentry. If the guest is
not using ASIDs, the vmexit caused by the on_selected_cpus IPI will
already force a TLB flush.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/hvm/hvm.c               | 54 ++++++++++++----------------
 xen/arch/x86/hvm/viridian/viridian.c |  7 +---
 xen/include/asm-x86/hvm/hvm.h        |  2 +-
 3 files changed, 25 insertions(+), 38 deletions(-)

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 4723f5d09c..e4fef0afcd 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -3973,7 +3973,21 @@ static void hvm_s3_resume(struct domain *d)
     }
 }
 
-bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
+static void do_flush(void *data)
+{
+    cpumask_t *mask = data;
+    unsigned int cpu = smp_processor_id();
+
+    ASSERT(cpumask_test_cpu(cpu, mask));
+    /*
+     * A vmexit/vmenter (caused by the IPI issued to execute this function) is
+     * enough to force a TLB flush since we have already ticked the vCPU ASID
+     * prior to issuing the IPI.
+     */
+    cpumask_clear_cpu(cpu, mask);
+}
+
+void hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
                         void *ctxt)
 {
     static DEFINE_PER_CPU(cpumask_t, flush_cpumask);
@@ -3981,27 +3995,8 @@ bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
     struct domain *d = current->domain;
     struct vcpu *v;
 
-    /* Avoid deadlock if more than one vcpu tries this at the same time. */
-    if ( !spin_trylock(&d->hypercall_deadlock_mutex) )
-        return false;
-
-    /* Pause all other vcpus. */
-    for_each_vcpu ( d, v )
-        if ( v != current && flush_vcpu(ctxt, v) )
-            vcpu_pause_nosync(v);
-
-    /* Now that all VCPUs are signalled to deschedule, we wait... */
-    for_each_vcpu ( d, v )
-        if ( v != current && flush_vcpu(ctxt, v) )
-            while ( !vcpu_runnable(v) && v->is_running )
-                cpu_relax();
-
-    /* All other vcpus are paused, safe to unlock now. */
-    spin_unlock(&d->hypercall_deadlock_mutex);
-
     cpumask_clear(mask);
 
-    /* Flush paging-mode soft state (e.g., va->gfn cache; PAE PDPE cache). */
     for_each_vcpu ( d, v )
     {
         unsigned int cpu;
@@ -4009,22 +4004,17 @@ bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
         if ( !flush_vcpu(ctxt, v) )
             continue;
 
-        paging_update_cr3(v, false);
+        hvm_asid_flush_vcpu(v);
 
         cpu = read_atomic(&v->dirty_cpu);
-        if ( is_vcpu_dirty_cpu(cpu) )
+        if ( cpu != smp_processor_id() && is_vcpu_dirty_cpu(cpu) )
             __cpumask_set_cpu(cpu, mask);
     }
 
-    /* Flush TLBs on all CPUs with dirty vcpu state. */
-    flush_tlb_mask(mask);
+    on_selected_cpus(mask, do_flush, mask, 0);
 
-    /* Done. */
-    for_each_vcpu ( d, v )
-        if ( v != current && flush_vcpu(ctxt, v) )
-            vcpu_unpause(v);
-
-    return true;
+    while ( !cpumask_empty(mask) )
+        cpu_relax();
 }
 
 static bool always_flush(void *ctxt, struct vcpu *v)
@@ -4037,7 +4027,9 @@ static int hvmop_flush_tlb_all(void)
     if ( !is_hvm_domain(current->domain) )
         return -EINVAL;
 
-    return hvm_flush_vcpu_tlb(always_flush, NULL) ? 0 : -ERESTART;
+    hvm_flush_vcpu_tlb(always_flush, NULL);
+
+    return 0;
 }
 
 static int hvmop_set_evtchn_upcall_vector(
diff --git a/xen/arch/x86/hvm/viridian/viridian.c b/xen/arch/x86/hvm/viridian/viridian.c
index 44c8e6cac6..ec73361597 100644
--- a/xen/arch/x86/hvm/viridian/viridian.c
+++ b/xen/arch/x86/hvm/viridian/viridian.c
@@ -604,12 +604,7 @@ int viridian_hypercall(struct cpu_user_regs *regs)
         if ( input_params.flags & HV_FLUSH_ALL_PROCESSORS )
             input_params.vcpu_mask = ~0ul;
 
-        /*
-         * A false return means that another vcpu is currently trying
-         * a similar operation, so back off.
-         */
-        if ( !hvm_flush_vcpu_tlb(need_flush, &input_params.vcpu_mask) )
-            return HVM_HCALL_preempted;
+        hvm_flush_vcpu_tlb(need_flush, &input_params.vcpu_mask);
 
         output.rep_complete = input.rep_count;
 
diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h
index 09793c12e9..1f70ee0823 100644
--- a/xen/include/asm-x86/hvm/hvm.h
+++ b/xen/include/asm-x86/hvm/hvm.h
@@ -333,7 +333,7 @@ const char *hvm_efer_valid(const struct vcpu *v, uint64_t value,
                            signed int cr0_pg);
 unsigned long hvm_cr4_guest_valid_bits(const struct domain *d, bool restore);
 
-bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
+void hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v),
                         void *ctxt);
 
 #ifdef CONFIG_HVM
-- 
2.24.1


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  parent reply	other threads:[~2020-01-10 16:04 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-10 16:04 [Xen-devel] [PATCH v2 0/3] x86: improve assisted tlb flush and use it in guest mode Roger Pau Monne
2020-01-10 16:04 ` [Xen-devel] [PATCH v2 1/3] x86/hvm: allow ASID flush when v != current Roger Pau Monne
2020-01-10 16:04 ` Roger Pau Monne [this message]
2020-01-10 16:04 ` [Xen-devel] [PATCH v2 3/3] x86/tlb: use Xen L0 assisted TLB flush when available Roger Pau Monne
2020-01-10 16:08 ` [Xen-devel] [PATCH v2 0/3] x86: improve assisted tlb flush and use it in guest mode Jan Beulich
2020-01-10 16:14   ` Roger Pau Monné

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