From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vidya Sagar Subject: [PATCH V3 0/2] PCI: Add MCFG quirks for Tegra194 host controllers Date: Sat, 11 Jan 2020 00:44:58 +0530 Message-ID: <20200110191500.9538-1-vidyas@nvidia.com> References: <20200106082709.14370-1-vidyas@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20200106082709.14370-1-vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org, rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org, lenb-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, andrew.murray-5wv7dgnIgG8@public.gmane.org, treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, kthota-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, sagar.tv-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org List-Id: linux-tegra@vger.kernel.org The PCIe controller in Tegra194 SoC is not completely ECAM-compliant. With the current hardware design limitations in place, ECAM can be enabled only for one controller (C5 controller to be precise) with bus numbers starting from 160 instead of 0. A different approach is taken to avoid this abnormal way of enabling ECAM for just one controller but to enable configuration space access for all the other controllers. In this approach, ops are added through MCFG quirk mechanism which access the configuration spaces by dynamically programming iATU (internal AddressTranslation Unit) to generate respective configuration accesses just like the way it is done in DesignWare core sub-system. To increase the size of ECAM, a device-tree change is pushed in this series to move the IO window from 32-bit PCIe aperture to 64-bit PCIe aperture leaving the entire 32MB of 32-bit aperture for configuration space access. V3: * Pushed a device-tree change in the series to enable more space for ECAM Vidya Sagar (2): arm64: tegra: Re-order PCIe aperture mappings to support ACPI boot PCI: Add MCFG quirks for Tegra194 host controllers arch/arm64/boot/dts/nvidia/tegra194.dtsi | 36 ++++---- drivers/acpi/pci_mcfg.c | 7 ++ drivers/pci/controller/dwc/Kconfig | 3 +- drivers/pci/controller/dwc/Makefile | 2 +- drivers/pci/controller/dwc/pcie-tegra194.c | 102 +++++++++++++++++++++ include/linux/pci-ecam.h | 1 + 6 files changed, 131 insertions(+), 20 deletions(-) -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49406C282DD for ; Fri, 10 Jan 2020 19:15:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1563D2051A for ; Fri, 10 Jan 2020 19:15:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="a9XjmD7v" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727812AbgAJTPJ (ORCPT ); Fri, 10 Jan 2020 14:15:09 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:1659 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727612AbgAJTPJ (ORCPT ); Fri, 10 Jan 2020 14:15:09 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 10 Jan 2020 11:14:50 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 10 Jan 2020 11:15:08 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 10 Jan 2020 11:15:08 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 10 Jan 2020 19:15:08 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 10 Jan 2020 19:15:08 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.48]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 10 Jan 2020 11:15:07 -0800 From: Vidya Sagar To: , , , , , , CC: , , , , , , , Subject: [PATCH V3 0/2] PCI: Add MCFG quirks for Tegra194 host controllers Date: Sat, 11 Jan 2020 00:44:58 +0530 Message-ID: <20200110191500.9538-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200106082709.14370-1-vidyas@nvidia.com> References: <20200106082709.14370-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578683690; bh=ijKK/DiU1QbdSZI//ZXmG99ZEoUzM/+Rr+0S/t1xBHU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=a9XjmD7vpFdKxUPscAV1tPEV+9JDgitMBH9OKMH3NETpDRHbK+JlZwqHKIIF0xJbU fnabinmenQjQjf3Ys7EUXue4hATK3hFof/wbfZLzOANr1C1tgFL+/koGp5KN/R2tsL tVjga8Jup/uU+FKx2yDW8LDrEaok3SzUrvNJwrrG7+I9XPio4uCLDJxtO0DsggFXgB Duwa7xXH35P0ijXtfSmM5zXbSUZnsk6G9wdpXEGBVE01ERa2jJfEzslXr5hm8/SphO NNQCkL2IJ5jaCzoae1BPlC7y1S9eg1hhyJOGwlhXzvLsr1WLFd/baB0oqx+uU7QiE/ eUZf3Bk+HSeVg== Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The PCIe controller in Tegra194 SoC is not completely ECAM-compliant. With the current hardware design limitations in place, ECAM can be enabled only for one controller (C5 controller to be precise) with bus numbers starting from 160 instead of 0. A different approach is taken to avoid this abnormal way of enabling ECAM for just one controller but to enable configuration space access for all the other controllers. In this approach, ops are added through MCFG quirk mechanism which access the configuration spaces by dynamically programming iATU (internal AddressTranslation Unit) to generate respective configuration accesses just like the way it is done in DesignWare core sub-system. To increase the size of ECAM, a device-tree change is pushed in this series to move the IO window from 32-bit PCIe aperture to 64-bit PCIe aperture leaving the entire 32MB of 32-bit aperture for configuration space access. V3: * Pushed a device-tree change in the series to enable more space for ECAM Vidya Sagar (2): arm64: tegra: Re-order PCIe aperture mappings to support ACPI boot PCI: Add MCFG quirks for Tegra194 host controllers arch/arm64/boot/dts/nvidia/tegra194.dtsi | 36 ++++---- drivers/acpi/pci_mcfg.c | 7 ++ drivers/pci/controller/dwc/Kconfig | 3 +- drivers/pci/controller/dwc/Makefile | 2 +- drivers/pci/controller/dwc/pcie-tegra194.c | 102 +++++++++++++++++++++ include/linux/pci-ecam.h | 1 + 6 files changed, 131 insertions(+), 20 deletions(-) -- 2.17.1