From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C024C33CAF for ; Mon, 13 Jan 2020 12:02:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D87ED2084D for ; Mon, 13 Jan 2020 12:02:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728824AbgAMMCy (ORCPT ); Mon, 13 Jan 2020 07:02:54 -0500 Received: from foss.arm.com ([217.140.110.172]:38470 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726127AbgAMMCx (ORCPT ); Mon, 13 Jan 2020 07:02:53 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D6A9B13D5; Mon, 13 Jan 2020 04:02:52 -0800 (PST) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 23CB73F6C4; Mon, 13 Jan 2020 04:02:52 -0800 (PST) Date: Mon, 13 Jan 2020 12:02:50 +0000 From: Andrew Murray To: "Z.q. Hou" Cc: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "arnd@arndb.de" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , "m.karthikeyan@mobiveil.co.in" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Mingkai Hu , "M.h. Lian" , Xiaowei Bao Subject: Re: [PATCHv9 10/12] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs Message-ID: <20200113120249.GO42593@e119886-lin.cambridge.arm.com> References: <20191120034451.30102-1-Zhiqiang.Hou@nxp.com> <20191120034451.30102-11-Zhiqiang.Hou@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20191120034451.30102-11-Zhiqiang.Hou@nxp.com> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Nov 20, 2019 at 03:46:23AM +0000, Z.q. Hou wrote: > From: Hou Zhiqiang > > This PCIe controller is based on the Mobiveil GPEX IP, which is > compatible with the PCI Express™ Base Specification, Revision 4.0. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > drivers/pci/controller/mobiveil/Kconfig | 10 + > drivers/pci/controller/mobiveil/Makefile | 1 + > .../mobiveil/pcie-layerscape-gen4.c | 274 ++++++++++++++++++ > .../pci/controller/mobiveil/pcie-mobiveil.h | 16 +- > 4 files changed, 299 insertions(+), 2 deletions(-) > create mode 100644 drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c > > diff --git a/drivers/pci/controller/mobiveil/Kconfig b/drivers/pci/controller/mobiveil/Kconfig > index 64343c07bfed..c823be8dab1c 100644 > --- a/drivers/pci/controller/mobiveil/Kconfig > +++ b/drivers/pci/controller/mobiveil/Kconfig > @@ -21,4 +21,14 @@ config PCIE_MOBIVEIL_PLAT > Soft IP. It has up to 8 outbound and inbound windows > for address translation and it is a PCIe Gen4 IP. > > +config PCIE_LAYERSCAPE_GEN4 > + bool "Freescale Layerscape PCIe Gen4 controller" > + depends on PCI > + depends on OF && (ARM64 || ARCH_LAYERSCAPE) > + depends on PCI_MSI_IRQ_DOMAIN > + select PCIE_MOBIVEIL_HOST > + help > + Say Y here if you want PCIe Gen4 controller support on > + Layerscape SoCs. The PCIe controller can work in RC or > + EP mode according to RCW[HOST_AGT_PEX] setting. I think you can remove the last sentence - it doesn't give any value to users of KConfig. > endmenu > diff --git a/drivers/pci/controller/mobiveil/Makefile b/drivers/pci/controller/mobiveil/Makefile > index 9fb6d1c6504d..99d879de32d6 100644 > --- a/drivers/pci/controller/mobiveil/Makefile > +++ b/drivers/pci/controller/mobiveil/Makefile > @@ -2,3 +2,4 @@ > obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o > obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o > obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o > +obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie-layerscape-gen4.o > diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c > new file mode 100644 > index 000000000000..6c0d3e2532db > --- /dev/null > +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c > @@ -0,0 +1,274 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * PCIe Gen4 host controller driver for NXP Layerscape SoCs > + * > + * Copyright 2019 NXP > + * > + * Author: Zhiqiang Hou > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "pcie-mobiveil.h" > + > +/* LUT and PF control registers */ > +#define PCIE_LUT_OFF 0x80000 > +#define PCIE_PF_OFF 0xc0000 > +#define PCIE_PF_INT_STAT 0x18 > +#define PF_INT_STAT_PABRST BIT(31) > + > +#define PCIE_PF_DBG 0x7fc > +#define PF_DBG_LTSSM_MASK 0x3f > +#define PF_DBG_LTSSM_L0 0x2d /* L0 state */ > +#define PF_DBG_WE BIT(31) > +#define PF_DBG_PABR BIT(27) > + > +#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev) > + > +struct ls_pcie_g4 { > + struct mobiveil_pcie pci; > + struct delayed_work dwork; > + int irq; > +}; > + > +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off) > +{ > + return ioread32(pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off); > +} > + > +static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie, > + u32 off, u32 val) > +{ > + iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off); > +} > + > +static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off) > +{ > + return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); > +} > + > +static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie, > + u32 off, u32 val) > +{ > + iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); > +} > + > +static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie) > +{ > + struct mobiveil_pcie *mv_pci = &pcie->pci; > + u32 header_type; > + > + header_type = mobiveil_csr_readb(mv_pci, PCI_HEADER_TYPE); > + header_type &= 0x7f; > + > + return header_type == PCI_HEADER_TYPE_BRIDGE; > +} > + > +static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci) > +{ > + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci); > + u32 state; > + > + state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); > + state = state & PF_DBG_LTSSM_MASK; > + > + if (state == PF_DBG_LTSSM_L0) > + return 1; > + > + return 0; > +} > + > +static void ls_pcie_g4_disable_interrupt(struct ls_pcie_g4 *pcie) > +{ > + struct mobiveil_pcie *mv_pci = &pcie->pci; > + > + mobiveil_csr_writel(mv_pci, 0, PAB_INTP_AMBA_MISC_ENB); > +} > + > +static void ls_pcie_g4_enable_interrupt(struct ls_pcie_g4 *pcie) > +{ > + struct mobiveil_pcie *mv_pci = &pcie->pci; > + u32 val; > + > + /* Clear the interrupt status */ > + mobiveil_csr_writel(mv_pci, 0xffffffff, PAB_INTP_AMBA_MISC_STAT); > + > + val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET | > + PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC; > + mobiveil_csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB); > +} > + > +static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie) > +{ > + struct mobiveil_pcie *mv_pci = &pcie->pci; > + struct device *dev = &mv_pci->pdev->dev; > + u32 val, act_stat; > + int to = 100; > + > + /* Poll for pab_csb_reset to set and PAB activity to clear */ > + do { > + usleep_range(10, 15); > + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT); > + act_stat = mobiveil_csr_readl(mv_pci, PAB_ACTIVITY_STAT); > + } while (((val & PF_INT_STAT_PABRST) == 0 || act_stat) && to--); > + if (to < 0) { > + dev_err(dev, "Poll PABRST&PABACT timeout\n"); > + return; If a timeout happens here - the caller has no idea this has happened and yet the following work doesn't get done. Isn't this a problem? > + } > + > + /* clear PEX_RESET bit in PEX_PF0_DBG register */ > + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); > + val |= PF_DBG_WE; > + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); > + > + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); > + val |= PF_DBG_PABR; > + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); > + > + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); > + val &= ~PF_DBG_WE; > + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); > + > + mobiveil_host_init(mv_pci, true); Can mobiveil_host_init fail? > + > + to = 100; > + while (!ls_pcie_g4_link_up(mv_pci) && to--) > + usleep_range(200, 250); > + if (to < 0) > + dev_err(dev, "PCIe link training timeout\n"); > +} > + > +static irqreturn_t ls_pcie_g4_isr(int irq, void *dev_id) > +{ > + struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id; > + struct mobiveil_pcie *mv_pci = &pcie->pci; > + u32 val; > + > + val = mobiveil_csr_readl(mv_pci, PAB_INTP_AMBA_MISC_STAT); > + if (!val) > + return IRQ_NONE; > + > + if (val & PAB_INTP_RESET) { Can you explain why this is needed (perhaps also in the cover letter)? > + ls_pcie_g4_disable_interrupt(pcie); > + schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1)); > + } > + > + mobiveil_csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_STAT); > + > + return IRQ_HANDLED; > +} > + > +static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci) > +{ > + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci); > + struct platform_device *pdev = mv_pci->pdev; > + struct device *dev = &pdev->dev; > + int ret; > + > + pcie->irq = platform_get_irq_byname(pdev, "intr"); > + if (pcie->irq < 0) { > + dev_err(dev, "Can't get 'intr' IRQ, errno = %d\n", pcie->irq); > + return pcie->irq; > + } > + ret = devm_request_irq(dev, pcie->irq, ls_pcie_g4_isr, > + IRQF_SHARED, pdev->name, pcie); > + if (ret) { > + dev_err(dev, "Can't register PCIe IRQ, errno = %d\n", ret); > + return ret; > + } > + > + return 0; > +} > + > +static void ls_pcie_g4_reset(struct work_struct *work) > +{ > + struct delayed_work *dwork = container_of(work, struct delayed_work, > + work); > + struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork); > + struct mobiveil_pcie *mv_pci = &pcie->pci; > + u16 ctrl; > + > + ctrl = mobiveil_csr_readw(mv_pci, PCI_BRIDGE_CONTROL); > + ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; > + mobiveil_csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL); > + ls_pcie_g4_reinit_hw(pcie); > + ls_pcie_g4_enable_interrupt(pcie); > +} > + > +static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = { > + .interrupt_init = ls_pcie_g4_interrupt_init, > +}; > + > +static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = { > + .link_up = ls_pcie_g4_link_up, > +}; > + > +static int __init ls_pcie_g4_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct pci_host_bridge *bridge; > + struct mobiveil_pcie *mv_pci; > + struct ls_pcie_g4 *pcie; > + struct device_node *np = dev->of_node; > + int ret; > + > + if (!of_parse_phandle(np, "msi-parent", 0)) { > + dev_err(dev, "Failed to find msi-parent\n"); > + return -EINVAL; > + } > + > + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); > + if (!bridge) > + return -ENOMEM; > + > + pcie = pci_host_bridge_priv(bridge); > + mv_pci = &pcie->pci; > + > + mv_pci->pdev = pdev; > + mv_pci->ops = &ls_pcie_g4_pab_ops; > + mv_pci->rp.ops = &ls_pcie_g4_rp_ops; > + mv_pci->rp.bridge = bridge; > + > + platform_set_drvdata(pdev, pcie); > + > + INIT_DELAYED_WORK(&pcie->dwork, ls_pcie_g4_reset); > + > + ret = mobiveil_pcie_host_probe(mv_pci); > + if (ret) { > + dev_err(dev, "Fail to probe\n"); > + return ret; > + } > + > + if (!ls_pcie_g4_is_bridge(pcie)) Is this a check that could apply to all host bridge drivers and thus live in mobiveil_pcie_host_probe? > + return -ENODEV; > + > + ls_pcie_g4_enable_interrupt(pcie); Is there an issue here in that we enable interrupts *after* telling the kernel about our controller? (Same applies for bailing if the IP isn't a bridge). Thanks, Andrew Murray > + > + return 0; > +} > + > +static const struct of_device_id ls_pcie_g4_of_match[] = { > + { .compatible = "fsl,lx2160a-pcie", }, > + { }, > +}; > + > +static struct platform_driver ls_pcie_g4_driver = { > + .driver = { > + .name = "layerscape-pcie-gen4", > + .of_match_table = ls_pcie_g4_of_match, > + .suppress_bind_attrs = true, > + }, > +}; > + > +builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe); > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > index 750a7fd95bc1..c57a68d2bac4 100644 > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > @@ -43,6 +43,8 @@ > #define PAGE_LO_MASK 0x3ff > #define PAGE_SEL_OFFSET_SHIFT 10 > > +#define PAB_ACTIVITY_STAT 0x81c > + > #define PAB_AXI_PIO_CTRL 0x0840 > #define APIO_EN_MASK 0xf > > @@ -51,8 +53,18 @@ > > #define PAB_INTP_AMBA_MISC_ENB 0x0b0c > #define PAB_INTP_AMBA_MISC_STAT 0x0b1c > -#define PAB_INTP_INTX_MASK 0x01e0 > -#define PAB_INTP_MSI_MASK 0x8 > +#define PAB_INTP_RESET BIT(1) > +#define PAB_INTP_MSI BIT(3) > +#define PAB_INTP_INTA BIT(5) > +#define PAB_INTP_INTB BIT(6) > +#define PAB_INTP_INTC BIT(7) > +#define PAB_INTP_INTD BIT(8) > +#define PAB_INTP_PCIE_UE BIT(9) > +#define PAB_INTP_IE_PMREDI BIT(29) > +#define PAB_INTP_IE_EC BIT(30) > +#define PAB_INTP_MSI_MASK PAB_INTP_MSI > +#define PAB_INTP_INTX_MASK (PAB_INTP_INTA | PAB_INTP_INTB |\ > + PAB_INTP_INTC | PAB_INTP_INTD) > > #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) > #define WIN_ENABLE_SHIFT 0 > -- > 2.17.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6706C33CAD for ; Mon, 13 Jan 2020 12:03:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8F527207FF for ; Mon, 13 Jan 2020 12:03:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="nxm+eHWK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8F527207FF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Ly0ZK/7kARvKz0qSFRrhIY1F5YEckNUFPKqxjHJyNj4=; b=nxm+eHWK1TBC17 qKE7t4W+c2CHwCIoioCNsVGyrDL8dVVFoMC4oqqNhv4toPuT63MBLPa63FYhoOgCIuq9J2WQac0wz IaZtY3QI2UtgTyNj+fq0gXj9nz9e0Lv/0wpDaIrlLQDAx5U2r6ZMBzvnfzG95t9qy2gcSBxeYE1Q+ Rc/k6EQMryHYvwN0iKnVFSB4Tc29dH8FmVDoU8c6mix1fgn51BYXEudzJkoY2YOTCUF3w53/7sklG tmdWavCtGVpx/rOuy+CU4GkBOfBP/HEACYzNZUdDfD2e+fpz8f5ZUGE2bABWnOlJ+CR/gcEuUxHI8 1/gDT8jlcQHrQp8fUomg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iqyQs-0000NO-KJ; Mon, 13 Jan 2020 12:02:58 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iqyQn-0000M9-Tt for linux-arm-kernel@lists.infradead.org; Mon, 13 Jan 2020 12:02:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D6A9B13D5; Mon, 13 Jan 2020 04:02:52 -0800 (PST) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 23CB73F6C4; Mon, 13 Jan 2020 04:02:52 -0800 (PST) Date: Mon, 13 Jan 2020 12:02:50 +0000 From: Andrew Murray To: "Z.q. Hou" Subject: Re: [PATCHv9 10/12] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs Message-ID: <20200113120249.GO42593@e119886-lin.cambridge.arm.com> References: <20191120034451.30102-1-Zhiqiang.Hou@nxp.com> <20191120034451.30102-11-Zhiqiang.Hou@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191120034451.30102-11-Zhiqiang.Hou@nxp.com> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200113_040254_052487_2D23B551 X-CRM114-Status: GOOD ( 29.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "m.karthikeyan@mobiveil.co.in" , "arnd@arndb.de" , "linux-pci@vger.kernel.org" , "l.subrahmanya@mobiveil.co.in" , "will.deacon@arm.com" , "linux-kernel@vger.kernel.org" , Leo Li , "M.h. Lian" , "robh+dt@kernel.org" , Mingkai Hu , Xiaowei Bao , "catalin.marinas@arm.com" , "bhelgaas@google.com" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gV2VkLCBOb3YgMjAsIDIwMTkgYXQgMDM6NDY6MjNBTSArMDAwMCwgWi5xLiBIb3Ugd3JvdGU6 Cj4gRnJvbTogSG91IFpoaXFpYW5nIDxaaGlxaWFuZy5Ib3VAbnhwLmNvbT4KPiAKPiBUaGlzIFBD SWUgY29udHJvbGxlciBpcyBiYXNlZCBvbiB0aGUgTW9iaXZlaWwgR1BFWCBJUCwgd2hpY2ggaXMK PiBjb21wYXRpYmxlIHdpdGggdGhlIFBDSSBFeHByZXNz4oSiIEJhc2UgU3BlY2lmaWNhdGlvbiwg UmV2aXNpb24gNC4wLgo+IAo+IFNpZ25lZC1vZmYtYnk6IEhvdSBaaGlxaWFuZyA8WmhpcWlhbmcu SG91QG54cC5jb20+Cj4gUmV2aWV3ZWQtYnk6IE1pbmdodWFuIExpYW4gPE1pbmdodWFuLkxpYW5A bnhwLmNvbT4KPiAtLS0KPiAgZHJpdmVycy9wY2kvY29udHJvbGxlci9tb2JpdmVpbC9LY29uZmln ICAgICAgIHwgIDEwICsKPiAgZHJpdmVycy9wY2kvY29udHJvbGxlci9tb2JpdmVpbC9NYWtlZmls ZSAgICAgIHwgICAxICsKPiAgLi4uL21vYml2ZWlsL3BjaWUtbGF5ZXJzY2FwZS1nZW40LmMgICAg ICAgICAgIHwgMjc0ICsrKysrKysrKysrKysrKysrKwo+ICAuLi4vcGNpL2NvbnRyb2xsZXIvbW9i aXZlaWwvcGNpZS1tb2JpdmVpbC5oICAgfCAgMTYgKy0KPiAgNCBmaWxlcyBjaGFuZ2VkLCAyOTkg aW5zZXJ0aW9ucygrKSwgMiBkZWxldGlvbnMoLSkKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZl cnMvcGNpL2NvbnRyb2xsZXIvbW9iaXZlaWwvcGNpZS1sYXllcnNjYXBlLWdlbjQuYwo+IAo+IGRp ZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL21vYml2ZWlsL0tjb25maWcgYi9kcml2 ZXJzL3BjaS9jb250cm9sbGVyL21vYml2ZWlsL0tjb25maWcKPiBpbmRleCA2NDM0M2MwN2JmZWQu LmM4MjNiZThkYWIxYyAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL21vYml2 ZWlsL0tjb25maWcKPiArKysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL21vYml2ZWlsL0tjb25m aWcKPiBAQCAtMjEsNCArMjEsMTQgQEAgY29uZmlnIFBDSUVfTU9CSVZFSUxfUExBVAo+ICAJICBT b2Z0IElQLiBJdCBoYXMgdXAgdG8gOCBvdXRib3VuZCBhbmQgaW5ib3VuZCB3aW5kb3dzCj4gIAkg IGZvciBhZGRyZXNzIHRyYW5zbGF0aW9uIGFuZCBpdCBpcyBhIFBDSWUgR2VuNCBJUC4KPiAgCj4g K2NvbmZpZyBQQ0lFX0xBWUVSU0NBUEVfR0VONAo+ICsJYm9vbCAiRnJlZXNjYWxlIExheWVyc2Nh cGUgUENJZSBHZW40IGNvbnRyb2xsZXIiCj4gKwlkZXBlbmRzIG9uIFBDSQo+ICsJZGVwZW5kcyBv biBPRiAmJiAoQVJNNjQgfHwgQVJDSF9MQVlFUlNDQVBFKQo+ICsJZGVwZW5kcyBvbiBQQ0lfTVNJ X0lSUV9ET01BSU4KPiArCXNlbGVjdCBQQ0lFX01PQklWRUlMX0hPU1QKPiArCWhlbHAKPiArCSAg U2F5IFkgaGVyZSBpZiB5b3Ugd2FudCBQQ0llIEdlbjQgY29udHJvbGxlciBzdXBwb3J0IG9uCj4g KwkgIExheWVyc2NhcGUgU29Dcy4gVGhlIFBDSWUgY29udHJvbGxlciBjYW4gd29yayBpbiBSQyBv cgo+ICsJICBFUCBtb2RlIGFjY29yZGluZyB0byBSQ1dbSE9TVF9BR1RfUEVYXSBzZXR0aW5nLgoK SSB0aGluayB5b3UgY2FuIHJlbW92ZSB0aGUgbGFzdCBzZW50ZW5jZSAtIGl0IGRvZXNuJ3QgZ2l2 ZSBhbnkgdmFsdWUKdG8gdXNlcnMgb2YgS0NvbmZpZy4KCgo+ICBlbmRtZW51Cj4gZGlmZiAtLWdp dCBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvbW9iaXZlaWwvTWFrZWZpbGUgYi9kcml2ZXJzL3Bj aS9jb250cm9sbGVyL21vYml2ZWlsL01ha2VmaWxlCj4gaW5kZXggOWZiNmQxYzY1MDRkLi45OWQ4 NzlkZTMyZDYgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9tb2JpdmVpbC9N YWtlZmlsZQo+ICsrKyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvbW9iaXZlaWwvTWFrZWZpbGUK PiBAQCAtMiwzICsyLDQgQEAKPiAgb2JqLSQoQ09ORklHX1BDSUVfTU9CSVZFSUwpICs9IHBjaWUt bW9iaXZlaWwubwo+ICBvYmotJChDT05GSUdfUENJRV9NT0JJVkVJTF9IT1NUKSArPSBwY2llLW1v Yml2ZWlsLWhvc3Qubwo+ICBvYmotJChDT05GSUdfUENJRV9NT0JJVkVJTF9QTEFUKSArPSBwY2ll LW1vYml2ZWlsLXBsYXQubwo+ICtvYmotJChDT05GSUdfUENJRV9MQVlFUlNDQVBFX0dFTjQpICs9 IHBjaWUtbGF5ZXJzY2FwZS1nZW40Lm8KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJv bGxlci9tb2JpdmVpbC9wY2llLWxheWVyc2NhcGUtZ2VuNC5jIGIvZHJpdmVycy9wY2kvY29udHJv bGxlci9tb2JpdmVpbC9wY2llLWxheWVyc2NhcGUtZ2VuNC5jCj4gbmV3IGZpbGUgbW9kZSAxMDA2 NDQKPiBpbmRleCAwMDAwMDAwMDAwMDAuLjZjMGQzZTI1MzJkYgo+IC0tLSAvZGV2L251bGwKPiAr KysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL21vYml2ZWlsL3BjaWUtbGF5ZXJzY2FwZS1nZW40 LmMKPiBAQCAtMCwwICsxLDI3NCBAQAo+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BM LTIuMAo+ICsvKgo+ICsgKiBQQ0llIEdlbjQgaG9zdCBjb250cm9sbGVyIGRyaXZlciBmb3IgTlhQ IExheWVyc2NhcGUgU29Dcwo+ICsgKgo+ICsgKiBDb3B5cmlnaHQgMjAxOSBOWFAKPiArICoKPiAr ICogQXV0aG9yOiBaaGlxaWFuZyBIb3UgPFpoaXFpYW5nLkhvdUBueHAuY29tPgo+ICsgKi8KPiAr Cj4gKyNpbmNsdWRlIDxsaW51eC9rZXJuZWwuaD4KPiArI2luY2x1ZGUgPGxpbnV4L2ludGVycnVw dC5oPgo+ICsjaW5jbHVkZSA8bGludXgvaW5pdC5oPgo+ICsjaW5jbHVkZSA8bGludXgvb2ZfcGNp Lmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9vZl9wbGF0Zm9ybS5oPgo+ICsjaW5jbHVkZSA8bGludXgv b2ZfaXJxLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9vZl9hZGRyZXNzLmg+Cj4gKyNpbmNsdWRlIDxs aW51eC9wY2kuaD4KPiArI2luY2x1ZGUgPGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPgo+ICsjaW5j bHVkZSA8bGludXgvcmVzb3VyY2UuaD4KPiArI2luY2x1ZGUgPGxpbnV4L21mZC9zeXNjb24uaD4K PiArI2luY2x1ZGUgPGxpbnV4L3JlZ21hcC5oPgo+ICsKPiArI2luY2x1ZGUgInBjaWUtbW9iaXZl aWwuaCIKPiArCj4gKy8qIExVVCBhbmQgUEYgY29udHJvbCByZWdpc3RlcnMgKi8KPiArI2RlZmlu ZSBQQ0lFX0xVVF9PRkYJCQkweDgwMDAwCj4gKyNkZWZpbmUgUENJRV9QRl9PRkYJCQkweGMwMDAw Cj4gKyNkZWZpbmUgUENJRV9QRl9JTlRfU1RBVAkJMHgxOAo+ICsjZGVmaW5lIFBGX0lOVF9TVEFU X1BBQlJTVAkJQklUKDMxKQo+ICsKPiArI2RlZmluZSBQQ0lFX1BGX0RCRwkJCTB4N2ZjCj4gKyNk ZWZpbmUgUEZfREJHX0xUU1NNX01BU0sJCTB4M2YKPiArI2RlZmluZSBQRl9EQkdfTFRTU01fTDAJ CQkweDJkIC8qIEwwIHN0YXRlICovCj4gKyNkZWZpbmUgUEZfREJHX1dFCQkJQklUKDMxKQo+ICsj ZGVmaW5lIFBGX0RCR19QQUJSCQkJQklUKDI3KQo+ICsKPiArI2RlZmluZSB0b19sc19wY2llX2c0 KHgpCQlwbGF0Zm9ybV9nZXRfZHJ2ZGF0YSgoeCktPnBkZXYpCj4gKwo+ICtzdHJ1Y3QgbHNfcGNp ZV9nNCB7Cj4gKwlzdHJ1Y3QgbW9iaXZlaWxfcGNpZSBwY2k7Cj4gKwlzdHJ1Y3QgZGVsYXllZF93 b3JrIGR3b3JrOwo+ICsJaW50IGlycTsKPiArfTsKPiArCj4gK3N0YXRpYyBpbmxpbmUgdTMyIGxz X3BjaWVfZzRfbHV0X3JlYWRsKHN0cnVjdCBsc19wY2llX2c0ICpwY2llLCB1MzIgb2ZmKQo+ICt7 Cj4gKwlyZXR1cm4gaW9yZWFkMzIocGNpZS0+cGNpLmNzcl9heGlfc2xhdmVfYmFzZSArIFBDSUVf TFVUX09GRiArIG9mZik7Cj4gK30KPiArCj4gK3N0YXRpYyBpbmxpbmUgdm9pZCBsc19wY2llX2c0 X2x1dF93cml0ZWwoc3RydWN0IGxzX3BjaWVfZzQgKnBjaWUsCj4gKwkJCQkJIHUzMiBvZmYsIHUz MiB2YWwpCj4gK3sKPiArCWlvd3JpdGUzMih2YWwsIHBjaWUtPnBjaS5jc3JfYXhpX3NsYXZlX2Jh c2UgKyBQQ0lFX0xVVF9PRkYgKyBvZmYpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW5saW5lIHUzMiBs c19wY2llX2c0X3BmX3JlYWRsKHN0cnVjdCBsc19wY2llX2c0ICpwY2llLCB1MzIgb2ZmKQo+ICt7 Cj4gKwlyZXR1cm4gaW9yZWFkMzIocGNpZS0+cGNpLmNzcl9heGlfc2xhdmVfYmFzZSArIFBDSUVf UEZfT0ZGICsgb2ZmKTsKPiArfQo+ICsKPiArc3RhdGljIGlubGluZSB2b2lkIGxzX3BjaWVfZzRf cGZfd3JpdGVsKHN0cnVjdCBsc19wY2llX2c0ICpwY2llLAo+ICsJCQkJCXUzMiBvZmYsIHUzMiB2 YWwpCj4gK3sKPiArCWlvd3JpdGUzMih2YWwsIHBjaWUtPnBjaS5jc3JfYXhpX3NsYXZlX2Jhc2Ug KyBQQ0lFX1BGX09GRiArIG9mZik7Cj4gK30KPiArCj4gK3N0YXRpYyBib29sIGxzX3BjaWVfZzRf aXNfYnJpZGdlKHN0cnVjdCBsc19wY2llX2c0ICpwY2llKQo+ICt7Cj4gKwlzdHJ1Y3QgbW9iaXZl aWxfcGNpZSAqbXZfcGNpID0gJnBjaWUtPnBjaTsKPiArCXUzMiBoZWFkZXJfdHlwZTsKPiArCj4g KwloZWFkZXJfdHlwZSA9IG1vYml2ZWlsX2Nzcl9yZWFkYihtdl9wY2ksIFBDSV9IRUFERVJfVFlQ RSk7Cj4gKwloZWFkZXJfdHlwZSAmPSAweDdmOwo+ICsKPiArCXJldHVybiBoZWFkZXJfdHlwZSA9 PSBQQ0lfSEVBREVSX1RZUEVfQlJJREdFOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50IGxzX3BjaWVf ZzRfbGlua191cChzdHJ1Y3QgbW9iaXZlaWxfcGNpZSAqcGNpKQo+ICt7Cj4gKwlzdHJ1Y3QgbHNf cGNpZV9nNCAqcGNpZSA9IHRvX2xzX3BjaWVfZzQocGNpKTsKPiArCXUzMiBzdGF0ZTsKPiArCj4g KwlzdGF0ZSA9IGxzX3BjaWVfZzRfcGZfcmVhZGwocGNpZSwgUENJRV9QRl9EQkcpOwo+ICsJc3Rh dGUgPQlzdGF0ZSAmIFBGX0RCR19MVFNTTV9NQVNLOwo+ICsKPiArCWlmIChzdGF0ZSA9PSBQRl9E QkdfTFRTU01fTDApCj4gKwkJcmV0dXJuIDE7Cj4gKwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4g K3N0YXRpYyB2b2lkIGxzX3BjaWVfZzRfZGlzYWJsZV9pbnRlcnJ1cHQoc3RydWN0IGxzX3BjaWVf ZzQgKnBjaWUpCj4gK3sKPiArCXN0cnVjdCBtb2JpdmVpbF9wY2llICptdl9wY2kgPSAmcGNpZS0+ cGNpOwo+ICsKPiArCW1vYml2ZWlsX2Nzcl93cml0ZWwobXZfcGNpLCAwLCBQQUJfSU5UUF9BTUJB X01JU0NfRU5CKTsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQgbHNfcGNpZV9nNF9lbmFibGVfaW50 ZXJydXB0KHN0cnVjdCBsc19wY2llX2c0ICpwY2llKQo+ICt7Cj4gKwlzdHJ1Y3QgbW9iaXZlaWxf cGNpZSAqbXZfcGNpID0gJnBjaWUtPnBjaTsKPiArCXUzMiB2YWw7Cj4gKwo+ICsJLyogQ2xlYXIg dGhlIGludGVycnVwdCBzdGF0dXMgKi8KPiArCW1vYml2ZWlsX2Nzcl93cml0ZWwobXZfcGNpLCAw eGZmZmZmZmZmLCBQQUJfSU5UUF9BTUJBX01JU0NfU1RBVCk7Cj4gKwo+ICsJdmFsID0gUEFCX0lO VFBfSU5UWF9NQVNLIHwgUEFCX0lOVFBfTVNJIHwgUEFCX0lOVFBfUkVTRVQgfAo+ICsJICAgICAg UEFCX0lOVFBfUENJRV9VRSB8IFBBQl9JTlRQX0lFX1BNUkVESSB8IFBBQl9JTlRQX0lFX0VDOwo+ ICsJbW9iaXZlaWxfY3NyX3dyaXRlbChtdl9wY2ksIHZhbCwgUEFCX0lOVFBfQU1CQV9NSVNDX0VO Qik7Cj4gK30KPiArCj4gK3N0YXRpYyB2b2lkIGxzX3BjaWVfZzRfcmVpbml0X2h3KHN0cnVjdCBs c19wY2llX2c0ICpwY2llKQo+ICt7Cj4gKwlzdHJ1Y3QgbW9iaXZlaWxfcGNpZSAqbXZfcGNpID0g JnBjaWUtPnBjaTsKPiArCXN0cnVjdCBkZXZpY2UgKmRldiA9ICZtdl9wY2ktPnBkZXYtPmRldjsK PiArCXUzMiB2YWwsIGFjdF9zdGF0Owo+ICsJaW50IHRvID0gMTAwOwo+ICsKPiArCS8qIFBvbGwg Zm9yIHBhYl9jc2JfcmVzZXQgdG8gc2V0IGFuZCBQQUIgYWN0aXZpdHkgdG8gY2xlYXIgKi8KPiAr CWRvIHsKPiArCQl1c2xlZXBfcmFuZ2UoMTAsIDE1KTsKPiArCQl2YWwgPSBsc19wY2llX2c0X3Bm X3JlYWRsKHBjaWUsIFBDSUVfUEZfSU5UX1NUQVQpOwo+ICsJCWFjdF9zdGF0ID0gbW9iaXZlaWxf Y3NyX3JlYWRsKG12X3BjaSwgUEFCX0FDVElWSVRZX1NUQVQpOwo+ICsJfSB3aGlsZSAoKCh2YWwg JiBQRl9JTlRfU1RBVF9QQUJSU1QpID09IDAgfHwgYWN0X3N0YXQpICYmIHRvLS0pOwo+ICsJaWYg KHRvIDwgMCkgewo+ICsJCWRldl9lcnIoZGV2LCAiUG9sbCBQQUJSU1QmUEFCQUNUIHRpbWVvdXRc biIpOwo+ICsJCXJldHVybjsKCklmIGEgdGltZW91dCBoYXBwZW5zIGhlcmUgLSB0aGUgY2FsbGVy IGhhcyBubyBpZGVhIHRoaXMgaGFzIGhhcHBlbmVkCmFuZCB5ZXQgdGhlIGZvbGxvd2luZyB3b3Jr IGRvZXNuJ3QgZ2V0IGRvbmUuIElzbid0IHRoaXMgYSBwcm9ibGVtPwoKPiArCX0KPiArCj4gKwkv KiBjbGVhciBQRVhfUkVTRVQgYml0IGluIFBFWF9QRjBfREJHIHJlZ2lzdGVyICovCj4gKwl2YWwg PSBsc19wY2llX2c0X3BmX3JlYWRsKHBjaWUsIFBDSUVfUEZfREJHKTsKPiArCXZhbCB8PSBQRl9E QkdfV0U7Cj4gKwlsc19wY2llX2c0X3BmX3dyaXRlbChwY2llLCBQQ0lFX1BGX0RCRywgdmFsKTsK PiArCj4gKwl2YWwgPSBsc19wY2llX2c0X3BmX3JlYWRsKHBjaWUsIFBDSUVfUEZfREJHKTsKPiAr CXZhbCB8PSBQRl9EQkdfUEFCUjsKPiArCWxzX3BjaWVfZzRfcGZfd3JpdGVsKHBjaWUsIFBDSUVf UEZfREJHLCB2YWwpOwo+ICsKPiArCXZhbCA9IGxzX3BjaWVfZzRfcGZfcmVhZGwocGNpZSwgUENJ RV9QRl9EQkcpOwo+ICsJdmFsICY9IH5QRl9EQkdfV0U7Cj4gKwlsc19wY2llX2c0X3BmX3dyaXRl bChwY2llLCBQQ0lFX1BGX0RCRywgdmFsKTsKPiArCj4gKwltb2JpdmVpbF9ob3N0X2luaXQobXZf cGNpLCB0cnVlKTsKCkNhbiBtb2JpdmVpbF9ob3N0X2luaXQgZmFpbD8KCj4gKwo+ICsJdG8gPSAx MDA7Cj4gKwl3aGlsZSAoIWxzX3BjaWVfZzRfbGlua191cChtdl9wY2kpICYmIHRvLS0pCj4gKwkJ dXNsZWVwX3JhbmdlKDIwMCwgMjUwKTsKPiArCWlmICh0byA8IDApCj4gKwkJZGV2X2VycihkZXYs ICJQQ0llIGxpbmsgdHJhaW5pbmcgdGltZW91dFxuIik7Cj4gK30KPiArCj4gK3N0YXRpYyBpcnFy ZXR1cm5fdCBsc19wY2llX2c0X2lzcihpbnQgaXJxLCB2b2lkICpkZXZfaWQpCj4gK3sKPiArCXN0 cnVjdCBsc19wY2llX2c0ICpwY2llID0gKHN0cnVjdCBsc19wY2llX2c0ICopZGV2X2lkOwo+ICsJ c3RydWN0IG1vYml2ZWlsX3BjaWUgKm12X3BjaSA9ICZwY2llLT5wY2k7Cj4gKwl1MzIgdmFsOwo+ ICsKPiArCXZhbCA9IG1vYml2ZWlsX2Nzcl9yZWFkbChtdl9wY2ksIFBBQl9JTlRQX0FNQkFfTUlT Q19TVEFUKTsKPiArCWlmICghdmFsKQo+ICsJCXJldHVybiBJUlFfTk9ORTsKPiArCj4gKwlpZiAo dmFsICYgUEFCX0lOVFBfUkVTRVQpIHsKCkNhbiB5b3UgZXhwbGFpbiB3aHkgdGhpcyBpcyBuZWVk ZWQgKHBlcmhhcHMgYWxzbyBpbiB0aGUgY292ZXIgbGV0dGVyKT8KCj4gKwkJbHNfcGNpZV9nNF9k aXNhYmxlX2ludGVycnVwdChwY2llKTsKPiArCQlzY2hlZHVsZV9kZWxheWVkX3dvcmsoJnBjaWUt PmR3b3JrLCBtc2Vjc190b19qaWZmaWVzKDEpKTsKPiArCX0KPiArCj4gKwltb2JpdmVpbF9jc3Jf d3JpdGVsKG12X3BjaSwgdmFsLCBQQUJfSU5UUF9BTUJBX01JU0NfU1RBVCk7Cj4gKwo+ICsJcmV0 dXJuIElSUV9IQU5ETEVEOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50IGxzX3BjaWVfZzRfaW50ZXJy dXB0X2luaXQoc3RydWN0IG1vYml2ZWlsX3BjaWUgKm12X3BjaSkKPiArewo+ICsJc3RydWN0IGxz X3BjaWVfZzQgKnBjaWUgPSB0b19sc19wY2llX2c0KG12X3BjaSk7Cj4gKwlzdHJ1Y3QgcGxhdGZv cm1fZGV2aWNlICpwZGV2ID0gbXZfcGNpLT5wZGV2Owo+ICsJc3RydWN0IGRldmljZSAqZGV2ID0g JnBkZXYtPmRldjsKPiArCWludCByZXQ7Cj4gKwo+ICsJcGNpZS0+aXJxID0gcGxhdGZvcm1fZ2V0 X2lycV9ieW5hbWUocGRldiwgImludHIiKTsKPiArCWlmIChwY2llLT5pcnEgPCAwKSB7Cj4gKwkJ ZGV2X2VycihkZXYsICJDYW4ndCBnZXQgJ2ludHInIElSUSwgZXJybm8gPSAlZFxuIiwgcGNpZS0+ aXJxKTsKPiArCQlyZXR1cm4gcGNpZS0+aXJxOwo+ICsJfQo+ICsJcmV0ID0gZGV2bV9yZXF1ZXN0 X2lycShkZXYsIHBjaWUtPmlycSwgbHNfcGNpZV9nNF9pc3IsCj4gKwkJCSAgICAgICBJUlFGX1NI QVJFRCwgcGRldi0+bmFtZSwgcGNpZSk7Cj4gKwlpZiAocmV0KSB7Cj4gKwkJZGV2X2VycihkZXYs ICJDYW4ndCByZWdpc3RlciBQQ0llIElSUSwgZXJybm8gPSAlZFxuIiwgcmV0KTsKPiArCQlyZXR1 cm4gIHJldDsKPiArCX0KPiArCj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQg bHNfcGNpZV9nNF9yZXNldChzdHJ1Y3Qgd29ya19zdHJ1Y3QgKndvcmspCj4gK3sKPiArCXN0cnVj dCBkZWxheWVkX3dvcmsgKmR3b3JrID0gY29udGFpbmVyX29mKHdvcmssIHN0cnVjdCBkZWxheWVk X3dvcmssCj4gKwkJCQkJCSAgd29yayk7Cj4gKwlzdHJ1Y3QgbHNfcGNpZV9nNCAqcGNpZSA9IGNv bnRhaW5lcl9vZihkd29yaywgc3RydWN0IGxzX3BjaWVfZzQsIGR3b3JrKTsKPiArCXN0cnVjdCBt b2JpdmVpbF9wY2llICptdl9wY2kgPSAmcGNpZS0+cGNpOwo+ICsJdTE2IGN0cmw7Cj4gKwo+ICsJ Y3RybCA9IG1vYml2ZWlsX2Nzcl9yZWFkdyhtdl9wY2ksIFBDSV9CUklER0VfQ09OVFJPTCk7Cj4g KwljdHJsICY9IH5QQ0lfQlJJREdFX0NUTF9CVVNfUkVTRVQ7Cj4gKwltb2JpdmVpbF9jc3Jfd3Jp dGV3KG12X3BjaSwgY3RybCwgUENJX0JSSURHRV9DT05UUk9MKTsKPiArCWxzX3BjaWVfZzRfcmVp bml0X2h3KHBjaWUpOwo+ICsJbHNfcGNpZV9nNF9lbmFibGVfaW50ZXJydXB0KHBjaWUpOwo+ICt9 Cj4gKwo+ICtzdGF0aWMgc3RydWN0IG1vYml2ZWlsX3JwX29wcyBsc19wY2llX2c0X3JwX29wcyA9 IHsKPiArCS5pbnRlcnJ1cHRfaW5pdCA9IGxzX3BjaWVfZzRfaW50ZXJydXB0X2luaXQsCj4gK307 Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IG1vYml2ZWlsX3BhYl9vcHMgbHNfcGNpZV9nNF9w YWJfb3BzID0gewo+ICsJLmxpbmtfdXAgPSBsc19wY2llX2c0X2xpbmtfdXAsCj4gK307Cj4gKwo+ ICtzdGF0aWMgaW50IF9faW5pdCBsc19wY2llX2c0X3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZp Y2UgKnBkZXYpCj4gK3sKPiArCXN0cnVjdCBkZXZpY2UgKmRldiA9ICZwZGV2LT5kZXY7Cj4gKwlz dHJ1Y3QgcGNpX2hvc3RfYnJpZGdlICpicmlkZ2U7Cj4gKwlzdHJ1Y3QgbW9iaXZlaWxfcGNpZSAq bXZfcGNpOwo+ICsJc3RydWN0IGxzX3BjaWVfZzQgKnBjaWU7Cj4gKwlzdHJ1Y3QgZGV2aWNlX25v ZGUgKm5wID0gZGV2LT5vZl9ub2RlOwo+ICsJaW50IHJldDsKPiArCj4gKwlpZiAoIW9mX3BhcnNl X3BoYW5kbGUobnAsICJtc2ktcGFyZW50IiwgMCkpIHsKPiArCQlkZXZfZXJyKGRldiwgIkZhaWxl ZCB0byBmaW5kIG1zaS1wYXJlbnRcbiIpOwo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsJfQo+ICsK PiArCWJyaWRnZSA9IGRldm1fcGNpX2FsbG9jX2hvc3RfYnJpZGdlKGRldiwgc2l6ZW9mKCpwY2ll KSk7Cj4gKwlpZiAoIWJyaWRnZSkKPiArCQlyZXR1cm4gLUVOT01FTTsKPiArCj4gKwlwY2llID0g cGNpX2hvc3RfYnJpZGdlX3ByaXYoYnJpZGdlKTsKPiArCW12X3BjaSA9ICZwY2llLT5wY2k7Cj4g Kwo+ICsJbXZfcGNpLT5wZGV2ID0gcGRldjsKPiArCW12X3BjaS0+b3BzID0gJmxzX3BjaWVfZzRf cGFiX29wczsKPiArCW12X3BjaS0+cnAub3BzID0gJmxzX3BjaWVfZzRfcnBfb3BzOwo+ICsJbXZf cGNpLT5ycC5icmlkZ2UgPSBicmlkZ2U7Cj4gKwo+ICsJcGxhdGZvcm1fc2V0X2RydmRhdGEocGRl diwgcGNpZSk7Cj4gKwo+ICsJSU5JVF9ERUxBWUVEX1dPUksoJnBjaWUtPmR3b3JrLCBsc19wY2ll X2c0X3Jlc2V0KTsKPiArCj4gKwlyZXQgPSBtb2JpdmVpbF9wY2llX2hvc3RfcHJvYmUobXZfcGNp KTsKPiArCWlmIChyZXQpIHsKPiArCQlkZXZfZXJyKGRldiwgIkZhaWwgdG8gcHJvYmVcbiIpOwo+ ICsJCXJldHVybiAgcmV0Owo+ICsJfQo+ICsKPiArCWlmICghbHNfcGNpZV9nNF9pc19icmlkZ2Uo cGNpZSkpCgpJcyB0aGlzIGEgY2hlY2sgdGhhdCBjb3VsZCBhcHBseSB0byBhbGwgaG9zdCBicmlk Z2UgZHJpdmVycyBhbmQgdGh1cyBsaXZlCmluIG1vYml2ZWlsX3BjaWVfaG9zdF9wcm9iZT8KCj4g KwkJcmV0dXJuIC1FTk9ERVY7Cj4gKwo+ICsJbHNfcGNpZV9nNF9lbmFibGVfaW50ZXJydXB0KHBj aWUpOwoKSXMgdGhlcmUgYW4gaXNzdWUgaGVyZSBpbiB0aGF0IHdlIGVuYWJsZSBpbnRlcnJ1cHRz ICphZnRlciogdGVsbGluZyB0aGUga2VybmVsCmFib3V0IG91ciBjb250cm9sbGVyPyAoU2FtZSBh cHBsaWVzIGZvciBiYWlsaW5nIGlmIHRoZSBJUCBpc24ndCBhIGJyaWRnZSkuCgpUaGFua3MsCgpB bmRyZXcgTXVycmF5Cgo+ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgY29uc3Qg c3RydWN0IG9mX2RldmljZV9pZCBsc19wY2llX2c0X29mX21hdGNoW10gPSB7Cj4gKwl7IC5jb21w YXRpYmxlID0gImZzbCxseDIxNjBhLXBjaWUiLCB9LAo+ICsJeyB9LAo+ICt9Owo+ICsKPiArc3Rh dGljIHN0cnVjdCBwbGF0Zm9ybV9kcml2ZXIgbHNfcGNpZV9nNF9kcml2ZXIgPSB7Cj4gKwkuZHJp dmVyID0gewo+ICsJCS5uYW1lID0gImxheWVyc2NhcGUtcGNpZS1nZW40IiwKPiArCQkub2ZfbWF0 Y2hfdGFibGUgPSBsc19wY2llX2c0X29mX21hdGNoLAo+ICsJCS5zdXBwcmVzc19iaW5kX2F0dHJz ID0gdHJ1ZSwKPiArCX0sCj4gK307Cj4gKwo+ICtidWlsdGluX3BsYXRmb3JtX2RyaXZlcl9wcm9i ZShsc19wY2llX2c0X2RyaXZlciwgbHNfcGNpZV9nNF9wcm9iZSk7Cj4gZGlmZiAtLWdpdCBhL2Ry aXZlcnMvcGNpL2NvbnRyb2xsZXIvbW9iaXZlaWwvcGNpZS1tb2JpdmVpbC5oIGIvZHJpdmVycy9w Y2kvY29udHJvbGxlci9tb2JpdmVpbC9wY2llLW1vYml2ZWlsLmgKPiBpbmRleCA3NTBhN2ZkOTVi YzEuLmM1N2E2OGQyYmFjNCAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL21v Yml2ZWlsL3BjaWUtbW9iaXZlaWwuaAo+ICsrKyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvbW9i aXZlaWwvcGNpZS1tb2JpdmVpbC5oCj4gQEAgLTQzLDYgKzQzLDggQEAKPiAgI2RlZmluZSAgUEFH RV9MT19NQVNLCQkJMHgzZmYKPiAgI2RlZmluZSAgUEFHRV9TRUxfT0ZGU0VUX1NISUZUCQkxMAo+ ICAKPiArI2RlZmluZSBQQUJfQUNUSVZJVFlfU1RBVAkJMHg4MWMKPiArCj4gICNkZWZpbmUgUEFC X0FYSV9QSU9fQ1RSTAkJMHgwODQwCj4gICNkZWZpbmUgIEFQSU9fRU5fTUFTSwkJCTB4Zgo+ICAK PiBAQCAtNTEsOCArNTMsMTggQEAKPiAgCj4gICNkZWZpbmUgUEFCX0lOVFBfQU1CQV9NSVNDX0VO QgkJMHgwYjBjCj4gICNkZWZpbmUgUEFCX0lOVFBfQU1CQV9NSVNDX1NUQVQJCTB4MGIxYwo+IC0j ZGVmaW5lICBQQUJfSU5UUF9JTlRYX01BU0sJCTB4MDFlMAo+IC0jZGVmaW5lICBQQUJfSU5UUF9N U0lfTUFTSwkJMHg4Cj4gKyNkZWZpbmUgIFBBQl9JTlRQX1JFU0VUCQkJQklUKDEpCj4gKyNkZWZp bmUgIFBBQl9JTlRQX01TSQkJCUJJVCgzKQo+ICsjZGVmaW5lICBQQUJfSU5UUF9JTlRBCQkJQklU KDUpCj4gKyNkZWZpbmUgIFBBQl9JTlRQX0lOVEIJCQlCSVQoNikKPiArI2RlZmluZSAgUEFCX0lO VFBfSU5UQwkJCUJJVCg3KQo+ICsjZGVmaW5lICBQQUJfSU5UUF9JTlRECQkJQklUKDgpCj4gKyNk ZWZpbmUgIFBBQl9JTlRQX1BDSUVfVUUJCUJJVCg5KQo+ICsjZGVmaW5lICBQQUJfSU5UUF9JRV9Q TVJFREkJCUJJVCgyOSkKPiArI2RlZmluZSAgUEFCX0lOVFBfSUVfRUMJCQlCSVQoMzApCj4gKyNk ZWZpbmUgIFBBQl9JTlRQX01TSV9NQVNLCQlQQUJfSU5UUF9NU0kKPiArI2RlZmluZSAgUEFCX0lO VFBfSU5UWF9NQVNLCQkoUEFCX0lOVFBfSU5UQSB8IFBBQl9JTlRQX0lOVEIgfFwKPiArCQkJCQlQ QUJfSU5UUF9JTlRDIHwgUEFCX0lOVFBfSU5URCkKPiAgCj4gICNkZWZpbmUgUEFCX0FYSV9BTUFQ X0NUUkwod2luKQkJUEFCX1JFR19BRERSKDB4MGJhMCwgd2luKQo+ICAjZGVmaW5lICBXSU5fRU5B QkxFX1NISUZUCQkwCj4gLS0gCj4gMi4xNy4xCj4gCgpfX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51 eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5v cmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==