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[66.175.222.153]) by smtp.gmail.com with ESMTPSA id i127sm15559616pfe.54.2020.01.13.06.58.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 13 Jan 2020 06:58:12 -0800 (PST) Date: Mon, 13 Jan 2020 22:58:03 +0800 From: Leo Yan To: Suzuki Kuruppassery Poulose Cc: James Clark , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, nd@arm.com, Mathieu Poirier , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Igor Lubashev Subject: Re: [PATCH] perf tools: Fix bug when recording SPE and non SPE events Message-ID: <20200113145803.GB10620@leoy-ThinkPad-X240s> References: <20191220110525.30131-1-james.clark@arm.com> <20191223034852.GB3981@leoy-ThinkPad-X240s> <20200113141751.GA10620@leoy-ThinkPad-X240s> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200113141751.GA10620@leoy-ThinkPad-X240s> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 13, 2020 at 10:17:51PM +0800, Leo Yan wrote: [...] > > > On Fri, Dec 20, 2019 at 11:05:25AM +0000, James Clark wrote: > > > > This patch fixes an issue when non Arm SPE events are specified after an > > > > Arm SPE event. In that case, perf will exit with an error code and not > > > > produce a record file. This is because a loop index is used to store the > > > > location of the relevant Arm SPE PMU, but if non SPE PMUs follow, that > > > > index will be overwritten. Fix this issue by saving the PMU into a > > > > variable instead of using the index, and also add an error message. > > > > > > > > Before the fix: > > > > ./perf record -e arm_spe/ts_enable=1/ -e branch-misses ls; echo $? > > > > 237 > > > > > > > > After the fix: > > > > ./perf record -e arm_spe/ts_enable=1/ -e branch-misses ls; echo $? > > > > ... > > > > 0 > > > > > > Just bring up a question related with PMU event registration. Let's > > > see the DT binding in arch/arm64/boot/dts/arm/fvp-base-revc.dts: > > > > > > spe-pmu { > > > compatible = "arm,statistical-profiling-extension-v1"; > > > interrupts = ; > > > }; > > > > > > > > > Now SPE registers PMU event for every CPU; seem to me, though SPE is an > > > > Do you mean "SPE PMU" here ? SPE is different from ETM, where the trace > > data is micro-architecture dependent. And thus you cannot mix the trace > > on different CPUs with different micro-archs. > > Understood that SPE is micro-architecture dependent. Maybe SPE is more general than we think :) Since SPE is defined in ARMv8 architecture reference manual (ARM DDI 0487D.a); should SPE trace data format is unified and defined in Chapter D9 "Statistical Profiling Extension Sample Record Specification"? Thanks, Leo