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Received: from MN2PR12MB3309.namprd12.prod.outlook.com (20.179.83.157) by MN2PR12MB3263.namprd12.prod.outlook.com (20.179.80.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2623.13; Tue, 14 Jan 2020 09:36:49 +0000 Received: from MN2PR12MB3309.namprd12.prod.outlook.com ([fe80::f945:5c4c:9c3f:930a]) by MN2PR12MB3309.namprd12.prod.outlook.com ([fe80::f945:5c4c:9c3f:930a%6]) with mapi id 15.20.2623.015; Tue, 14 Jan 2020 09:36:49 +0000 Date: Tue, 14 Jan 2020 17:36:41 +0800 From: Huang Rui To: "amd-gfx@lists.freedesktop.org" , "Kuehling, Felix" Subject: Re: [PATCH 1/5] drm/amdgpu: only set cp active field for kiq queue Message-ID: <20200114093640.GA20112@jenkins-Celadon-RN> References: <1578638233-9357-1-git-send-email-ray.huang@amd.com> Content-Disposition: inline In-Reply-To: <1578638233-9357-1-git-send-email-ray.huang@amd.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-ClientProxiedBy: HK2PR06CA0022.apcprd06.prod.outlook.com (2603:1096:202:2e::34) To MN2PR12MB3309.namprd12.prod.outlook.com (2603:10b6:208:106::29) MIME-Version: 1.0 Received: from jenkins-Celadon-RN (180.167.199.189) by HK2PR06CA0022.apcprd06.prod.outlook.com (2603:1096:202:2e::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2623.9 via Frontend Transport; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Ping~ On Fri, Jan 10, 2020 at 02:37:09PM +0800, Huang, Ray wrote: > The mec ucode will set the CP_HQD_ACTIVE bit while the queue is mapped by > MAP_QUEUES packet. So we only need set cp active field for kiq queue. > > Signed-off-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 +++++-- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 7 +++++-- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++++-- > 3 files changed, 15 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 5b05334..22c69d8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -3323,8 +3323,11 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) > tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); > mqd->cp_hqd_ib_control = tmp; > > - /* activate the queue */ > - mqd->cp_hqd_active = 1; > + /* map_queues packet doesn't need activate the queue, > + * so only kiq need set this field. > + */ > + if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) > + mqd->cp_hqd_active = 1; > > return 0; > } > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 8b9f440..306ee61 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -4558,8 +4558,11 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) > mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM); > mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES); > > - /* activate the queue */ > - mqd->cp_hqd_active = 1; > + /* map_queues packet doesn't need activate the queue, > + * so only kiq need set this field. > + */ > + if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) > + mqd->cp_hqd_active = 1; > > return 0; > } > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 45328f9..e29818b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -3313,8 +3313,11 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) > tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); > mqd->cp_hqd_ib_control = tmp; > > - /* activate the queue */ > - mqd->cp_hqd_active = 1; > + /* map_queues packet doesn't need activate the queue, > + * so only kiq need set this field. > + */ > + if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) > + mqd->cp_hqd_active = 1; > > return 0; > } > -- > 2.7.4 > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx