From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85B93C33C9E for ; Tue, 14 Jan 2020 17:41:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 613822072B for ; Tue, 14 Jan 2020 17:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728587AbgANRlv (ORCPT ); Tue, 14 Jan 2020 12:41:51 -0500 Received: from foss.arm.com ([217.140.110.172]:55684 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726053AbgANRlv (ORCPT ); Tue, 14 Jan 2020 12:41:51 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D5301396; Tue, 14 Jan 2020 09:41:48 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3C8493F68E; Tue, 14 Jan 2020 09:41:47 -0800 (PST) Date: Tue, 14 Jan 2020 17:41:44 +0000 From: Andre Przywara To: Radhey Shyam Pandey Cc: "David S . Miller" , Michal Simek , Robert Hancock , "netdev@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 12/14] net: axienet: Autodetect 64-bit DMA capability Message-ID: <20200114174144.6e8c6387@donnerap.cambridge.arm.com> In-Reply-To: References: <20200110115415.75683-1-andre.przywara@arm.com> <20200110115415.75683-13-andre.przywara@arm.com> Organization: ARM X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 14 Jan 2020 17:03:41 +0000 Radhey Shyam Pandey wrote: Hi, > > -----Original Message----- > > From: Andre Przywara > > Sent: Friday, January 10, 2020 5:24 PM > > To: David S . Miller ; Radhey Shyam Pandey > > > > Cc: Michal Simek ; Robert Hancock > > ; netdev@vger.kernel.org; linux-arm- > > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > > Subject: [PATCH 12/14] net: axienet: Autodetect 64-bit DMA capability > > > > When newer revisions of the Axienet IP are configured for a 64-bit bus, > I assume in design axidma address width is set to 64-bits. So I wrote "64-bit bus" here, but really meant: "address bus wider than 32 bits". In our case it's set to 40 bits, because that's how wide the other busses in the system are. And we have memory from 2GB to 4GB, and from 34GB till 40GB, but not in-between (VExpress/Juno memory layout). > If not, please provide an overview of the design connections. The exact parameter name from PG021 is: "Address Width (32-64) / c_addr_width". > > we *need* to write to the MSB part of the an address registers, > > otherwise the IP won't recognise this as a DMA start condition. > > This is even true when the actual DMA address comes from the lower 4 GB. > > > > To autodetect this configuration, at probe time we write all 1's to such > Is reading address width axidma IP user parameter(c_addr_width) from > the design not sufficient to detect configured bus width? What do you mean by that? Reading from where? Is there a way to access those parameters from a running system? Cheers, Andre. > > an MSB register, and see if any bits stick. If this is configured for a > > 32-bit bus, those MSB registers are RES0, so reading back 0 indicates > > that no MSB writes are necessary. > > On the other hands reading anything other than 0 indicated the need to > > write the MSB registers, so we set the respective flag. > > > > For now this leaves the actual DMA mask at 32-bit, as we can't reliably > > detect the actually wired number of address lines beyond 32. > > > > Signed-off-by: Andre Przywara > > --- > > drivers/net/ethernet/xilinx/xilinx_axienet.h | 1 + > > .../net/ethernet/xilinx/xilinx_axienet_main.c | 27 +++++++++++++++++++ > > 2 files changed, 28 insertions(+) > > > > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h > > b/drivers/net/ethernet/xilinx/xilinx_axienet.h > > index 4aea4c23d3bb..4feaaa02819c 100644 > > --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h > > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h > > @@ -161,6 +161,7 @@ > > #define XAE_FCC_OFFSET 0x0000040C /* Flow Control > > Configuration */ > > #define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode > > configuration */ > > #define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII > > configuration */ > > +#define XAE_ID_OFFSET 0x000004F8 /* Identification register > > */ > > #define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management > > Config */ > > #define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management > > Control */ > > #define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write > > Data */ > > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > index 133f088d797e..f7f593df0c11 100644 > > --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > @@ -151,6 +151,9 @@ static void axienet_dma_out_addr(struct axienet_local > > *lp, off_t reg, > > dma_addr_t addr) > > { > > axienet_dma_out32(lp, reg, lower_32_bits(addr)); > > + > > + if (lp->features & XAE_FEATURE_DMA_64BIT) > > + axienet_dma_out32(lp, reg + 4, upper_32_bits(addr)); > > } > > > > static void desc_set_phys_addr(struct axienet_local *lp, dma_addr_t addr, > > @@ -1934,6 +1937,30 @@ static int axienet_probe(struct platform_device > > *pdev) > > goto free_netdev; > > } > > > > + /* > > + * Autodetect the need for 64-bit DMA pointers. > > + * When the IP is configured for a bus width bigger than 32 bits, > > + * writing the MSB registers is mandatory, even if they are all 0. > > + * We can detect this case by writing all 1's to one such register > > + * and see if that sticks: when the IP is configured for 32 bits > > + * only, those registers are RES0. > > + * Those MSB registers were introduced in IP v7.1, which we check first. > > + */ > > + if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) { > > + void __iomem *desc = lp->dma_regs + > > XAXIDMA_TX_CDESC_OFFSET + 4; > > + > > + iowrite32(0x0, desc); > > + if (ioread32(desc) == 0) { /* sanity check */ > > + iowrite32(0xffffffff, desc); > > + if (ioread32(desc) > 0) { > > + lp->features |= XAE_FEATURE_DMA_64BIT; > > + dev_info(&pdev->dev, > > + "autodetected 64-bit DMA range\n"); > > + } > > + iowrite32(0x0, desc); > > + } > > + } > > + > > /* Check for Ethernet core IRQ (optional) */ > > if (lp->eth_irq <= 0) > > dev_info(&pdev->dev, "Ethernet core IRQ not defined\n"); > > -- > > 2.17.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7149BC47409 for ; Tue, 14 Jan 2020 17:41:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4BE5624658 for ; Tue, 14 Jan 2020 17:41:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="aBYc5UBq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4BE5624658 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=scfRcDdVwXWDBchcF23QuvRsLUyhfi/FSxDMqzBy3W8=; b=aBYc5UBq9S38/u ZXnBcdsHJUUroIrdviEGIKoswM3uF9n5UZTS7J0lfT24EBopP69yoFKULOJ2evC7EjhchLRkSjIfJ peLCydWDBe5lnl4PKS0cXE7fmI9jbVcUU/vJBiWu4absd6e3qz/0CmJ+fyA5buYfhWOM24lOlRCKf VNX6XEWycPZ4N0Vc9UeEl/whp1HVLzV1j7aJPvhEnT+BzZ0Nh1VKps5G3pxf7468PTU/nH1OddDsR iav3eWpSDSJGv7y8Hz2pJnkA9sf05DtZxiaNMWHMZSixZYlosLyzmaVPPZ0CBUxulh/Of3/NiouZo NP8SRGqJArwjqt5TCIfQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1irQCP-00040H-KL; Tue, 14 Jan 2020 17:41:53 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1irQCL-0003zv-BA for linux-arm-kernel@lists.infradead.org; Tue, 14 Jan 2020 17:41:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D5301396; Tue, 14 Jan 2020 09:41:48 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3C8493F68E; Tue, 14 Jan 2020 09:41:47 -0800 (PST) Date: Tue, 14 Jan 2020 17:41:44 +0000 From: Andre Przywara To: Radhey Shyam Pandey Subject: Re: [PATCH 12/14] net: axienet: Autodetect 64-bit DMA capability Message-ID: <20200114174144.6e8c6387@donnerap.cambridge.arm.com> In-Reply-To: References: <20200110115415.75683-1-andre.przywara@arm.com> <20200110115415.75683-13-andre.przywara@arm.com> Organization: ARM X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200114_094149_467240_8E29655D X-CRM114-Status: GOOD ( 26.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Hancock , Michal Simek , "David S . Miller" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 14 Jan 2020 17:03:41 +0000 Radhey Shyam Pandey wrote: Hi, > > -----Original Message----- > > From: Andre Przywara > > Sent: Friday, January 10, 2020 5:24 PM > > To: David S . Miller ; Radhey Shyam Pandey > > > > Cc: Michal Simek ; Robert Hancock > > ; netdev@vger.kernel.org; linux-arm- > > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > > Subject: [PATCH 12/14] net: axienet: Autodetect 64-bit DMA capability > > > > When newer revisions of the Axienet IP are configured for a 64-bit bus, > I assume in design axidma address width is set to 64-bits. So I wrote "64-bit bus" here, but really meant: "address bus wider than 32 bits". In our case it's set to 40 bits, because that's how wide the other busses in the system are. And we have memory from 2GB to 4GB, and from 34GB till 40GB, but not in-between (VExpress/Juno memory layout). > If not, please provide an overview of the design connections. The exact parameter name from PG021 is: "Address Width (32-64) / c_addr_width". > > we *need* to write to the MSB part of the an address registers, > > otherwise the IP won't recognise this as a DMA start condition. > > This is even true when the actual DMA address comes from the lower 4 GB. > > > > To autodetect this configuration, at probe time we write all 1's to such > Is reading address width axidma IP user parameter(c_addr_width) from > the design not sufficient to detect configured bus width? What do you mean by that? Reading from where? Is there a way to access those parameters from a running system? Cheers, Andre. > > an MSB register, and see if any bits stick. If this is configured for a > > 32-bit bus, those MSB registers are RES0, so reading back 0 indicates > > that no MSB writes are necessary. > > On the other hands reading anything other than 0 indicated the need to > > write the MSB registers, so we set the respective flag. > > > > For now this leaves the actual DMA mask at 32-bit, as we can't reliably > > detect the actually wired number of address lines beyond 32. > > > > Signed-off-by: Andre Przywara > > --- > > drivers/net/ethernet/xilinx/xilinx_axienet.h | 1 + > > .../net/ethernet/xilinx/xilinx_axienet_main.c | 27 +++++++++++++++++++ > > 2 files changed, 28 insertions(+) > > > > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h > > b/drivers/net/ethernet/xilinx/xilinx_axienet.h > > index 4aea4c23d3bb..4feaaa02819c 100644 > > --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h > > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h > > @@ -161,6 +161,7 @@ > > #define XAE_FCC_OFFSET 0x0000040C /* Flow Control > > Configuration */ > > #define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode > > configuration */ > > #define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII > > configuration */ > > +#define XAE_ID_OFFSET 0x000004F8 /* Identification register > > */ > > #define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management > > Config */ > > #define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management > > Control */ > > #define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write > > Data */ > > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > index 133f088d797e..f7f593df0c11 100644 > > --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > @@ -151,6 +151,9 @@ static void axienet_dma_out_addr(struct axienet_local > > *lp, off_t reg, > > dma_addr_t addr) > > { > > axienet_dma_out32(lp, reg, lower_32_bits(addr)); > > + > > + if (lp->features & XAE_FEATURE_DMA_64BIT) > > + axienet_dma_out32(lp, reg + 4, upper_32_bits(addr)); > > } > > > > static void desc_set_phys_addr(struct axienet_local *lp, dma_addr_t addr, > > @@ -1934,6 +1937,30 @@ static int axienet_probe(struct platform_device > > *pdev) > > goto free_netdev; > > } > > > > + /* > > + * Autodetect the need for 64-bit DMA pointers. > > + * When the IP is configured for a bus width bigger than 32 bits, > > + * writing the MSB registers is mandatory, even if they are all 0. > > + * We can detect this case by writing all 1's to one such register > > + * and see if that sticks: when the IP is configured for 32 bits > > + * only, those registers are RES0. > > + * Those MSB registers were introduced in IP v7.1, which we check first. > > + */ > > + if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) { > > + void __iomem *desc = lp->dma_regs + > > XAXIDMA_TX_CDESC_OFFSET + 4; > > + > > + iowrite32(0x0, desc); > > + if (ioread32(desc) == 0) { /* sanity check */ > > + iowrite32(0xffffffff, desc); > > + if (ioread32(desc) > 0) { > > + lp->features |= XAE_FEATURE_DMA_64BIT; > > + dev_info(&pdev->dev, > > + "autodetected 64-bit DMA range\n"); > > + } > > + iowrite32(0x0, desc); > > + } > > + } > > + > > /* Check for Ethernet core IRQ (optional) */ > > if (lp->eth_irq <= 0) > > dev_info(&pdev->dev, "Ethernet core IRQ not defined\n"); > > -- > > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel