From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F9D2C33CB3 for ; Wed, 15 Jan 2020 14:15:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 656952467E for ; Wed, 15 Jan 2020 14:15:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="I31EknCz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730197AbgAOOPC (ORCPT ); Wed, 15 Jan 2020 09:15:02 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:33239 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729615AbgAOONM (ORCPT ); Wed, 15 Jan 2020 09:13:12 -0500 Received: by mail-wr1-f65.google.com with SMTP id b6so15926881wrq.0 for ; Wed, 15 Jan 2020 06:13:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nWgJuKnKe2SBn73azCS8u4UiAG88rfUFNWE/ANlTpX0=; b=I31EknCzD3TH7Es/RpEGkKg1eeUwbESGqgoiUxv6yx7BRJW761w2kObfINWKdWsiz/ geYIDDnxuwLo6JlgBkJ/gY/ygWzRL/vU6bBsL5yf5ppFYHkt3FUXhnpdiymrQiklzonU BgYmELJVIjtkO4YRqCLkZpPZlXoEVDNmFJ2RZzw2yThBRrfcB4hk8hHtpx1T+X8TFT9L rNJXsiFi9+mJfIdELLw3OatJR1NvyXmn/smMRhP0JEZIhb43r05iD8ottHPxKWUz0KwV tG5TJWCE7MXUMZDbudzLyeGwbNsqg65Cdom26V4Se0RZJHb3TCLQt/28UaXCp+RafkSb bwoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nWgJuKnKe2SBn73azCS8u4UiAG88rfUFNWE/ANlTpX0=; b=gbt5GmsXr1wwxQELU/6lV228CywDy0k7WDpqKL2+psQddmQWo1ne9o/ROwownAiQ6b QajKk1S1KcB2FpZ8PctPuPd6e61NAj79rpk0t+DoFAVL02ym5tFlrz+b0WqaUlOC0tBP zeDiyLVN4YIklpP3QG5Mu60cewn/i48jxUHGJItnhDTzufXHtDJEMkLhlLemZJr81mVU Otzv+KxgTYfO5tr/cSqJDVMVs9QEHJMOD5JDsAWI5eXaKXuAMAYZVhXdIRFkN/y+EMBM PTIQp7KaXg8hqsWPXK1Irs+xBh2q5mvOoqFzwwoAN/xyZEzuU0lVsOixjzqRauT9QDs3 yizA== X-Gm-Message-State: APjAAAVofYFeWLcCLVGvnQDGWqoawV36S7ZNJLvIQ1fmvh0/u9khkwJ4 w2uYHCtft+kDPTB8l8vUZ+HE1busAUs= X-Google-Smtp-Source: APXvYqyU468zJql6OZKrz6H/3JbxwJjaJTcbgNPPhW1aN1w4uMkl7DYGnYit+BmPBPF2MrRCcROo5A== X-Received: by 2002:a5d:4481:: with SMTP id j1mr32580311wrq.348.1579097590717; Wed, 15 Jan 2020 06:13:10 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:10 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Jorge Ramirez-Ortiz , Jorge Ramirez-Ortiz , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH 04/19] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings Date: Wed, 15 Jan 2020 14:13:18 +0000 Message-Id: <20200115141333.1222676-5-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed phy controller embedded in QCS404. Based on Sriharsha Allenki's original definitions. [bod: converted to yaml format] Signed-off-by: Jorge Ramirez-Ortiz Cc: Jorge Ramirez-Ortiz Cc: Rob Herring Cc: Mark Rutland Cc: Bjorn Andersson Cc: Jorge Ramirez-Ortiz Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- .../devicetree/bindings/qcom,usb-ss.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/qcom,usb-ss.yaml diff --git a/Documentation/devicetree/bindings/qcom,usb-ss.yaml b/Documentation/devicetree/bindings/qcom,usb-ss.yaml new file mode 100644 index 000000000000..fb0e399d64a0 --- /dev/null +++ b/Documentation/devicetree/bindings/qcom,usb-ss.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY. + +properties: + +- compatible: + enum: + - qcom,usb-ssphy + + reg: + maxItems: 1 + description: USB PHY base address and length of the register map. + + "#phy-cells": + const: 0 + description: Should be 0. See phy/phy-bindings.txt for details. + + clocks: + items: + - description: Block reference clock + - description: PHY AHB clock + - description: SuperSpeed pipe clock + + clock-names: + items: + - const: ref + - const: phy + - const: sleep + + vdd-supply: + maxItems: 1 + description: phandle to the regulator VDD supply node. + + vdda1p8-supply: + maxItems: 1 + description: phandle to the regulator 1.8V supply node. + + resets: + items: + - description: COM reset + - description: PHY reset line + + reset-names: + items: + - description: com + - description: phy + +Example: + +usb3_phy: usb3-phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x78000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "phy", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; +}; -- 2.24.0